#Build: Synplify Pro G-2012.09L-SP1 , Build 029R, Mar 11 2013 #install: C:\lscc\diamond\2.2\synpbase #OS: Windows XP 5.1 #Hostname: ITLFFERRARI #Implementation: prj_diamond_ver0 $ Start of Compile #Thu Jun 20 21:29:49 2013 Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013 @N: : | Running in 32-bit mode Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. @N: : | : Running Verilog Compiler in System Verilog mode @N: : | : Running Verilog Compiler in Multiple File Compilation Unit mode @I::"C:\lscc\diamond\2.2\synpbase\lib\lucent\machxo2.v" @I::"C:\lscc\diamond\2.2\synpbase\lib\lucent\pmi_def.v" @I::"C:\lscc\diamond\2.2\synpbase\lib\vlog\umr_capim.v" @I::"C:\lscc\diamond\2.2\synpbase\lib\vlog\scemi_objects.v" @I::"C:\lscc\diamond\2.2\synpbase\lib\vlog\scemi_pipes.svh" @I::"C:\lscc\diamond\2.2\synpbase\lib\vlog\hypermods.v" @I::"C:\lscc\diamond\2.2\cae_library\synthesis\verilog\machxo2.v" @I::"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\system_conf.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\pmi_def.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\er1.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\typeb.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\typea.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\jtag_cores.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\jtag_cores.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\jtag_lm32.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_addsub.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_adder.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v" @W:CS141 : lm32_cpu.v(652) | Unrecognized synthesis directive attribute @W:CS141 : lm32_cpu.v(653) | Unrecognized synthesis directive attribute @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_functions.v" @N:CG334 : lm32_cpu.v(2773) | Read directive translate_off @N:CG333 : lm32_cpu.v(2786) | Read directive translate_on @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_dcache.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_debug.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_decoder.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_icache.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v" @W:CS141 : lm32_interrupt.v(130) | Unrecognized synthesis directive attribute @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v" @N:CG334 : lm32_load_store_unit.v(678) | Read directive translate_off @N:CG333 : lm32_load_store_unit.v(681) | Read directive translate_on @N:CG334 : lm32_load_store_unit.v(811) | Read directive translate_off @N:CG333 : lm32_load_store_unit.v(825) | Read directive translate_on @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_logic_op.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_mc_arithmetic.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_multiplier.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_shifter.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_top.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v" @N:CG334 : lm32_monitor_ram.v(597) | Read directive translate_off @N:CG333 : lm32_monitor_ram.v(640) | Read directive translate_on @N:CG334 : lm32_monitor_ram.v(717) | Read directive translate_off @N:CG333 : lm32_monitor_ram.v(760) | Read directive translate_on @N:CG334 : lm32_monitor_ram.v(932) | Read directive translate_off @N:CG333 : lm32_monitor_ram.v(1007) | Read directive translate_on @N:CG334 : lm32_monitor_ram.v(1117) | Read directive translate_off @N:CG333 : lm32_monitor_ram.v(1192) | Read directive translate_on @N:CG334 : lm32_monitor_ram.v(1461) | Read directive translate_off @N:CG333 : lm32_monitor_ram.v(1536) | Read directive translate_on @N:CG334 : lm32_monitor_ram.v(1645) | Read directive translate_off @N:CG333 : lm32_monitor_ram.v(1720) | Read directive translate_on @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_trace.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\uart_core.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\uart_core.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txcver_fifo.v" @N:CG334 : intface.v(953) | Read directive translate_off @N:CG333 : intface.v(1017) | Read directive translate_on @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\uart_core.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver_fifo.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\uart_core.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txmitt.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdram_include_all.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdram_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\wb_sdr_ctrl.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\wb_sdr_ctrl.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_par.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdram_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\wb_fifo_intf.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdram_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_fifo_intf.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdram_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_ctrl.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdram_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdram_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_data.v" Verilog syntax check successful! Selecting top level module platform_rev0 @N:CG364 : platform_rev0.v(48) | Synthesizing module arbiter2 MAX_DAT_WIDTH=32'b00000000000000000000000000100000 WBS_DAT_WIDTH=32'b00000000000000000000000000100000 WBM0_DAT_WIDTH=32'b00000000000000000000000000100000 WBM1_DAT_WIDTH=32'b00000000000000000000000000100000 Generated name = arbiter2_32s_32s_32s_32s @N:CG364 : lm32_instruction_unit.v(77) | Synthesizing module lm32_instruction_unit associativity=32'b00000000000000000000000000000001 sets=32'b00000000000000000000001000000000 bytes_per_line=32'b00000000000000000000000000010000 base_address=32'b00000000000000000000000000000000 limit=32'b00000000000000000000000000000000 addr_offset_width=32'b00000000000000000000000000000010 addr_offset_lsb=32'b00000000000000000000000000000010 addr_offset_msb=32'b00000000000000000000000000000011 Generated name = lm32_instruction_unit_1s_512s_16s_0s_0s_2s_2s_3s @N:CG793 : lm32_instruction_unit.v(824) | Ignoring system task $display @W:CL113 : lm32_instruction_unit.v(792) | Feedback mux created for signal i_lock_o. @W:CL113 : lm32_instruction_unit.v(792) | Feedback mux created for signal i_cti_o[2:0]. @W:CL251 : lm32_instruction_unit.v(792) | All reachable assignments to i_cti_o[2:0] assign 1, register removed by optimization @W:CL250 : lm32_instruction_unit.v(792) | All reachable assignments to i_lock_o assign 0, register removed by optimization @W:CL190 : lm32_instruction_unit.v(792) | Optimizing register bit i_adr_o[0] to a constant 0 @W:CL190 : lm32_instruction_unit.v(792) | Optimizing register bit i_adr_o[1] to a constant 0 @W:CL279 : lm32_instruction_unit.v(792) | Pruning register bits 1 to 0 of i_adr_o[31:0] @N:CG364 : lm32_decoder.v(113) | Synthesizing module lm32_decoder @N:CG364 : lm32_load_store_unit.v(69) | Synthesizing module lm32_load_store_unit associativity=32'b00000000000000000000000000000001 sets=32'b00000000000000000000001000000000 bytes_per_line=32'b00000000000000000000000000010000 base_address=32'b00000000000000000000000000000000 limit=32'b00000000000000000000000000000000 addr_offset_width=32'b00000000000000000000000000000010 addr_offset_lsb=32'b00000000000000000000000000000010 addr_offset_msb=32'b00000000000000000000000000000011 Generated name = lm32_load_store_unit_1s_512s_16s_0s_0s_2s_2s_3s @W:CL190 : lm32_load_store_unit.v(623) | Optimizing register bit d_cti_o[0] to a constant 1 @W:CL190 : lm32_load_store_unit.v(623) | Optimizing register bit d_cti_o[1] to a constant 1 @W:CL190 : lm32_load_store_unit.v(623) | Optimizing register bit d_cti_o[2] to a constant 1 @W:CL190 : lm32_load_store_unit.v(623) | Optimizing register bit d_lock_o to a constant 0 @W:CL169 : lm32_load_store_unit.v(623) | Pruning register d_cti_o[2:0] @W:CL169 : lm32_load_store_unit.v(623) | Pruning register d_lock_o @N:CG364 : lm32_addsub.v(55) | Synthesizing module lm32_addsub @N:CG364 : pmi_def.v(48) | Synthesizing module pmi_addsub pmi_data_width=32'b00000000000000000000000000100000 pmi_result_width=32'b00000000000000000000000000100000 pmi_sign=24'b011011110110011001100110 pmi_family=56'b01001101011000010110001101101000010110000100111100110010 module_type=80'b01110000011011010110100101011111011000010110010001100100011100110111010101100010 Generated name = pmi_addsub_32s_32s_off_MachXO2_pmi_addsub @N:CG364 : lm32_adder.v(56) | Synthesizing module lm32_adder @N:CG364 : lm32_logic_op.v(56) | Synthesizing module lm32_logic_op @N:CG364 : lm32_shifter.v(56) | Synthesizing module lm32_shifter @N:CG364 : lm32_multiplier.v(56) | Synthesizing module lm32_multiplier @N:CG364 : lm32_mc_arithmetic.v(64) | Synthesizing module lm32_mc_arithmetic @N:CG364 : lm32_interrupt.v(56) | Synthesizing module lm32_interrupt @N:CG364 : lm32_jtag.v(87) | Synthesizing module lm32_jtag @W:CL169 : lm32_jtag.v(309) | Pruning register command[3:0] @W:CL113 : lm32_jtag.v(309) | Feedback mux created for signal state[3:0]. @W:CL250 : lm32_jtag.v(309) | All reachable assignments to state[3:0] assign 0, register removed by optimization @N:CG364 : lm32_debug.v(69) | Synthesizing module lm32_debug breakpoints=32'b00000000000000000000000000000000 watchpoints=32'b00000000000000000000000000000000 Generated name = lm32_debug_0s_0 @W:CG133 : lm32_debug.v(164) | No assignment to bp_a_-1_ @W:CG133 : lm32_debug.v(164) | No assignment to bp_a_0_ @W:CG133 : lm32_debug.v(165) | No assignment to bp_e_-1_ @W:CG133 : lm32_debug.v(165) | No assignment to bp_e_0_ @W:CG360 : lm32_debug.v(166) | No assignment to wire bp_match_n @W:CG133 : lm32_debug.v(168) | No assignment to wpc_c[0] @W:CG133 : lm32_debug.v(168) | No assignment to wpc_c[-1] @W:CG133 : lm32_debug.v(169) | No assignment to wp_-1_ @W:CG133 : lm32_debug.v(169) | No assignment to wp_0_ @W:CG360 : lm32_debug.v(170) | No assignment to wire wp_match_n @N:CG364 : lm32_cpu.v(100) | Synthesizing module lm32_cpu @W:CL169 : lm32_cpu.v(2303) | Pruning register x_result_sel_logic_x @W:CL169 : lm32_cpu.v(2303) | Pruning register eret_m @W:CL169 : lm32_cpu.v(2303) | Pruning register bret_m @N:CG364 : lm32_monitor_ram.v(53) | Synthesizing module lm32_monitor_ram @N:CG364 : machxo2.v(1291) | Synthesizing module DP8KC @N:CG364 : machxo2.v(1120) | Synthesizing module VHI @N:CG364 : machxo2.v(1124) | Synthesizing module VLO @N:CG364 : lm32_monitor.v(57) | Synthesizing module lm32_monitor @A:CL282 : lm32_monitor.v(143) | Feedback mux created for signal write_data[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @N:CG364 : jtag_cores.v(60) | Synthesizing module jtagconn16 @W:CG146 : jtag_cores.v(60) | Creating black box for empty module jtagconn16 @N:CG364 : typea.v(65) | Synthesizing module TYPEA @N:CG364 : jtag_lm32.v(51) | Synthesizing module jtag_lm32 @N:CG364 : jtag_cores.v(75) | Synthesizing module jtag_cores @W:CG781 : jtag_cores.v(146) | Undriven input CONTROL_DATAN on instance jtag_lm32_inst, tying to 0 @N:CG364 : lm32_top.v(58) | Synthesizing module lm32_top @N:CG364 : intface.v(321) | Synthesizing module intface CLK_IN_MHZ=72'b001100100011010100101110001100000011000000110000001100000011000000110000 UART_WB_ADR_WIDTH=32'b00000000000000000000000000000100 UART_WB_DAT_WIDTH=32'b00000000000000000000000000001000 BAUD_RATE=32'b00000000000000011100001000000000 FIFO=32'b00000000000000000000000000000000 LCR_DATA_BITS=32'b00000000000000000000000000001000 LCR_STOP_BITS=32'b00000000000000000000000000000001 LCR_PARITY_ENABLE=32'b00000000000000000000000000000000 LCR_PARITY_ODD=32'b00000000000000000000000000000000 LCR_PARITY_STICK=32'b00000000000000000000000000000000 LCR_SET_BREAK=32'b00000000000000000000000000000000 STDOUT_SIM=32'b00000000000000000000000000000000 STDOUT_SIMFAST=32'b00000000000000000000000000000000 A_RBR=4'b0000 A_THR=4'b0000 A_IER=4'b0001 A_IIR=4'b0010 A_LCR=4'b0011 A_LSR=4'b0101 A_DIV=3'b100 idle=3'b000 int0=3'b001 int1=3'b010 int2=3'b011 int3=3'b100 Generated name = intface_Z1 @W:CG813 : intface.v(501) | Rounding real from 217.013889 to 217 (simulation mismatch possible) @W:CG360 : intface.v(382) | No assignment to wire fifo_empty_thr @W:CG360 : intface.v(383) | No assignment to wire fifo_full_thr @W:CG360 : intface.v(436) | No assignment to wire thr_fifo @W:CG133 : intface.v(466) | No assignment to iir_rd_strobe_delay @W:CG133 : intface.v(469) | No assignment to lsr2_r @W:CG133 : intface.v(469) | No assignment to lsr3_r @W:CG133 : intface.v(469) | No assignment to lsr4_r @W:CG360 : intface.v(491) | No assignment to wire fifo_almost_full_thr @W:CG360 : intface.v(492) | No assignment to wire fifo_almost_empty_thr @W:CG360 : intface.v(493) | No assignment to wire fifo_din_thr @W:CG133 : intface.v(494) | No assignment to fifo_wr_thr @W:CG133 : intface.v(495) | No assignment to fifo_wr_q_thr @W:CG360 : intface.v(496) | No assignment to wire fifo_wr_pulse_thr @N:CG364 : rxcver.v(94) | Synthesizing module rxcver UART_WB_DAT_WIDTH=32'b00000000000000000000000000001000 FIFO=32'b00000000000000000000000000000000 idle=3'b000 shift=3'b001 parity=3'b010 stop=3'b011 idle1=3'b100 lat_family=56'b01001101011000010110001101101000010110000100111100110010 Generated name = rxcver_8s_0s_0_1_2_3_4_MachXO2 @W:CG360 : rxcver.v(134) | No assignment to wire rbr_fifo @W:CG360 : rxcver.v(141) | No assignment to wire fifo_empty @W:CG360 : rxcver.v(142) | No assignment to wire fifo_almost_full @W:CG133 : rxcver.v(151) | No assignment to count @W:CG133 : rxcver.v(163) | No assignment to rxclk_en @W:CG360 : rxcver.v(166) | No assignment to wire rbr_fifo_error @W:CG360 : rxcver.v(181) | No assignment to wire fifo_full @W:CG360 : rxcver.v(184) | No assignment to wire fifo_almost_empty @W:CG133 : rxcver.v(185) | No assignment to fifo_din @W:CG133 : rxcver.v(186) | No assignment to fifo_wr @W:CG133 : rxcver.v(187) | No assignment to fifo_wr_q @W:CG360 : rxcver.v(188) | No assignment to wire fifo_wr_pulse @N:CL177 : rxcver.v(472) | Sharing sequential element sin_d0_delay. @N:CG364 : txmitt.v(103) | Synthesizing module txmitt UART_WB_DAT_WIDTH=32'b00000000000000000000000000001000 FIFO=32'b00000000000000000000000000000000 start=3'b000 shift=3'b001 parity=3'b010 stop_1bit=3'b011 stop_2bit=3'b100 stop_halfbit=3'b101 start1=3'b110 Generated name = txmitt_8s_0s_0_1_2_3_4_5_6 @W:CG133 : txmitt.v(150) | No assignment to tx_in_start_s @W:CG133 : txmitt.v(155) | No assignment to txclk_ena @W:CG133 : txmitt.v(156) | No assignment to txclk_enb @W:CG133 : txmitt.v(158) | No assignment to count_v @W:CG133 : txmitt.v(159) | No assignment to thr_rd_int @W:CG133 : txmitt.v(160) | No assignment to thr_rd_delay @W:CG133 : txmitt.v(161) | No assignment to last_word @N:CG364 : uart_core.v(131) | Synthesizing module uart_core CLK_IN_MHZ=72'b001100100011010100101110001100000011000000110000001100000011000000110000 UART_WB_ADR_WIDTH=32'b00000000000000000000000000000100 UART_WB_DAT_WIDTH=32'b00000000000000000000000000001000 BAUD_RATE=32'b00000000000000011100001000000000 FIFO=32'b00000000000000000000000000000000 LCR_DATA_BITS=32'b00000000000000000000000000001000 LCR_STOP_BITS=32'b00000000000000000000000000000001 LCR_PARITY_ENABLE=32'b00000000000000000000000000000000 LCR_PARITY_ODD=32'b00000000000000000000000000000000 LCR_PARITY_STICK=32'b00000000000000000000000000000000 LCR_SET_BREAK=32'b00000000000000000000000000000000 STDOUT_SIM=32'b00000000000000000000000000000000 STDOUT_SIMFAST=32'b00000000000000000000000000000000 Generated name = uart_core_Z2 @N:CG364 : pmi_def.v(210) | Synthesizing module pmi_pll_fp @N:CG364 : pmi_def.v(154) | Synthesizing module pmi_fifo_dc pmi_data_width_w=32'b00000000000000000000000001000101 pmi_data_width_r=32'b00000000000000000000000001000101 pmi_data_depth_w=32'b00000000000000000000000000010000 pmi_data_depth_r=32'b00000000000000000000000000010000 pmi_full_flag=32'b00000000000000000000000000010000 pmi_empty_flag=32'b00000000000000000000000000000000 pmi_almost_full_flag=32'b00000000000000000000000000001111 pmi_almost_empty_flag=32'b00000000000000000000000000000001 pmi_regmode=40'b0110111001101111011100100110010101100111 pmi_resetmode=40'b0110000101110011011110010110111001100011 pmi_family=56'b01001101011000010110001101101000010110000100111100110010 module_type=88'b0111000001101101011010010101111101100110011010010110011001101111010111110110010001100011 pmi_implementation=24'b010011000101010101010100 Generated name = pmi_fifo_dc_Z3 @N:CG364 : pmi_def.v(154) | Synthesizing module pmi_fifo_dc pmi_data_width_w=32'b00000000000000000000000000100000 pmi_data_width_r=32'b00000000000000000000000000100000 pmi_data_depth_w=32'b00000000000000000000000000010000 pmi_data_depth_r=32'b00000000000000000000000000010000 pmi_full_flag=32'b00000000000000000000000000010000 pmi_empty_flag=32'b00000000000000000000000000000000 pmi_almost_full_flag=32'b00000000000000000000000000001011 pmi_almost_empty_flag=32'b00000000000000000000000000000001 pmi_regmode=40'b0110111001101111011100100110010101100111 pmi_resetmode=40'b0110000101110011011110010110111001100011 pmi_family=56'b01001101011000010110001101101000010110000100111100110010 module_type=88'b0111000001101101011010010101111101100110011010010110011001101111010111110110010001100011 pmi_implementation=24'b010011000101010101010100 Generated name = pmi_fifo_dc_Z4 @N:CG364 : wb_fifo_intf.v(54) | Synthesizing module wb_fifo_intf @N:CG364 : sdr_ctrl.v(54) | Synthesizing module sdr_ctrl @N:CG364 : sdr_sig.v(56) | Synthesizing module sdr_sig @W:CL271 : sdr_sig.v(147) | Pruning bits 31 to 23 of sys_A[31:0] -- not in use ... @N:CG364 : sdr_data.v(56) | Synthesizing module sdr_data @N:CG364 : machxo2.v(82) | Synthesizing module BB @W:CL271 : sdr_data.v(127) | Pruning bits 10 to 1 of rd_dat_cnt[10:0] -- not in use ... @N:CG364 : sdr_fifo_intf.v(56) | Synthesizing module sdr_fifo_intf @N:CG364 : wb_sdr_ctrl.v(57) | Synthesizing module wb_sdr_ctrl SYS_FREQ=32'b00110010001101010010111000110000 SDRAM_FREQ=24'b001100010011000000110000 LATTICE_FAMILY=56'b01001101011000010110001101101000010110000100111100110010 LATTICE_DEVICE=24'b010000010110110001101100 NUM_CLK_WAIT=32'b00000000000000000000000000000001 NUM_CLK_CL=3'b011 NUM_CLK_READ=32'b00000000000000000000000000000010 NUM_CLK_WRITE=32'b00000000000000000000000000000010 i_NOP=4'b0000 i_PRE=4'b0001 i_tRP=4'b0010 i_AR1=4'b0011 i_tRFC1=4'b0100 i_AR2=4'b0101 i_tRFC2=4'b0110 i_MRS=4'b0111 i_tMRD=4'b1000 i_ready=4'b1001 c_idle=4'b0000 c_tRCD=4'b0001 c_cl=4'b0010 c_rdata=4'b0011 c_wdata=4'b0100 c_tRFC=4'b0101 c_tDAL=4'b0110 c_ACTIVE=4'b1000 c_READA=4'b1111 c_WRITEA=4'b1110 c_AR=4'b1011 c_ReWait=4'b1100 c_PRECH=4'b1001 c_tRP=4'b1010 INHIBIT=4'b1111 NOP=4'b0111 ACTIVE=4'b0011 READ=4'b0101 WRITE=4'b0100 BURST_TERMINATE=4'b0110 PRECHARGE=4'b0010 AUTO_REFRESH=4'b0001 LOAD_MODE_REGISTER=4'b0000 tDLY=32'b00000000000000000000000000000010 READ_FIFO_DEPTH=32'b00000000000000000000000000010000 READ_FIFO_ALMOST_FULL=32'b00000000000000000000000000001011 WRITE_FIFO_DEPTH=32'b00000000000000000000000000010000 WRITE_FIFO_ALMOST_EMPTY=32'b00000000000000000000000000000001 Generated name = wb_sdr_ctrl_Z5 @N:CG179 : wb_sdr_ctrl.v(308) | Removing redundant assignment @N:CG364 : platform_rev0.v(332) | Synthesizing module platform_rev0 @W:CG133 : platform_rev0.v(348) | No assignment to i @W:CG360 : platform_rev0.v(364) | No assignment to wire SHAREDBUS_en @W:CL157 : wb_sdr_ctrl.v(121) | *Output sdr_CLK has undriven bits -- simulation mismatch possible. @W:CL247 : sdr_data.v(77) | Input port bit 68 of wb2sdr_q[68:0] is unused @W:CL246 : sdr_data.v(77) | Input port bits 31 to 0 of wb2sdr_q[68:0] are unused @W:CL159 : sdr_data.v(78) | Input sdr2wb_full is unused @W:CL279 : sdr_sig.v(147) | Pruning register bits 1 to 0 of sys_A[22:0] @W:CL246 : sdr_sig.v(102) | Input port bits 68 to 23 of wb2sdr_q[68:0] are unused @W:CL246 : sdr_sig.v(102) | Input port bits 1 to 0 of wb2sdr_q[68:0] are unused @N:CL201 : sdr_ctrl.v(244) | Trying to extract state machine for register cState Extracted state machine for register cState State machine has 14 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 1000 1001 1010 1011 1100 1110 1111 @N:CL201 : sdr_ctrl.v(162) | Trying to extract state machine for register iState Extracted state machine for register iState State machine has 10 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 @W:CL246 : sdr_ctrl.v(82) | Input port bits 67 to 0 of wb2sdr_q[68:0] are unused @N:CL201 : wb_fifo_intf.v(135) | Trying to extract state machine for register wb_status Extracted state machine for register wb_status State machine has 4 reachable states with original encodings of: 00 01 10 11 @W:CL159 : wb_fifo_intf.v(92) | Input S_BTE_I is unused @W:CL159 : wb_fifo_intf.v(93) | Input S_LOCK_I is unused @W:CL159 : wb_fifo_intf.v(103) | Input wb2sdr_empty is unused @W:CL159 : uart_core.v(155) | Input UART_LOCK_I is unused @W:CL159 : uart_core.v(160) | Input UART_SEL_I is unused @N:CL201 : txmitt.v(333) | Trying to extract state machine for register genblk2.genblk1.tx_state Extracted state machine for register genblk2.genblk1.tx_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @W:CL159 : txmitt.v(135) | Input fifo_empty_thr is unused @W:CL159 : txmitt.v(136) | Input fifo_full_thr is unused @N:CL201 : rxcver.v(315) | Trying to extract state machine for register cs_state Extracted state machine for register cs_state State machine has 5 reachable states with original encodings of: 000 001 010 011 100 @W:CL157 : rxcver.v(134) | *Output rbr_fifo has undriven bits -- simulation mismatch possible. @W:CL157 : rxcver.v(141) | *Output fifo_empty has undriven bits -- simulation mismatch possible. @W:CL157 : rxcver.v(142) | *Output fifo_almost_full has undriven bits -- simulation mismatch possible. @N:CL201 : intface.v(874) | Trying to extract state machine for register genblk22.cs_state Extracted state machine for register genblk22.cs_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @W:CL157 : intface.v(382) | *Output fifo_empty_thr has undriven bits -- simulation mismatch possible. @W:CL157 : intface.v(383) | *Output fifo_full_thr has undriven bits -- simulation mismatch possible. @W:CL159 : intface.v(344) | Input cti_i is unused @W:CL159 : intface.v(345) | Input bte_i is unused @W:CL159 : intface.v(355) | Input rbr_fifo is unused @W:CL159 : intface.v(381) | Input fifo_empty is unused @W:CL159 : intface.v(384) | Input thr_rd is unused @W:CL159 : intface.v(385) | Input fifo_almost_full is unused @W:CL246 : lm32_top.v(168) | Input port bits 31 to 14 of DEBUG_ADR_I[31:0] are unused @W:CL246 : lm32_top.v(168) | Input port bits 12 to 11 of DEBUG_ADR_I[31:0] are unused @W:CL246 : lm32_top.v(168) | Input port bits 1 to 0 of DEBUG_ADR_I[31:0] are unused @W:CL159 : lm32_top.v(172) | Input DEBUG_CTI_I is unused @W:CL159 : lm32_top.v(173) | Input DEBUG_BTE_I is unused @W:CL159 : lm32_top.v(174) | Input DEBUG_LOCK_I is unused @W:CL159 : jtag_lm32.v(60) | Input CONTROL_DATAN is unused @N:CL201 : lm32_monitor.v(143) | Trying to extract state machine for register state Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @N:CL134 : lm32_cpu.v(2664) | Found RAM registers, depth=32, width=32 @N:CL134 : lm32_cpu.v(2664) | Found RAM registers, depth=32, width=32 @W:CL159 : lm32_cpu.v(279) | Input I_RTY_I is unused @W:CL246 : lm32_debug.v(123) | Input port bits 31 to 2 of csr_write_data[31:0] are unused @W:CL247 : lm32_debug.v(123) | Input port bit 0 of csr_write_data[31:0] is unused @W:CL159 : lm32_debug.v(118) | Input pc_x is unused @W:CL159 : lm32_debug.v(119) | Input load_x is unused @W:CL159 : lm32_debug.v(120) | Input store_x is unused @W:CL159 : lm32_debug.v(121) | Input load_store_address_x is unused @W:CL246 : lm32_jtag.v(151) | Input port bits 31 to 8 of csr_write_data[31:0] are unused @W:CL159 : lm32_jtag.v(139) | Input jtag_clk is unused @N:CL201 : lm32_mc_arithmetic.v(169) | Trying to extract state machine for register state Extracted state machine for register state State machine has 3 reachable states with original encodings of: 000 010 011 @W:CL246 : lm32_shifter.v(79) | Input port bits 31 to 5 of operand_1_x[31:0] are unused @W:CL246 : lm32_load_store_unit.v(159) | Input port bits 31 to 2 of load_store_address_x[31:0] are unused @W:CL159 : lm32_load_store_unit.v(152) | Input stall_a is unused @W:CL159 : lm32_load_store_unit.v(162) | Input load_x is unused @W:CL159 : lm32_load_store_unit.v(163) | Input store_x is unused @W:CL159 : lm32_load_store_unit.v(165) | Input store_q_x is unused @W:CL159 : lm32_load_store_unit.v(182) | Input d_rty_i is unused @W:CL159 : lm32_instruction_unit.v(204) | Input valid_f is unused @W:CL159 : lm32_instruction_unit.v(206) | Input kill_f is unused @N:CL201 : platform_rev0.v(246) | Trying to extract state machine for register selected Extracted state machine for register selected State machine has 3 reachable states with original encodings of: 00 01 10 @END Process took 0h:00m:04s realtime, 0h:00m:04s cputime # Thu Jun 20 21:29:54 2013 ###########################################################]