Setting log file to 'C:/work/project/artekit_demos/forza4_rev0/diamond/prj_diamond_ver0/hdla_gen_hierarchy.html'.
INFO: (VHDL-1504) The default vhdl library search path is now "C:/lscc/diamond/2.2/cae_library/vhdl_packages/vdbs"
-- (VERI-1482) Analyzing Verilog file C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v
-- (VERI-1482) Analyzing Verilog file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/platform_rev0.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/platform_rev0.v(46,10-46,25) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/system_conf.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/platform_rev0.v(327,10-327,65) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(52,10-52,21) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/pmi_def.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(54,10-54,25) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/system_conf.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(57,12-57,54) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/er1.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(58,12-58,56) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typeb.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(59,12-59,56) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(60,12-60,61) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/jtag_cores.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/jtag_cores.v(53,10-53,25) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/system_conf.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/jtag_cores.v(54,10-54,26) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include.v(60,10-60,25) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/system_conf.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(61,12-61,60) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/jtag_lm32.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(62,12-62,60) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_jtag.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_jtag.v(52,10-52,26) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(65,10-65,60) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_addsub.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_addsub.v(49,10-49,26) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(66,10-66,59) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_adder.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_adder.v(50,10-50,26) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(67,10-67,57) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_cpu.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_cpu.v(94,10-94,26) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_cpu.v(791,10-791,28) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_functions.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_functions.v(54,9-54,14) WARNING: (VERI-1214) assignment to input value
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(68,10-68,60) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_dcache.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_dcache.v(52,10-52,26) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(69,10-69,59) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_debug.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_debug.v(53,10-53,26) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_debug.v(186,10-186,28) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_functions.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(70,10-70,61) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_decoder.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_decoder.v(56,10-56,26) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_decoder.v(336,10-336,28) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_functions.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(71,10-71,60) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_icache.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_icache.v(57,10-57,26) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(72,10-72,70) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_instruction_unit.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_instruction_unit.v(71,10-71,26) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_instruction_unit.v(380,10-380,28) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_functions.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(73,10-73,63) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_interrupt.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_interrupt.v(50,10-50,26) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(74,10-74,69) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_load_store_unit.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_load_store_unit.v(63,10-63,26) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_load_store_unit.v(283,10-283,28) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_functions.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(75,10-75,62) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_logic_op.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_logic_op.v(50,10-50,26) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(77,10-77,67) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_mc_arithmetic.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_mc_arithmetic.v(50,10-50,26) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(80,12-80,66) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_multiplier.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_multiplier.v(50,10-50,26) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(83,12-83,63) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_shifter.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_shifter.v(50,10-50,26) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(85,10-85,57) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_top.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_top.v(52,10-52,26) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_top.v(277,10-277,28) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_functions.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(87,12-87,63) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_monitor.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_monitor.v(50,10-50,25) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/system_conf.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_monitor.v(51,10-51,26) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(88,12-88,67) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_monitor_ram.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_monitor_ram.v(51,10-51,25) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/system_conf.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v(105,12-105,61) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_trace.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_trace.v(52,10-52,26) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_include.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_trace.v(53,10-53,25) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/system_conf.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/platform_rev0.v(328,10-328,59) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/uart_core.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/uart_core.v(124,10-124,25) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/system_conf.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/uart_core.v(125,10-125,21) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/intface.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/intface.v(319,10-319,25) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/system_conf.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/intface.v(320,10-320,25) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/txcver_fifo.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/txcver_fifo.v(51,10-51,25) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/system_conf.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/intface.v(510,4-510,30) WARNING: (VERI-1199) parameter declaration becomes local in intface with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/intface.v(511,4-511,30) WARNING: (VERI-1199) parameter declaration becomes local in intface with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/intface.v(512,4-512,30) WARNING: (VERI-1199) parameter declaration becomes local in intface with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/intface.v(513,4-513,30) WARNING: (VERI-1199) parameter declaration becomes local in intface with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/intface.v(514,4-514,30) WARNING: (VERI-1199) parameter declaration becomes local in intface with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/intface.v(515,4-515,30) WARNING: (VERI-1199) parameter declaration becomes local in intface with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/intface.v(516,4-516,30) WARNING: (VERI-1199) parameter declaration becomes local in intface with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/intface.v(819,4-819,29) WARNING: (VERI-1199) parameter declaration becomes local in intface with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/intface.v(820,4-820,29) WARNING: (VERI-1199) parameter declaration becomes local in intface with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/intface.v(821,4-821,29) WARNING: (VERI-1199) parameter declaration becomes local in intface with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/intface.v(822,4-822,29) WARNING: (VERI-1199) parameter declaration becomes local in intface with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/intface.v(823,4-823,29) WARNING: (VERI-1199) parameter declaration becomes local in intface with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/uart_core.v(126,10-126,20) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/rxcver.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/rxcver.v(92,10-92,25) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/system_conf.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/rxcver.v(93,10-93,25) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/rxcver_fifo.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/rxcver_fifo.v(52,10-52,25) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/system_conf.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/rxcver.v(172,4-172,31) WARNING: (VERI-1199) parameter declaration becomes local in rxcver with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/rxcver.v(173,4-173,31) WARNING: (VERI-1199) parameter declaration becomes local in rxcver with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/rxcver.v(174,4-174,31) WARNING: (VERI-1199) parameter declaration becomes local in rxcver with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/rxcver.v(175,4-175,31) WARNING: (VERI-1199) parameter declaration becomes local in rxcver with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/rxcver.v(176,4-176,33) WARNING: (VERI-1199) parameter declaration becomes local in rxcver with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/rxcver.v(179,4-179,46) WARNING: (VERI-1199) parameter declaration becomes local in rxcver with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/uart_core.v(127,10-127,20) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/txmitt.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/txmitt.v(102,10-102,25) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/system_conf.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/txmitt.v(164,3-164,35) WARNING: (VERI-1199) parameter declaration becomes local in txmitt with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/txmitt.v(165,3-165,35) WARNING: (VERI-1199) parameter declaration becomes local in txmitt with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/txmitt.v(166,3-166,35) WARNING: (VERI-1199) parameter declaration becomes local in txmitt with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/txmitt.v(167,3-167,35) WARNING: (VERI-1199) parameter declaration becomes local in txmitt with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/txmitt.v(168,3-168,35) WARNING: (VERI-1199) parameter declaration becomes local in txmitt with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/txmitt.v(169,3-169,35) WARNING: (VERI-1199) parameter declaration becomes local in txmitt with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/txmitt.v(170,3-170,35) WARNING: (VERI-1199) parameter declaration becomes local in txmitt with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/platform_rev0.v(329,10-329,69) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdram_include_all.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdram_include_all.v(37,10-37,25) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/system_conf.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdram_include_all.v(38,10-38,25) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/wb_sdr_ctrl.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/wb_sdr_ctrl.v(93,10-93,21) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(122,1-122,62) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(124,1-124,45) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(132,1-132,31) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(133,1-133,31) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(150,1-150,29) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(151,1-151,29) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(152,1-152,29) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(153,1-153,29) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(154,1-154,29) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(155,1-155,29) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(156,1-156,29) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(157,1-157,29) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(158,1-158,29) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(159,1-159,29) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(165,1-165,30) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(166,1-166,30) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(167,1-167,30) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(168,1-168,30) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(169,1-169,30) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(170,1-170,30) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(171,1-171,30) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(172,1-172,30) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(173,1-173,30) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(174,1-174,30) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(175,1-175,30) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(176,1-176,30) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(177,1-177,30) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(178,1-178,30) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(183,1-183,40) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(184,1-184,40) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(185,1-185,40) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(186,1-186,40) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(187,1-187,40) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(188,1-188,40) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(189,1-189,40) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(190,1-190,40) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(191,1-191,40) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v(194,1-194,20) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/wb_sdr_ctrl.v(287,1-287,32) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/wb_sdr_ctrl.v(288,1-288,77) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/wb_sdr_ctrl.v(289,1-289,33) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/wb_sdr_ctrl.v(290,1-290,39) WARNING: (VERI-1199) parameter declaration becomes local in wb_sdr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdram_include_all.v(39,10-39,26) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/wb_fifo_intf.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/wb_fifo_intf.v(84,10-84,21) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdram_include_all.v(40,10-40,27) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_fifo_intf.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_fifo_intf.v(88,10-88,21) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdram_include_all.v(41,10-41,22) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_ctrl.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_ctrl.v(78,10-78,21) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdram_include_all.v(42,10-42,21) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_sig.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_sig.v(74,10-74,21) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdram_include_all.v(43,10-43,22) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_data.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_data.v(70,10-70,21) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_par.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/platform_rev0.v(330,10-330,63) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(82,11-82,26) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/system_conf.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(122,4-122,43) WARNING: (VERI-1199) parameter declaration becomes local in wb_ebr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(123,4-123,23) WARNING: (VERI-1199) parameter declaration becomes local in wb_ebr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(124,4-124,89) WARNING: (VERI-1199) parameter declaration becomes local in wb_ebr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(125,4-125,71) WARNING: (VERI-1199) parameter declaration becomes local in wb_ebr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(126,4-126,32) WARNING: (VERI-1199) parameter declaration becomes local in wb_ebr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(127,4-127,32) WARNING: (VERI-1199) parameter declaration becomes local in wb_ebr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(128,4-128,32) WARNING: (VERI-1199) parameter declaration becomes local in wb_ebr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(129,4-129,32) WARNING: (VERI-1199) parameter declaration becomes local in wb_ebr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(130,4-130,32) WARNING: (VERI-1199) parameter declaration becomes local in wb_ebr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(131,4-131,32) WARNING: (VERI-1199) parameter declaration becomes local in wb_ebr_ctrl with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/platform_rev0.v(331,10-331,59) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash.v(121,12-121,17) WARNING: (VERI-1214) assignment to input value
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash.v(125,4-125,91) WARNING: (VERI-1199) parameter declaration becomes local in spi_flash with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash.v(126,4-126,78) WARNING: (VERI-1199) parameter declaration becomes local in spi_flash with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash.v(127,4-127,111) WARNING: (VERI-1199) parameter declaration becomes local in spi_flash with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash.v(128,4-128,143) WARNING: (VERI-1199) parameter declaration becomes local in spi_flash with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/platform_rev0.v(332,10-332,57) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/wb_intf.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/wb_intf.v(173,4-173,31) WARNING: (VERI-1199) parameter declaration becomes local in wb_intf with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/wb_intf.v(174,4-174,31) WARNING: (VERI-1199) parameter declaration becomes local in wb_intf with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/wb_intf.v(175,4-175,31) WARNING: (VERI-1199) parameter declaration becomes local in wb_intf with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/wb_intf.v(177,4-177,30) WARNING: (VERI-1199) parameter declaration becomes local in wb_intf with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/wb_intf.v(178,4-178,30) WARNING: (VERI-1199) parameter declaration becomes local in wb_intf with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/platform_rev0.v(333,10-333,64) INFO: (VERI-1328) analyzing included file C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash_intf.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash_intf.v(93,4-93,33) WARNING: (VERI-1199) parameter declaration becomes local in spi_flash_intf with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash_intf.v(94,4-94,33) WARNING: (VERI-1199) parameter declaration becomes local in spi_flash_intf with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash_intf.v(95,4-95,33) WARNING: (VERI-1199) parameter declaration becomes local in spi_flash_intf with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash_intf.v(96,4-96,33) WARNING: (VERI-1199) parameter declaration becomes local in spi_flash_intf with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash_intf.v(98,4-98,34) WARNING: (VERI-1199) parameter declaration becomes local in spi_flash_intf with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash_intf.v(99,4-99,34) WARNING: (VERI-1199) parameter declaration becomes local in spi_flash_intf with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash_intf.v(100,4-100,34) WARNING: (VERI-1199) parameter declaration becomes local in spi_flash_intf with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash_intf.v(101,4-101,34) WARNING: (VERI-1199) parameter declaration becomes local in spi_flash_intf with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash_intf.v(102,4-102,34) WARNING: (VERI-1199) parameter declaration becomes local in spi_flash_intf with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash_intf.v(103,4-103,34) WARNING: (VERI-1199) parameter declaration becomes local in spi_flash_intf with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash_intf.v(104,4-104,34) WARNING: (VERI-1199) parameter declaration becomes local in spi_flash_intf with formal parameter declaration list
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash_intf.v(106,4-106,29) WARNING: (VERI-1199) parameter declaration becomes local in spi_flash_intf with formal parameter declaration list
-- (VERI-1482) Analyzing Verilog file C:/work/project/artekit_demos/forza4_rev0/diamond/pll_fabrizio.v
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/er1.v(65,8-65,11) INFO: (VERI-1018) compiling module ER1
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/er1.v(65,1-251,10) INFO: (VERI-9000) elaborating module 'ER1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typeb.v(51,1-78,10) INFO: (VERI-9000) elaborating module 'TYPEB_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typeb.v(51,1-78,10) INFO: (VERI-9000) elaborating module 'TYPEB_uniq_2'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typeb.v(51,1-78,10) INFO: (VERI-9000) elaborating module 'TYPEB_uniq_3'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_2'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_3'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_4'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_5'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_6'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/platform_rev0.v(336,8-336,21) INFO: (VERI-1018) compiling module platform_rev0
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/platform_rev0.v(336,1-789,10) INFO: (VERI-9000) elaborating module 'platform_rev0'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/platform_rev0.v(48,1-325,10) INFO: (VERI-9000) elaborating module 'arbiter2_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_top.v(58,1-435,10) INFO: (VERI-9000) elaborating module 'lm32_top_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/uart_core.v(131,1-364,10) INFO: (VERI-9000) elaborating module 'uart_core_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/wb_sdr_ctrl.v(57,1-406,10) INFO: (VERI-9000) elaborating module 'wb_sdr_ctrl_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(83,1-483,10) INFO: (VERI-9000) elaborating module 'wb_ebr_ctrl_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash.v(47,1-408,10) INFO: (VERI-9000) elaborating module 'spi_flash_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_cpu.v(100,1-2788,10) INFO: (VERI-9000) elaborating module 'lm32_cpu_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_monitor.v(57,1-190,10) INFO: (VERI-9000) elaborating module 'lm32_monitor_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/jtag_cores.v(75,23-154,10) INFO: (VERI-9000) elaborating module 'jtag_cores_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/intface.v(321,1-1019,10) INFO: (VERI-9000) elaborating module 'intface_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/rxcver.v(94,1-588,10) INFO: (VERI-9000) elaborating module 'rxcver_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/txmitt.v(103,1-593,10) INFO: (VERI-9000) elaborating module 'txmitt_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/wb_fifo_intf.v(54,1-173,10) INFO: (VERI-9000) elaborating module 'wb_fifo_intf_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_fifo_intf.v(56,1-180,10) INFO: (VERI-9000) elaborating module 'sdr_fifo_intf_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/wb_intf.v(49,1-1323,10) INFO: (VERI-9000) elaborating module 'wb_intf_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash_intf.v(47,1-593,10) INFO: (VERI-9000) elaborating module 'spi_flash_intf_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_instruction_unit.v(77,1-889,10) INFO: (VERI-9000) elaborating module 'lm32_instruction_unit_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_decoder.v(113,1-603,10) INFO: (VERI-9000) elaborating module 'lm32_decoder_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_load_store_unit.v(69,1-827,10) INFO: (VERI-9000) elaborating module 'lm32_load_store_unit_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_adder.v(56,1-135,10) INFO: (VERI-9000) elaborating module 'lm32_adder_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_logic_op.v(56,1-96,10) INFO: (VERI-9000) elaborating module 'lm32_logic_op_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_shifter.v(56,1-155,10) INFO: (VERI-9000) elaborating module 'lm32_shifter_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_multiplier.v(56,1-120,10) INFO: (VERI-9000) elaborating module 'lm32_multiplier_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_mc_arithmetic.v(64,1-309,10) INFO: (VERI-9000) elaborating module 'lm32_mc_arithmetic_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_interrupt.v(56,1-355,10) INFO: (VERI-9000) elaborating module 'lm32_interrupt_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_jtag.v(87,1-587,10) INFO: (VERI-9000) elaborating module 'lm32_jtag_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_debug.v(69,1-367,10) INFO: (VERI-9000) elaborating module 'lm32_debug_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_monitor_ram.v(53,1-1986,10) INFO: (VERI-9000) elaborating module 'lm32_monitor_ram_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/jtag_lm32.v(51,1-3083,10) INFO: (VERI-9000) elaborating module 'jtag_lm32_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_ctrl.v(54,1-368,10) INFO: (VERI-9000) elaborating module 'sdr_ctrl_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_sig.v(56,1-272,10) INFO: (VERI-9000) elaborating module 'sdr_sig_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_data.v(56,1-336,10) INFO: (VERI-9000) elaborating module 'sdr_data_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_addsub.v(55,1-114,10) INFO: (VERI-9000) elaborating module 'lm32_addsub_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_7'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_8'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_9'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_10'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_11'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_12'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_13'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_14'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_15'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_16'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_17'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/platform_rev0.v(336,1-789,10) INFO: (VERI-9000) elaborating module 'platform_rev0'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/platform_rev0.v(48,1-325,10) INFO: (VERI-9000) elaborating module 'arbiter2_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_top.v(58,1-435,10) INFO: (VERI-9000) elaborating module 'lm32_top_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/uart_core.v(131,1-364,10) INFO: (VERI-9000) elaborating module 'uart_core_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/wb_sdr_ctrl.v(57,1-406,10) INFO: (VERI-9000) elaborating module 'wb_sdr_ctrl_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(83,1-483,10) INFO: (VERI-9000) elaborating module 'wb_ebr_ctrl_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash.v(47,1-408,10) INFO: (VERI-9000) elaborating module 'spi_flash_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_cpu.v(100,1-2788,10) INFO: (VERI-9000) elaborating module 'lm32_cpu_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_monitor.v(57,1-190,10) INFO: (VERI-9000) elaborating module 'lm32_monitor_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/jtag_cores.v(75,23-154,10) INFO: (VERI-9000) elaborating module 'jtag_cores_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/intface.v(321,1-1019,10) INFO: (VERI-9000) elaborating module 'intface_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/rxcver.v(94,1-588,10) INFO: (VERI-9000) elaborating module 'rxcver_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/uart_core/rtl/verilog/txmitt.v(103,1-593,10) INFO: (VERI-9000) elaborating module 'txmitt_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/wb_fifo_intf.v(54,1-173,10) INFO: (VERI-9000) elaborating module 'wb_fifo_intf_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_fifo_intf.v(56,1-180,10) INFO: (VERI-9000) elaborating module 'sdr_fifo_intf_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/wb_intf.v(49,1-1323,10) INFO: (VERI-9000) elaborating module 'wb_intf_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/spi_flash/rtl/verilog/spi_flash_intf.v(47,1-593,10) INFO: (VERI-9000) elaborating module 'spi_flash_intf_uniq_1'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(1601,1-1606,10) INFO: (VERI-9000) elaborating module 'ODDRXE_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_instruction_unit.v(77,1-889,10) INFO: (VERI-9000) elaborating module 'lm32_instruction_unit_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_decoder.v(113,1-603,10) INFO: (VERI-9000) elaborating module 'lm32_decoder_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_load_store_unit.v(69,1-827,10) INFO: (VERI-9000) elaborating module 'lm32_load_store_unit_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_adder.v(56,1-135,10) INFO: (VERI-9000) elaborating module 'lm32_adder_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_logic_op.v(56,1-96,10) INFO: (VERI-9000) elaborating module 'lm32_logic_op_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_shifter.v(56,1-155,10) INFO: (VERI-9000) elaborating module 'lm32_shifter_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_multiplier.v(56,1-120,10) INFO: (VERI-9000) elaborating module 'lm32_multiplier_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_mc_arithmetic.v(64,1-309,10) INFO: (VERI-9000) elaborating module 'lm32_mc_arithmetic_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_interrupt.v(56,1-355,10) INFO: (VERI-9000) elaborating module 'lm32_interrupt_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_jtag.v(87,1-587,10) INFO: (VERI-9000) elaborating module 'lm32_jtag_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_debug.v(69,1-367,10) INFO: (VERI-9000) elaborating module 'lm32_debug_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_monitor_ram.v(53,1-1986,10) INFO: (VERI-9000) elaborating module 'lm32_monitor_ram_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/jtag_lm32.v(51,1-3083,10) INFO: (VERI-9000) elaborating module 'jtag_lm32_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_ctrl.v(54,1-368,10) INFO: (VERI-9000) elaborating module 'sdr_ctrl_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_sig.v(56,1-272,10) INFO: (VERI-9000) elaborating module 'sdr_sig_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/wb_sdr_ctrl/rtl/verilog/sdr_data.v(56,1-336,10) INFO: (VERI-9000) elaborating module 'sdr_data_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/lm32_addsub.v(55,1-114,10) INFO: (VERI-9000) elaborating module 'lm32_addsub_uniq_1'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_7'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_8'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_9'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_10'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_11'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_12'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_13'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_14'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_15'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_16'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/../components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA_uniq_17'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_1'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_2'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_3'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC_uniq_4'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) INFO: (VERI-9000) elaborating module 'VHI_uniq_1'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) INFO: (VERI-9000) elaborating module 'VLO_uniq_1'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(82,1-87,10) INFO: (VERI-9000) elaborating module 'BB_uniq_1'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(82,1-87,10) INFO: (VERI-9000) elaborating module 'BB_uniq_2'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(82,1-87,10) INFO: (VERI-9000) elaborating module 'BB_uniq_3'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(82,1-87,10) INFO: (VERI-9000) elaborating module 'BB_uniq_4'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(82,1-87,10) INFO: (VERI-9000) elaborating module 'BB_uniq_5'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(82,1-87,10) INFO: (VERI-9000) elaborating module 'BB_uniq_6'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(82,1-87,10) INFO: (VERI-9000) elaborating module 'BB_uniq_7'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(82,1-87,10) INFO: (VERI-9000) elaborating module 'BB_uniq_8'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(82,1-87,10) INFO: (VERI-9000) elaborating module 'BB_uniq_9'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(82,1-87,10) INFO: (VERI-9000) elaborating module 'BB_uniq_10'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(82,1-87,10) INFO: (VERI-9000) elaborating module 'BB_uniq_11'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(82,1-87,10) INFO: (VERI-9000) elaborating module 'BB_uniq_12'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(82,1-87,10) INFO: (VERI-9000) elaborating module 'BB_uniq_13'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(82,1-87,10) INFO: (VERI-9000) elaborating module 'BB_uniq_14'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(82,1-87,10) INFO: (VERI-9000) elaborating module 'BB_uniq_15'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(82,1-87,10) INFO: (VERI-9000) elaborating module 'BB_uniq_16'
C:/work/project/artekit_demos/forza4_rev0/diamond/../msb/platform_rev0/soc/platform_rev0.v(709,1-754,35) WARNING: (VERI-1453) port C_ADR_I is not connected to this instance
C:/work/project/artekit_demos/forza4_rev0/diamond/pll_fabrizio.v(8,8-8,20) INFO: (VERI-1018) compiling module pll_fabrizio
C:/work/project/artekit_demos/forza4_rev0/diamond/pll_fabrizio.v(8,1-98,10) INFO: (VERI-9000) elaborating module 'pll_fabrizio'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) INFO: (VERI-9000) elaborating module 'VLO_uniq_2'
C:/lscc/diamond/2.2/cae_library/synthesis/verilog/machxo2.v(1730,1-1786,10) INFO: (VERI-9000) elaborating module 'EHXPLLJ_uniq_1'
Design load finished with (0) errors, and (101) warnings.