Synthesis Report #Build: Synplify Pro G-2012.09L-SP1 , Build 029R, Mar 11 2013 #install: C:\lscc\diamond\2.2\synpbase #OS: Windows XP 5.1 #Hostname: ITLFFERRARI #Implementation: prj_diamond_ver0 $ Start of Compile #Fri Jun 21 15:15:36 2013 Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013 @N|Running in 32-bit mode Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. @I::"C:\lscc\diamond\2.2\synpbase\lib\lucent\machxo2.v" @I::"C:\lscc\diamond\2.2\synpbase\lib\lucent\pmi_def.v" @I::"C:\lscc\diamond\2.2\synpbase\lib\vlog\umr_capim.v" @I::"C:\lscc\diamond\2.2\synpbase\lib\vlog\scemi_objects.v" @I::"C:\lscc\diamond\2.2\synpbase\lib\vlog\scemi_pipes.svh" @I::"C:\lscc\diamond\2.2\synpbase\lib\vlog\hypermods.v" @I::"C:\lscc\diamond\2.2\cae_library\synthesis\verilog\machxo2.v" @I::"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\system_conf.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\pmi_def.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\er1.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\typeb.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\typea.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\jtag_cores.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\jtag_cores.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\jtag_lm32.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_addsub.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_adder.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v" @W: CS141 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":652:9:652:17|Unrecognized synthesis directive attribute @W: CS141 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":653:9:653:17|Unrecognized synthesis directive attribute @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_functions.v" @N: CG334 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2773:13:2773:25|Read directive translate_off @N: CG333 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2786:13:2786:24|Read directive translate_on @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_dcache.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_debug.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_decoder.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_icache.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v" @W: CS141 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":130:9:130:17|Unrecognized synthesis directive attribute @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v" @N: CG334 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":678:25:678:37|Read directive translate_off @N: CG333 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":681:25:681:36|Read directive translate_on @N: CG334 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":811:13:811:25|Read directive translate_off @N: CG333 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":825:13:825:24|Read directive translate_on @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_logic_op.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_mc_arithmetic.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_multiplier.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_shifter.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_top.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v" @N: CG334 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":597:16:597:28|Read directive translate_off @N: CG333 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":640:16:640:27|Read directive translate_on @N: CG334 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":717:16:717:28|Read directive translate_off @N: CG333 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":760:16:760:27|Read directive translate_on @N: CG334 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":932:16:932:28|Read directive translate_off @N: CG333 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1007:16:1007:27|Read directive translate_on @N: CG334 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1117:16:1117:28|Read directive translate_off @N: CG333 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1192:16:1192:27|Read directive translate_on @N: CG334 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1461:16:1461:28|Read directive translate_off @N: CG333 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1536:16:1536:27|Read directive translate_on @N: CG334 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1645:16:1645:28|Read directive translate_off @N: CG333 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":1720:16:1720:27|Read directive translate_on @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_trace.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\uart_core.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\uart_core.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txcver_fifo.v" @N: CG334 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":953:16:953:28|Read directive translate_off @N: CG333 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":1017:16:1017:27|Read directive translate_on @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\uart_core.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver_fifo.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\uart_core.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txmitt.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdram_include_all.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdram_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\wb_sdr_ctrl.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\wb_sdr_ctrl.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_par.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdram_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\wb_fifo_intf.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdram_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_fifo_intf.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdram_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_ctrl.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdram_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdram_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_data.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v" @I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash_intf.v" @I::"C:\work\project\artekit_demos\forza4_rev0\diamond\pll_fabrizio.v" Verilog syntax check successful! Selecting top level module platform_rev0 @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":48:7:48:14|Synthesizing module arbiter2 MAX_DAT_WIDTH=32'b00000000000000000000000000100000 WBS_DAT_WIDTH=32'b00000000000000000000000000100000 WBM0_DAT_WIDTH=32'b00000000000000000000000000100000 WBM1_DAT_WIDTH=32'b00000000000000000000000000100000 Generated name = arbiter2_32s_32s_32s_32s @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":77:7:77:27|Synthesizing module lm32_instruction_unit associativity=32'b00000000000000000000000000000001 sets=32'b00000000000000000000001000000000 bytes_per_line=32'b00000000000000000000000000010000 base_address=32'b00000000000000000000000000000000 limit=32'b00000000000000000000000000000000 addr_offset_width=32'b00000000000000000000000000000010 addr_offset_lsb=32'b00000000000000000000000000000010 addr_offset_msb=32'b00000000000000000000000000000011 Generated name = lm32_instruction_unit_1s_512s_16s_0s_0s_2s_2s_3s @N: CG793 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":824:16:824:23|Ignoring system task $display @W: CL113 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":792:0:792:5|Feedback mux created for signal i_lock_o. @W: CL113 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":792:0:792:5|Feedback mux created for signal i_cti_o[2:0]. @W: CL251 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":792:0:792:5|All reachable assignments to i_cti_o[2:0] assign 1, register removed by optimization @W: CL250 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":792:0:792:5|All reachable assignments to i_lock_o assign 0, register removed by optimization @W: CL190 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":792:0:792:5|Optimizing register bit i_adr_o[0] to a constant 0 @W: CL190 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":792:0:792:5|Optimizing register bit i_adr_o[1] to a constant 0 @W: CL279 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":792:0:792:5|Pruning register bits 1 to 0 of i_adr_o[31:0] @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_decoder.v":113:7:113:18|Synthesizing module lm32_decoder @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":69:7:69:26|Synthesizing module lm32_load_store_unit associativity=32'b00000000000000000000000000000001 sets=32'b00000000000000000000001000000000 bytes_per_line=32'b00000000000000000000000000010000 base_address=32'b00000000000000000000000000000000 limit=32'b00000000000000000000000000000000 addr_offset_width=32'b00000000000000000000000000000010 addr_offset_lsb=32'b00000000000000000000000000000010 addr_offset_msb=32'b00000000000000000000000000000011 Generated name = lm32_load_store_unit_1s_512s_16s_0s_0s_2s_2s_3s @W: CL190 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":623:0:623:5|Optimizing register bit d_cti_o[0] to a constant 1 @W: CL190 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":623:0:623:5|Optimizing register bit d_cti_o[1] to a constant 1 @W: CL190 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":623:0:623:5|Optimizing register bit d_cti_o[2] to a constant 1 @W: CL190 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":623:0:623:5|Optimizing register bit d_lock_o to a constant 0 @W: CL169 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":623:0:623:5|Pruning register d_cti_o[2:0] @W: CL169 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":623:0:623:5|Pruning register d_lock_o @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_addsub.v":55:7:55:17|Synthesizing module lm32_addsub @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\pmi_def.v":48:7:48:16|Synthesizing module pmi_addsub pmi_data_width=32'b00000000000000000000000000100000 pmi_result_width=32'b00000000000000000000000000100000 pmi_sign=24'b011011110110011001100110 pmi_family=56'b01001101011000010110001101101000010110000100111100110010 module_type=80'b01110000011011010110100101011111011000010110010001100100011100110111010101100010 Generated name = pmi_addsub_32s_32s_off_MachXO2_pmi_addsub @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_adder.v":56:7:56:16|Synthesizing module lm32_adder @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_logic_op.v":56:7:56:19|Synthesizing module lm32_logic_op @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_shifter.v":56:7:56:18|Synthesizing module lm32_shifter @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_multiplier.v":56:7:56:21|Synthesizing module lm32_multiplier @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_mc_arithmetic.v":64:7:64:24|Synthesizing module lm32_mc_arithmetic @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":56:7:56:20|Synthesizing module lm32_interrupt @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v":87:7:87:15|Synthesizing module lm32_jtag @W: CL169 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v":309:3:309:8|Pruning register command[3:0] @W: CL113 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v":309:3:309:8|Feedback mux created for signal state[3:0]. @W: CL250 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v":309:3:309:8|All reachable assignments to state[3:0] assign 0, register removed by optimization @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":69:7:69:16|Synthesizing module lm32_debug breakpoints=32'b00000000000000000000000000000000 watchpoints=32'b00000000000000000000000000000000 Generated name = lm32_debug_0s_0 @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":164:19:164:22|No assignment to bp_a_-1_ @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":164:19:164:22|No assignment to bp_a_0_ @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":165:4:165:7|No assignment to bp_e_-1_ @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":165:4:165:7|No assignment to bp_e_0_ @W: CG360 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":166:22:166:31|No assignment to wire bp_match_n @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":168:22:168:26|No assignment to wpc_c[0] @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":168:22:168:26|No assignment to wpc_c[-1] @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":169:21:169:22|No assignment to wp_-1_ @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":169:21:169:22|No assignment to wp_0_ @W: CG360 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":170:20:170:29|No assignment to wire wp_match_n @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":100:7:100:14|Synthesizing module lm32_cpu @W: CL169 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2303:0:2303:5|Pruning register x_result_sel_logic_x @W: CL169 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2303:0:2303:5|Pruning register eret_m @W: CL169 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2303:0:2303:5|Pruning register bret_m @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v":53:7:53:22|Synthesizing module lm32_monitor_ram @N: CG364 :"C:\lscc\diamond\2.2\cae_library\synthesis\verilog\machxo2.v":1291:7:1291:11|Synthesizing module DP8KC @N: CG364 :"C:\lscc\diamond\2.2\cae_library\synthesis\verilog\machxo2.v":1120:7:1120:9|Synthesizing module VHI @N: CG364 :"C:\lscc\diamond\2.2\cae_library\synthesis\verilog\machxo2.v":1124:7:1124:9|Synthesizing module VLO @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor.v":57:7:57:18|Synthesizing module lm32_monitor @A: CL282 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor.v":143:0:143:5|Feedback mux created for signal write_data[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\jtag_cores.v":60:7:60:16|Synthesizing module jtagconn16 @W: CG146 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\jtag_cores.v":60:7:60:16|Creating black box for empty module jtagconn16 @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\typea.v":65:7:65:11|Synthesizing module TYPEA @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\jtag_lm32.v":51:7:51:15|Synthesizing module jtag_lm32 @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\jtag_cores.v":75:29:75:38|Synthesizing module jtag_cores @W: CG781 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\jtag_cores.v":146:20:146:20|Undriven input CONTROL_DATAN on instance jtag_lm32_inst, tying to 0 @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_top.v":58:7:58:14|Synthesizing module lm32_top @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":321:7:321:13|Synthesizing module intface CLK_IN_MHZ=72'b001100100011010100101110001100000011000000110000001100000011000000110000 UART_WB_ADR_WIDTH=32'b00000000000000000000000000000100 UART_WB_DAT_WIDTH=32'b00000000000000000000000000001000 BAUD_RATE=32'b00000000000000011100001000000000 FIFO=32'b00000000000000000000000000000000 LCR_DATA_BITS=32'b00000000000000000000000000001000 LCR_STOP_BITS=32'b00000000000000000000000000000001 LCR_PARITY_ENABLE=32'b00000000000000000000000000000000 LCR_PARITY_ODD=32'b00000000000000000000000000000000 LCR_PARITY_STICK=32'b00000000000000000000000000000000 LCR_SET_BREAK=32'b00000000000000000000000000000000 STDOUT_SIM=32'b00000000000000000000000000000000 STDOUT_SIMFAST=32'b00000000000000000000000000000000 A_RBR=4'b0000 A_THR=4'b0000 A_IER=4'b0001 A_IIR=4'b0010 A_LCR=4'b0011 A_LSR=4'b0101 A_DIV=3'b100 idle=3'b000 int0=3'b001 int1=3'b010 int2=3'b011 int3=3'b100 Generated name = intface_Z1 @W: CG813 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":501:21:501:54|Rounding real from 217.013889 to 217 (simulation mismatch possible) @W: CG360 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":382:11:382:24|No assignment to wire fifo_empty_thr @W: CG360 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":383:8:383:20|No assignment to wire fifo_full_thr @W: CG360 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":436:32:436:39|No assignment to wire thr_fifo @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":466:13:466:31|No assignment to iir_rd_strobe_delay @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":469:13:469:18|No assignment to lsr2_r @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":469:21:469:26|No assignment to lsr3_r @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":469:29:469:34|No assignment to lsr4_r @W: CG360 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":491:13:491:32|No assignment to wire fifo_almost_full_thr @W: CG360 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":492:13:492:33|No assignment to wire fifo_almost_empty_thr @W: CG360 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":493:19:493:30|No assignment to wire fifo_din_thr @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":494:13:494:23|No assignment to fifo_wr_thr @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":495:13:495:25|No assignment to fifo_wr_q_thr @W: CG360 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":496:13:496:29|No assignment to wire fifo_wr_pulse_thr @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":94:7:94:12|Synthesizing module rxcver UART_WB_DAT_WIDTH=32'b00000000000000000000000000001000 FIFO=32'b00000000000000000000000000000000 idle=3'b000 shift=3'b001 parity=3'b010 stop=3'b011 idle1=3'b100 lat_family=56'b01001101011000010110001101101000010110000100111100110010 Generated name = rxcver_8s_0s_0_1_2_3_4_MachXO2 @W: CG360 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":134:26:134:33|No assignment to wire rbr_fifo @W: CG360 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":141:27:141:36|No assignment to wire fifo_empty @W: CG360 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":142:27:142:42|No assignment to wire fifo_almost_full @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":151:25:151:29|No assignment to count @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":163:13:163:20|No assignment to rxclk_en @W: CG360 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":166:26:166:39|No assignment to wire rbr_fifo_error @W: CG360 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":181:16:181:24|No assignment to wire fifo_full @W: CG360 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":184:16:184:32|No assignment to wire fifo_almost_empty @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":185:16:185:23|No assignment to fifo_din @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":186:16:186:22|No assignment to fifo_wr @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":187:16:187:24|No assignment to fifo_wr_q @W: CG360 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":188:16:188:28|No assignment to wire fifo_wr_pulse @N: CL177 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":472:3:472:8|Sharing sequential element sin_d0_delay. @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txmitt.v":103:7:103:12|Synthesizing module txmitt UART_WB_DAT_WIDTH=32'b00000000000000000000000000001000 FIFO=32'b00000000000000000000000000000000 start=3'b000 shift=3'b001 parity=3'b010 stop_1bit=3'b011 stop_2bit=3'b100 stop_halfbit=3'b101 start1=3'b110 Generated name = txmitt_8s_0s_0_1_2_3_4_5_6 @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txmitt.v":150:27:150:39|No assignment to tx_in_start_s @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txmitt.v":155:27:155:35|No assignment to txclk_ena @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txmitt.v":156:27:156:35|No assignment to txclk_enb @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txmitt.v":158:27:158:33|No assignment to count_v @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txmitt.v":159:27:159:36|No assignment to thr_rd_int @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txmitt.v":160:27:160:38|No assignment to thr_rd_delay @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txmitt.v":161:27:161:35|No assignment to last_word @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\uart_core.v":131:7:131:15|Synthesizing module uart_core CLK_IN_MHZ=72'b001100100011010100101110001100000011000000110000001100000011000000110000 UART_WB_ADR_WIDTH=32'b00000000000000000000000000000100 UART_WB_DAT_WIDTH=32'b00000000000000000000000000001000 BAUD_RATE=32'b00000000000000011100001000000000 FIFO=32'b00000000000000000000000000000000 LCR_DATA_BITS=32'b00000000000000000000000000001000 LCR_STOP_BITS=32'b00000000000000000000000000000001 LCR_PARITY_ENABLE=32'b00000000000000000000000000000000 LCR_PARITY_ODD=32'b00000000000000000000000000000000 LCR_PARITY_STICK=32'b00000000000000000000000000000000 LCR_SET_BREAK=32'b00000000000000000000000000000000 STDOUT_SIM=32'b00000000000000000000000000000000 STDOUT_SIMFAST=32'b00000000000000000000000000000000 Generated name = uart_core_Z2 @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\pmi_def.v":210:7:210:16|Synthesizing module pmi_pll_fp @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\pmi_def.v":154:7:154:17|Synthesizing module pmi_fifo_dc pmi_data_width_w=32'b00000000000000000000000001000101 pmi_data_width_r=32'b00000000000000000000000001000101 pmi_data_depth_w=32'b00000000000000000000000000010000 pmi_data_depth_r=32'b00000000000000000000000000010000 pmi_full_flag=32'b00000000000000000000000000010000 pmi_empty_flag=32'b00000000000000000000000000000000 pmi_almost_full_flag=32'b00000000000000000000000000001111 pmi_almost_empty_flag=32'b00000000000000000000000000000001 pmi_regmode=40'b0110111001101111011100100110010101100111 pmi_resetmode=40'b0110000101110011011110010110111001100011 pmi_family=56'b01001101011000010110001101101000010110000100111100110010 module_type=88'b0111000001101101011010010101111101100110011010010110011001101111010111110110010001100011 pmi_implementation=24'b010011000101010101010100 Generated name = pmi_fifo_dc_Z3 @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\pmi_def.v":154:7:154:17|Synthesizing module pmi_fifo_dc pmi_data_width_w=32'b00000000000000000000000000100000 pmi_data_width_r=32'b00000000000000000000000000100000 pmi_data_depth_w=32'b00000000000000000000000000010000 pmi_data_depth_r=32'b00000000000000000000000000010000 pmi_full_flag=32'b00000000000000000000000000010000 pmi_empty_flag=32'b00000000000000000000000000000000 pmi_almost_full_flag=32'b00000000000000000000000000001011 pmi_almost_empty_flag=32'b00000000000000000000000000000001 pmi_regmode=40'b0110111001101111011100100110010101100111 pmi_resetmode=40'b0110000101110011011110010110111001100011 pmi_family=56'b01001101011000010110001101101000010110000100111100110010 module_type=88'b0111000001101101011010010101111101100110011010010110011001101111010111110110010001100011 pmi_implementation=24'b010011000101010101010100 Generated name = pmi_fifo_dc_Z4 @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\wb_fifo_intf.v":54:7:54:18|Synthesizing module wb_fifo_intf @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_ctrl.v":54:7:54:14|Synthesizing module sdr_ctrl @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":56:7:56:13|Synthesizing module sdr_sig @W: CL271 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":147:0:147:5|Pruning bits 31 to 23 of sys_A[31:0] -- not in use ... @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_data.v":56:7:56:14|Synthesizing module sdr_data @N: CG364 :"C:\lscc\diamond\2.2\cae_library\synthesis\verilog\machxo2.v":82:7:82:8|Synthesizing module BB @W: CL271 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_data.v":127:0:127:5|Pruning bits 10 to 1 of rd_dat_cnt[10:0] -- not in use ... @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_fifo_intf.v":56:7:56:19|Synthesizing module sdr_fifo_intf @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\wb_sdr_ctrl.v":57:7:57:17|Synthesizing module wb_sdr_ctrl SYS_FREQ=32'b00110010001101010010111000110000 SDRAM_FREQ=24'b001100010011000000110000 LATTICE_FAMILY=56'b01001101011000010110001101101000010110000100111100110010 LATTICE_DEVICE=24'b010000010110110001101100 NUM_CLK_WAIT=32'b00000000000000000000000000000001 NUM_CLK_CL=3'b011 NUM_CLK_READ=32'b00000000000000000000000000000010 NUM_CLK_WRITE=32'b00000000000000000000000000000010 i_NOP=4'b0000 i_PRE=4'b0001 i_tRP=4'b0010 i_AR1=4'b0011 i_tRFC1=4'b0100 i_AR2=4'b0101 i_tRFC2=4'b0110 i_MRS=4'b0111 i_tMRD=4'b1000 i_ready=4'b1001 c_idle=4'b0000 c_tRCD=4'b0001 c_cl=4'b0010 c_rdata=4'b0011 c_wdata=4'b0100 c_tRFC=4'b0101 c_tDAL=4'b0110 c_ACTIVE=4'b1000 c_READA=4'b1111 c_WRITEA=4'b1110 c_AR=4'b1011 c_ReWait=4'b1100 c_PRECH=4'b1001 c_tRP=4'b1010 INHIBIT=4'b1111 NOP=4'b0111 ACTIVE=4'b0011 READ=4'b0101 WRITE=4'b0100 BURST_TERMINATE=4'b0110 PRECHARGE=4'b0010 AUTO_REFRESH=4'b0001 LOAD_MODE_REGISTER=4'b0000 tDLY=32'b00000000000000000000000000000010 READ_FIFO_DEPTH=32'b00000000000000000000000000010000 READ_FIFO_ALMOST_FULL=32'b00000000000000000000000000001011 WRITE_FIFO_DEPTH=32'b00000000000000000000000000010000 WRITE_FIFO_ALMOST_EMPTY=32'b00000000000000000000000000000001 Generated name = wb_sdr_ctrl_Z5 @N: CG364 :"C:\lscc\diamond\2.2\cae_library\synthesis\verilog\machxo2.v":1601:7:1601:12|Synthesizing module ODDRXE @N: CG179 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\wb_sdr_ctrl.v":281:21:281:31|Removing redundant assignment @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":83:7:83:17|Synthesizing module wb_ebr_ctrl SIZE=32'b00000000000000000011000000000000 EBR_WB_DAT_WIDTH=32'b00000000000000000000000000100000 INIT_FILE_FORMAT=24'b011010000110010101111000 INIT_FILE_NAME=536'b01000011001110100010111101110111011011110111001001101011001011110111000001110010011011110110101001100101011000110111010000101111011000010111001001110100011001010110101101101001011101000101111101100100011001010110110101101111011100110010111101100110011011110111001001111010011000010011010001011111011100100110010101110110001100000010111101110011011011110110011001110100011101110110000101110010011001010010111101110011011011110110011001110100011101110110000101110010011001010010111101100001011000010110000100101110011011010110010101101101 lat_family=56'b01001101011000010110001101101000010110000100111100110010 UDLY=32'b00000000000000000000000000000001 EBR_WB_ADR_WIDTH=32'b00000000000000000000000000001100 EBR_ADDR_DEPTH=32'b00000000000000000000110000000000 ST_IDLE=3'b000 ST_BURST=3'b001 ST_END=3'b010 ST_SUBRD=3'b100 ST_SUB=3'b101 ST_SUBWR=3'b110 Generated name = wb_ebr_ctrl_Z6 @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\pmi_def.v":65:7:65:16|Synthesizing module pmi_ram_dp pmi_wr_addr_depth=32'b00000000000000000000110000000000 pmi_wr_addr_width=32'b00000000000000000000000000001100 pmi_wr_data_width=32'b00000000000000000000000000100000 pmi_rd_addr_depth=32'b00000000000000000000110000000000 pmi_rd_addr_width=32'b00000000000000000000000000001100 pmi_rd_data_width=32'b00000000000000000000000000100000 pmi_regmode=40'b0110111001101111011100100110010101100111 pmi_gsr=48'b011001010110111001100001011000100110110001100101 pmi_resetmode=32'b01110011011110010110111001100011 pmi_optimization=40'b0111001101110000011001010110010101100100 pmi_init_file=536'b01000011001110100010111101110111011011110111001001101011001011110111000001110010011011110110101001100101011000110111010000101111011000010111001001110100011001010110101101101001011101000101111101100100011001010110110101101111011100110010111101100110011011110111001001111010011000010011010001011111011100100110010101110110001100000010111101110011011011110110011001110100011101110110000101110010011001010010111101110011011011110110011001110100011101110110000101110010011001010010111101100001011000010110000100101110011011010110010101101101 pmi_init_file_format=24'b011010000110010101111000 pmi_family=56'b01001101011000010110001101101000010110000100111100110010 module_type=80'b01110000011011010110100101011111011100100110000101101101010111110110010001110000 Generated name = pmi_ram_dp_Z7 @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":49:7:49:13|Synthesizing module wb_intf S_WB_DAT_WIDTH=32'b00000000000000000000000000100000 S_WB_ADR_WIDTH=32'b00000000000000000000000000100000 C_PORT_ENABLE=32'b00000000000000000000000000000000 C_WB_DAT_WIDTH=32'b00000000000000000000000000100000 C_WB_ADR_WIDTH=32'b00000000000000000000000000001011 WB_DAT_WIDTH=32'b00000000000000000000000000100000 PAGE_PRG_BUF_ENA=32'b00000000000000000000000000000000 PAGE_READ_BUF_ENA=32'b00000000000000000000000000000000 BUF_WIDTH=32'b00000000000000000000000000000000 PAGE_WIDTH=32'b00000000000000000000000000000010 SPI_READ=32'b00000000000000000000000000000011 SPI_FAST_READ=32'b00000000000000000000000000001011 SPI_BYTE_PRG=32'b00000000000000000000000000000010 SPI_PAGE_PRG=32'b00000000000000000000000000000010 SPI_BLK1_ERS=32'b00000000000000000000000011011000 SPI_BLK2_ERS=32'b00000000000000000000000011011000 SPI_BLK3_ERS=32'b00000000000000000000000011011000 SPI_CHIP_ERS=32'b00000000000000000000000011000111 SPI_WRT_ENB=32'b00000000000000000000000000000110 SPI_WRT_DISB=32'b00000000000000000000000000000100 SPI_READ_STAT=32'b00000000000000000000000000000101 SPI_WRT_STAT=32'b00000000000000000000000000000001 SPI_PWD_DOWN=32'b00000000000000000000000010111001 SPI_PWD_UP=32'b00000000000000000000000010101011 SPI_DEV_ID=32'b00000000000000000000000010011111 WB_IDLE=2'b00 WB_PORTA=2'b01 WB_PORTB=2'b10 CTR_IDLE=1'b0 CTR_CMD=1'b1 Generated name = wb_intf_Z8 @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":107:22:107:32|No assignment to spi_cmd_ext @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":133:26:133:38|No assignment to read_data_arb @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":149:17:149:28|No assignment to reg_spi_read @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":149:31:149:47|No assignment to reg_spi_fast_read @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":150:17:150:32|No assignment to reg_spi_byte_prg @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":150:35:150:50|No assignment to reg_spi_page_prg @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":150:53:150:68|No assignment to reg_spi_chip_ers @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":151:17:151:32|No assignment to reg_spi_blk1_ers @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":151:35:151:50|No assignment to reg_spi_blk2_ers @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":151:53:151:68|No assignment to reg_spi_blk3_ers @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":152:17:152:32|No assignment to reg_spi_wrt_disb @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":152:35:152:49|No assignment to reg_spi_wrt_enb @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":153:17:153:32|No assignment to reg_spi_wrt_stat @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":153:35:153:51|No assignment to reg_spi_read_stat @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":154:17:154:30|No assignment to reg_spi_dev_id @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":154:33:154:48|No assignment to reg_spi_pwd_down @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":154:51:154:64|No assignment to reg_spi_pwd_up @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":155:12:155:24|No assignment to reg_fast_read @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":172:12:172:20|No assignment to ctr_state @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":527:28:527:38|No assignment to reg_C_DAT_O @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":528:14:528:24|No assignment to reg_C_ACK_O @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":542:28:542:42|No assignment to reg_wb2spi_data @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":543:14:543:26|No assignment to reg_wb2spi_we @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":570:14:570:24|No assignment to spi_cmd_arb @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":571:14:571:22|No assignment to bytes_arb @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":572:14:572:23|No assignment to length_arb @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":573:14:573:28|No assignment to page_prg_length @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":573:31:573:44|No assignment to page_rd_length @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":574:14:574:28|No assignment to c_ctrl_port_req @W: CL190 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":298:2:298:7|Optimizing register bit cmd_bytes[0] to a constant 0 @W: CL190 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":298:2:298:7|Optimizing register bit cmd_bytes[1] to a constant 0 @W: CL190 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":298:2:298:7|Optimizing register bit cmd_bytes[3] to a constant 0 @W: CL190 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":298:2:298:7|Optimizing register bit page_cmd to a constant 0 @W: CL190 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":298:2:298:7|Optimizing register bit spi_cmd[26] to a constant 0 @W: CL190 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":298:2:298:7|Optimizing register bit spi_cmd[27] to a constant 0 @W: CL190 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":298:2:298:7|Optimizing register bit spi_cmd[28] to a constant 0 @W: CL190 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":298:2:298:7|Optimizing register bit spi_cmd[29] to a constant 0 @W: CL190 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":298:2:298:7|Optimizing register bit spi_cmd[30] to a constant 0 @W: CL190 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":298:2:298:7|Optimizing register bit spi_cmd[31] to a constant 0 @W: CL279 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":298:2:298:7|Pruning register bits 31 to 26 of spi_cmd[31:0] @W: CL169 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":298:2:298:7|Pruning register page_cmd @W: CL260 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":298:2:298:7|Pruning register bit 3 of cmd_bytes[3:0] @W: CL279 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":298:2:298:7|Pruning register bits 1 to 0 of cmd_bytes[3:0] @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash_intf.v":47:7:47:20|Synthesizing module spi_flash_intf WB_DAT_WIDTH=32'b00000000000000000000000000100000 C_PORT_ENABLE=32'b00000000000000000000000000000000 C_WB_DAT_WIDTH=32'b00000000000000000000000000100000 PAGE_PRG_BUF_ENA=32'b00000000000000000000000000000000 PAGE_READ_BUF_ENA=32'b00000000000000000000000000000000 BUF_WIDTH=32'b00000000000000000000000000000000 PAGE_WIDTH=32'b00000000000000000000000000000010 CMD_IDLE=2'b00 CMD_ENB=2'b01 CMD_SPI=2'b10 CMD_CHK=2'b11 SPI_IDLE=3'b000 SPI_OPCODE=3'b001 SPI_WAIT=3'b010 SPI_READ=3'b011 SPI_WRITE=3'b100 SPI_END=3'b101 SPI_INIT=3'b110 STOP_CYCLE=32'b00000000000000000000000000001000 Generated name = spi_flash_intf_Z9 @A: CL282 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash_intf.v":215:3:215:8|Feedback mux created for signal byte_wr[7:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area. @W: CL189 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash_intf.v":215:3:215:8|Register bit byte_wr[0] is always 0, optimizing ... @W: CL190 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash_intf.v":215:3:215:8|Optimizing register bit cmd_dword[0] to a constant 0 @W: CL260 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash_intf.v":215:3:215:8|Pruning register bit 0 of byte_wr[7:0] @W: CL260 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash_intf.v":215:3:215:8|Pruning register bit 0 of cmd_dword[31:0] @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash.v":47:7:47:15|Synthesizing module spi_flash LATTICE_FAMILY=56'b01001101011000010110001101101000010110000100111100110010 S_WB_ADR_WIDTH=32'b00000000000000000000000000100000 S_WB_DAT_WIDTH=32'b00000000000000000000000000100000 C_PORT_ENABLE=32'b00000000000000000000000000000000 C_WB_ADR_WIDTH=32'b00000000000000000000000000001011 C_WB_DAT_WIDTH=32'b00000000000000000000000000100000 PAGE_PRG_BUF_ENA=32'b00000000000000000000000000000000 PAGE_READ_BUF_ENA=32'b00000000000000000000000000000000 SECTOR_SIZE=32'b00000000000000001000000000000000 PAGE_SIZE=32'b00000000000000000000000100000000 CLOCK_SEL=32'b00000000000000000000000000000000 SPI_READ=32'b00000000000000000000000000000011 SPI_FAST_READ=32'b00000000000000000000000000001011 SPI_BYTE_PRG=32'b00000000000000000000000000000010 SPI_PAGE_PRG=32'b00000000000000000000000000000010 SPI_BLK1_ERS=32'b00000000000000000000000011011000 SPI_BLK2_ERS=32'b00000000000000000000000011011000 SPI_BLK3_ERS=32'b00000000000000000000000011011000 SPI_CHIP_ERS=32'b00000000000000000000000011000111 SPI_WRT_ENB=32'b00000000000000000000000000000110 SPI_WRT_DISB=32'b00000000000000000000000000000100 SPI_READ_STAT=32'b00000000000000000000000000000101 SPI_WRT_STAT=32'b00000000000000000000000000000001 SPI_PWD_DOWN=32'b00000000000000000000000010111001 SPI_PWD_UP=32'b00000000000000000000000010101011 SPI_DEV_ID=32'b00000000000000000000000010011111 WB_DAT_WIDTH=32'b00000000000000000000000000100000 BUF_SIZE=32'b00000000000000000000000001000000 PAGE_WIDTH=32'b00000000000000000000000000000010 BUF_WIDTH=32'b00000000000000000000000000000000 Generated name = spi_flash_Z10 @W: CG360 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash.v":145:29:145:36|No assignment to wire spi2wb_q @W: CL169 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash.v":167:3:167:8|Pruning register clk_cnt[3:0] @W: CL169 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash.v":167:3:167:8|Pruning register clk_div @N: CG364 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":336:7:336:19|Synthesizing module platform_rev0 @W: CG781 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":735:1:735:8|Undriven input C_ADR_I on instance SPIFlash, tying to 0 @W: CG781 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":735:1:735:8|Undriven input C_DAT_I on instance SPIFlash, tying to 0 @W: CG781 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":735:1:735:8|Undriven input C_WE_I on instance SPIFlash, tying to 0 @W: CG781 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":735:1:735:8|Undriven input C_STB_I on instance SPIFlash, tying to 0 @W: CG781 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":735:1:735:8|Undriven input C_CYC_I on instance SPIFlash, tying to 0 @W: CG781 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":735:1:735:8|Undriven input C_SEL_I on instance SPIFlash, tying to 0 @W: CG781 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":735:1:735:8|Undriven input C_CTI_I on instance SPIFlash, tying to 0 @W: CG781 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":735:1:735:8|Undriven input C_BTE_I on instance SPIFlash, tying to 0 @W: CG781 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":735:1:735:8|Undriven input C_LOCK_I on instance SPIFlash, tying to 0 @W: CG133 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":357:7:357:7|No assignment to i @W: CG360 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":373:5:373:16|No assignment to wire SHAREDBUS_en @W: CL156 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash.v":145:29:145:36|*Input spi2wb_q[31:0] to expression [instance] has undriven bits that are tied to 0 -- simulation mismatch possible. @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash.v":84:11:84:18|Input S_LOCK_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash.v":91:31:91:37|Input C_ADR_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash.v":92:31:92:37|Input C_DAT_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash.v":93:10:93:15|Input C_WE_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash.v":94:10:94:16|Input C_STB_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash.v":95:10:95:16|Input C_CYC_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash.v":96:33:96:39|Input C_SEL_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash.v":97:16:97:22|Input C_CTI_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash.v":98:16:98:22|Input C_BTE_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash.v":99:10:99:17|Input C_LOCK_I is unused @N: CL201 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash_intf.v":215:3:215:8|Trying to extract state machine for register spi_state Extracted state machine for register spi_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @N: CL201 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash_intf.v":121:3:121:8|Trying to extract state machine for register cmd_state Extracted state machine for register cmd_state State machine has 4 reachable states with original encodings of: 00 01 10 11 @W: CL247 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash_intf.v":67:16:67:24|Input port bit 3 of cmd_bytes[3:0] is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash_intf.v":66:17:66:27|Input spi_cmd_ext is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash_intf.v":69:10:69:17|Input page_cmd is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash_intf.v":81:31:81:38|Input wb2spi_q is unused @N: CL201 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":298:2:298:7|Trying to extract state machine for register genblk1.wb_state Extracted state machine for register genblk1.wb_state State machine has 2 reachable states with original encodings of: 00 01 @W: CL246 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":78:31:78:37|Input port bits 31 to 24 of S_ADR_I[31:0] are unused @W: CL246 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":78:31:78:37|Input port bits 1 to 0 of S_ADR_I[31:0] are unused @A: CL153 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":107:22:107:32|*Unassigned bits of spi_cmd_ext[31:0] are referenced and tied to 0 -- simulation mismatch possible. @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":84:16:84:22|Input S_CTI_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":85:16:85:22|Input S_BTE_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":92:31:92:37|Input C_ADR_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":93:31:93:37|Input C_DAT_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":94:10:94:15|Input C_WE_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":95:10:95:16|Input C_STB_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":96:10:96:16|Input C_CYC_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":97:33:97:39|Input C_SEL_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":98:16:98:22|Input C_CTI_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":99:16:99:22|Input C_BTE_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":125:31:125:38|Input spi2wb_q is unused @N: CL201 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Trying to extract state machine for register genblk1.state Extracted state machine for register genblk1.state State machine has 6 reachable states with original encodings of: 000 001 010 100 101 110 @W: CL246 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":93:17:93:25|Input port bits 31 to 14 of EBR_ADR_I[31:0] are unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":100:16:100:24|Input EBR_BTE_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":101:10:101:19|Input EBR_LOCK_I is unused @W: CL247 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_data.v":77:39:77:46|Input port bit 68 of wb2sdr_q[68:0] is unused @W: CL246 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_data.v":77:39:77:46|Input port bits 31 to 0 of wb2sdr_q[68:0] are unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_data.v":78:39:78:49|Input sdr2wb_full is unused @W: CL279 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":147:0:147:5|Pruning register bits 1 to 0 of sys_A[22:0] @W: CL246 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":102:26:102:33|Input port bits 68 to 23 of wb2sdr_q[68:0] are unused @W: CL246 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":102:26:102:33|Input port bits 1 to 0 of wb2sdr_q[68:0] are unused @N: CL201 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_ctrl.v":244:0:244:5|Trying to extract state machine for register cState Extracted state machine for register cState State machine has 14 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 1000 1001 1010 1011 1100 1110 1111 @N: CL201 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_ctrl.v":162:0:162:5|Trying to extract state machine for register iState Extracted state machine for register iState State machine has 10 reachable states with original encodings of: 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 @W: CL246 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_ctrl.v":82:40:82:47|Input port bits 67 to 0 of wb2sdr_q[68:0] are unused @N: CL201 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\wb_fifo_intf.v":135:0:135:5|Trying to extract state machine for register wb_status Extracted state machine for register wb_status State machine has 4 reachable states with original encodings of: 00 01 10 11 @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\wb_fifo_intf.v":92:18:92:24|Input S_BTE_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\wb_fifo_intf.v":93:18:93:25|Input S_LOCK_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\wb_fifo_intf.v":103:18:103:29|Input wb2sdr_empty is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\uart_core.v":155:10:155:20|Input UART_LOCK_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\uart_core.v":160:36:160:45|Input UART_SEL_I is unused @N: CL201 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txmitt.v":333:3:333:8|Trying to extract state machine for register genblk2.genblk1.tx_state Extracted state machine for register genblk2.genblk1.tx_state State machine has 7 reachable states with original encodings of: 000 001 010 011 100 101 110 @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txmitt.v":135:27:135:40|Input fifo_empty_thr is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txmitt.v":136:15:136:27|Input fifo_full_thr is unused @N: CL201 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":315:3:315:8|Trying to extract state machine for register cs_state Extracted state machine for register cs_state State machine has 5 reachable states with original encodings of: 000 001 010 011 100 @W: CL157 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":134:26:134:33|*Output rbr_fifo has undriven bits -- simulation mismatch possible. @W: CL157 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":141:27:141:36|*Output fifo_empty has undriven bits -- simulation mismatch possible. @W: CL157 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":142:27:142:42|*Output fifo_almost_full has undriven bits -- simulation mismatch possible. @N: CL201 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":874:2:874:7|Trying to extract state machine for register genblk22.cs_state Extracted state machine for register genblk22.cs_state State machine has 4 reachable states with original encodings of: 000 001 010 011 @W: CL157 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":382:11:382:24|*Output fifo_empty_thr has undriven bits -- simulation mismatch possible. @W: CL157 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":383:8:383:20|*Output fifo_full_thr has undriven bits -- simulation mismatch possible. @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":344:16:344:20|Input cti_i is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":345:16:345:20|Input bte_i is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":355:34:355:41|Input rbr_fifo is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":381:10:381:19|Input fifo_empty is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":384:10:384:15|Input thr_rd is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":385:10:385:25|Input fifo_almost_full is unused @W: CL246 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_top.v":168:23:168:33|Input port bits 31 to 14 of DEBUG_ADR_I[31:0] are unused @W: CL246 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_top.v":168:23:168:33|Input port bits 12 to 11 of DEBUG_ADR_I[31:0] are unused @W: CL246 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_top.v":168:23:168:33|Input port bits 1 to 0 of DEBUG_ADR_I[31:0] are unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_top.v":172:24:172:34|Input DEBUG_CTI_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_top.v":173:24:173:34|Input DEBUG_BTE_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_top.v":174:6:174:17|Input DEBUG_LOCK_I is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\jtag_lm32.v":60:13:60:25|Input CONTROL_DATAN is unused @N: CL201 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor.v":143:0:143:5|Trying to extract state machine for register state Extracted state machine for register state State machine has 3 reachable states with original encodings of: 00 01 10 @N: CL134 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Found RAM registers, depth=32, width=32 @N: CL134 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Found RAM registers, depth=32, width=32 @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":279:6:279:12|Input I_RTY_I is unused @W: CL246 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":123:23:123:36|Input port bits 31 to 2 of csr_write_data[31:0] are unused @W: CL247 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":123:23:123:36|Input port bit 0 of csr_write_data[31:0] is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":118:21:118:24|Input pc_x is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":119:6:119:11|Input load_x is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":120:6:120:12|Input store_x is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_debug.v":121:23:121:42|Input load_store_address_x is unused @W: CL246 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v":151:26:151:39|Input port bits 31 to 8 of csr_write_data[31:0] are unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v":139:9:139:16|Input jtag_clk is unused @N: CL201 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_mc_arithmetic.v":169:0:169:5|Trying to extract state machine for register state Extracted state machine for register state State machine has 3 reachable states with original encodings of: 000 010 011 @W: CL246 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_shifter.v":79:23:79:33|Input port bits 31 to 5 of operand_1_x[31:0] are unused @W: CL246 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":159:23:159:42|Input port bits 31 to 2 of load_store_address_x[31:0] are unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":152:6:152:12|Input stall_a is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":162:6:162:11|Input load_x is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":163:6:163:12|Input store_x is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":165:6:165:14|Input store_q_x is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":182:6:182:12|Input d_rty_i is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":204:6:204:12|Input valid_f is unused @W: CL159 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":206:6:206:11|Input kill_f is unused @N: CL201 :"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":246:0:246:5|Trying to extract state machine for register selected Extracted state machine for register selected State machine has 3 reachable states with original encodings of: 00 01 10 @END Process took 0h:00m:03s realtime, 0h:00m:03s cputime # Fri Jun 21 15:15:39 2013 ###########################################################] Premap Report Synopsys Lattice Technology Pre-mapping, Version maplat, Build 618R, Built Mar 14 2013 09:19:55 Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. Product Version G-2012.09L-SP1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 49MB) @L: C:\work\project\artekit_demos\forza4_rev0\diamond\prj_diamond_ver0\prj_diamond_ver0_prj_diamond_ver0_scck.rpt Printing clock summary report in "C:\work\project\artekit_demos\forza4_rev0\diamond\prj_diamond_ver0\prj_diamond_ver0_prj_diamond_ver0_scck.rpt" file @N: MF249 |Running in 32-bit mode. @N: MF666 |Clock conversion enabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 54MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 53MB peak: 54MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 63MB peak: 63MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 63MB peak: 65MB) @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":792:0:792:5|Removing sequential instance LM32.cpu.instruction_unit.i_stb_o, because it is equivalent to instance LM32.cpu.instruction_unit.i_cyc_o @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v":623:0:623:5|Removing sequential instance LM32.cpu.load_store_unit.d_stb_o, because it is equivalent to instance LM32.cpu.load_store_unit.d_cyc_o @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txmitt.v":528:6:528:11|Removing sequential instance uart.u_txmitt.genblk5.thr_ready, because it is equivalent to instance uart.u_txmitt.genblk4.thr_empty @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":298:2:298:7|Removing sequential instance SPIFlash.wb_intf_inst.wr_enb, because it is equivalent to instance SPIFlash.wb_intf_inst.spi_wr @W: MT462 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\jtag_lm32.v":3081:23:3081:47|Net LM32.jtag_cores.reg_update appears to be an unidentified clock source. Assuming default frequency. Clock Summary ************** Start Requested Requested Clock Clock Clock Frequency Period Type Group -------------------------------------------------------------------------------------------------------- System 1.0 MHz 1000.000 system system_clkgroup platform_rev0|clk_i 1.0 MHz 1000.000 inferred Inferred_clkgroup_0 wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock 1.0 MHz 1000.000 inferred Inferred_clkgroup_1 jtag_cores|jtck 1.0 MHz 1000.000 inferred Inferred_clkgroup_2 ======================================================================================================== @W: MT531 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v":274:3:274:8|Found signal identified as System clock which controls 1 sequential elements including LM32.cpu.jtag.rx_toggle. Using this clock, which has no specified timing constraint, can prevent conversion of gated or generated clocks and can adversely impact design performance. @W: MT529 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":246:0:246:5|Found inferred clock platform_rev0|clk_i which controls 1821 sequential elements including arbiter.locked. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. @W: MT529 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_ctrl.v":244:0:244:5|Found inferred clock wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock which controls 216 sequential elements including sdram.sdr_fifo_intf_uut.U1.cState_1[13:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. @W: MT529 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\typea.v":94:2:94:7|Found inferred clock jtag_cores|jtck which controls 22 sequential elements including LM32.jtag_cores.jtag_lm32_inst.DATA_BIT0.DATA_OUT. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. syn_allowed_resources : blockrams=26 set on top level netlist platform_rev0 Finished Pre Mapping Phase.Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 47MB peak: 81MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Fri Jun 21 15:15:41 2013 ###########################################################] Map & Optimize Report Synopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:19:55 Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. Product Version G-2012.09L-SP1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 49MB peak: 49MB) @N: MF249 |Running in 32-bit mode. @N: MF666 |Clock conversion enabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 58MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 60MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 78MB peak: 80MB) @W: MO111 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":383:8:383:20|Tristate driver fifo_full_thr on net fifo_full_thr has its enable tied to GND (module intface_Z1) @W: MO111 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":382:11:382:24|Tristate driver fifo_empty_thr on net fifo_empty_thr has its enable tied to GND (module intface_Z1) @W: MO111 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":142:27:142:42|Tristate driver fifo_almost_full on net fifo_almost_full has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_MachXO2) @W: MO111 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":141:27:141:36|Tristate driver fifo_empty on net fifo_empty has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_MachXO2) @W: MO111 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":134:26:134:33|Tristate driver rbr_fifo_1 on net rbr_fifo_1 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_MachXO2) @W: MO111 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":134:26:134:33|Tristate driver rbr_fifo_2 on net rbr_fifo_2 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_MachXO2) @W: MO111 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":134:26:134:33|Tristate driver rbr_fifo_3 on net rbr_fifo_3 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_MachXO2) @W: MO111 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":134:26:134:33|Tristate driver rbr_fifo_4 on net rbr_fifo_4 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_MachXO2) @W: MO111 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":134:26:134:33|Tristate driver rbr_fifo_5 on net rbr_fifo_5 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_MachXO2) @W: MO111 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":134:26:134:33|Tristate driver rbr_fifo_6 on net rbr_fifo_6 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_MachXO2) @W: MO111 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":134:26:134:33|Tristate driver rbr_fifo_7 on net rbr_fifo_7 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_MachXO2) @W: MO111 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":134:26:134:33|Tristate driver rbr_fifo_8 on net rbr_fifo_8 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_MachXO2) @W: MO111 :|Tristate driver fifo_empty_thr_t on net fifo_empty_thr has its enable tied to GND (module uart_core_Z2) @W: MO111 :|Tristate driver fifo_full_thr_t on net fifo_full_thr has its enable tied to GND (module uart_core_Z2) @W: MO111 :|Tristate driver RBR_FIFO_t[0] on net RBR_FIFO[0] has its enable tied to GND (module uart_core_Z2) @W: MO111 :|Tristate driver RBR_FIFO_t[1] on net RBR_FIFO[1] has its enable tied to GND (module uart_core_Z2) @W: MO111 :|Tristate driver RBR_FIFO_t[2] on net RBR_FIFO[2] has its enable tied to GND (module uart_core_Z2) @W: MO111 :|Tristate driver RBR_FIFO_t[3] on net RBR_FIFO[3] has its enable tied to GND (module uart_core_Z2) @W: MO111 :|Tristate driver RBR_FIFO_t[4] on net RBR_FIFO[4] has its enable tied to GND (module uart_core_Z2) @W: MO111 :|Tristate driver RBR_FIFO_t[5] on net RBR_FIFO[5] has its enable tied to GND (module uart_core_Z2) @W: MO111 :|Tristate driver RBR_FIFO_t[6] on net RBR_FIFO[6] has its enable tied to GND (module uart_core_Z2) @W: MO111 :|Tristate driver RBR_FIFO_t[7] on net RBR_FIFO[7] has its enable tied to GND (module uart_core_Z2) @W: MO111 :|Tristate driver fifo_empty_t on net fifo_empty has its enable tied to GND (module uart_core_Z2) @W: MO111 :|Tristate driver fifo_almost_full_t on net fifo_almost_full has its enable tied to GND (module uart_core_Z2) @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":583:0:583:5|Removing sequential instance instruction_unit.pc_w[31:2] of view:PrimLib.dffr(prim) in hierarchy view:work.lm32_cpu(verilog) because there are no references to its outputs @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_multiplier.v":98:0:98:5|Removing sequential instance LM32.cpu.multiplier.multiplier[31:0], because it is equivalent to instance LM32.cpu.operand_1_x[31:0] @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_multiplier.v":98:0:98:5|Removing sequential instance LM32.cpu.multiplier.muliplicand[31:0], because it is equivalent to instance LM32.cpu.operand_0_x[31:0] Available hyper_sources - for debug and ip models None Found @W: MT462 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\jtag_lm32.v":3081:23:3081:47|Net LM32.jtag_cores.reg_update appears to be an unidentified clock source. Assuming default frequency. @N: FA239 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":360:15:360:22|ROM genblk1\.spi_cmd_21[1:0] mapped in logic. @N: FA239 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":360:15:360:22|ROM genblk1\.spi_cmd_21[1:0] mapped in logic. @N: MO106 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":360:15:360:22|Found ROM, 'genblk1\.spi_cmd_21[1:0]', 10 words by 2 bits Finished RTL optimizations (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 79MB peak: 80MB) Encoding state machine selected[2:0] (view:work.arbiter2_32s_32s_32s_32s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N: MF135 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Found RAM 'registers_1[31:0]', 32 words by 32 bits @N: MF135 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Found RAM 'registers[31:0]', 32 words by 32 bits @N: MF179 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":1585:18:1585:44|Found 32 bit by 32 bit '==' comparator, 'cmp_zero' @N: MF179 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":1485:18:1485:45|Found 5 bit by 5 bit '==' comparator, 'un1_raw_x_0' @N: MF179 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":1486:18:1486:45|Found 5 bit by 5 bit '==' comparator, 'un1_raw_m_0' @N: MF179 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":1487:18:1487:45|Found 5 bit by 5 bit '==' comparator, 'un1_raw_w_0' @N: MF179 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":1488:18:1488:45|Found 5 bit by 5 bit '==' comparator, 'un1_raw_x_1' @N: MF179 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":1489:18:1489:45|Found 5 bit by 5 bit '==' comparator, 'un1_raw_m_1' @N: MF179 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":1490:18:1490:45|Found 5 bit by 5 bit '==' comparator, 'un1_raw_w_1' @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_26, because it is equivalent to instance LM32.cpu.registers_1rff_26 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_27, because it is equivalent to instance LM32.cpu.registers_1rff_27 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_28, because it is equivalent to instance LM32.cpu.registers_1rff_28 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_29, because it is equivalent to instance LM32.cpu.registers_1rff_29 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_30, because it is equivalent to instance LM32.cpu.registers_1rff_30 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_31, because it is equivalent to instance LM32.cpu.registers_1rff_31 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_0, because it is equivalent to instance LM32.cpu.registers_1rff_0 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_1, because it is equivalent to instance LM32.cpu.registers_1rff_1 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_2, because it is equivalent to instance LM32.cpu.registers_1rff_2 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_3, because it is equivalent to instance LM32.cpu.registers_1rff_3 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_4, because it is equivalent to instance LM32.cpu.registers_1rff_4 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_5, because it is equivalent to instance LM32.cpu.registers_1rff_5 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_6, because it is equivalent to instance LM32.cpu.registers_1rff_6 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_7, because it is equivalent to instance LM32.cpu.registers_1rff_7 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_8, because it is equivalent to instance LM32.cpu.registers_1rff_8 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_9, because it is equivalent to instance LM32.cpu.registers_1rff_9 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_10, because it is equivalent to instance LM32.cpu.registers_1rff_10 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_11, because it is equivalent to instance LM32.cpu.registers_1rff_11 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_12, because it is equivalent to instance LM32.cpu.registers_1rff_12 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_13, because it is equivalent to instance LM32.cpu.registers_1rff_13 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_14, because it is equivalent to instance LM32.cpu.registers_1rff_14 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_15, because it is equivalent to instance LM32.cpu.registers_1rff_15 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_16, because it is equivalent to instance LM32.cpu.registers_1rff_16 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_17, because it is equivalent to instance LM32.cpu.registers_1rff_17 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_18, because it is equivalent to instance LM32.cpu.registers_1rff_18 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_19, because it is equivalent to instance LM32.cpu.registers_1rff_19 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_20, because it is equivalent to instance LM32.cpu.registers_1rff_20 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_21, because it is equivalent to instance LM32.cpu.registers_1rff_21 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_22, because it is equivalent to instance LM32.cpu.registers_1rff_22 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_23, because it is equivalent to instance LM32.cpu.registers_1rff_23 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_24, because it is equivalent to instance LM32.cpu.registers_1rff_24 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Removing instance LM32.cpu.registersrff_25, because it is equivalent to instance LM32.cpu.registers_1rff_25 Encoding state machine state[2:0] (view:work.lm32_mc_arithmetic(verilog)) original code -> new code 000 -> 00 010 -> 01 011 -> 10 @N:"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_mc_arithmetic.v":169:0:169:5|Found counter in view:work.lm32_mc_arithmetic(verilog) inst cycles[5:0] Encoding state machine state[2:0] (view:work.lm32_monitor(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor.v":143:0:143:5|Removing instance LM32.debug_rom.MON_ACK_O, because it is equivalent to instance LM32.debug_rom.state[1] Encoding state machine genblk22\.cs_state[3:0] (view:work.intface_Z1(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 Encoding state machine cs_state[4:0] (view:work.rxcver_8s_0s_0_1_2_3_4_MachXO2(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 @N:"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":315:3:315:8|Found counter in view:work.rxcver_8s_0s_0_1_2_3_4_MachXO2(verilog) inst databit_recved_num[3:0] @N: MF179 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":332:10:332:30|Found 16 bit by 16 bit '==' comparator, 'cs_state12' Encoding state machine genblk2\.genblk1\.tx_state[6:0] (view:work.txmitt_8s_0s_0_1_2_3_4_5_6(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 @N:"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txmitt.v":333:3:333:8|Found counter in view:work.txmitt_8s_0s_0_1_2_3_4_5_6(verilog) inst genblk2\.genblk1\.counter[15:0] Encoding state machine wb_status[3:0] (view:work.wb_fifo_intf(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 Encoding state machine cState_1[13:0] (view:work.sdr_ctrl(verilog)) original code -> new code 0000 -> 00000000000001 0001 -> 00000000000010 0010 -> 00000000000100 0011 -> 00000000001000 0100 -> 00000000010000 0101 -> 00000000100000 0110 -> 00000001000000 1000 -> 00000010000000 1001 -> 00000100000000 1010 -> 00001000000000 1011 -> 00010000000000 1100 -> 00100000000000 1110 -> 01000000000000 1111 -> 10000000000000 Encoding state machine iState_1[9:0] (view:work.sdr_ctrl(verilog)) original code -> new code 0000 -> 0000000001 0001 -> 0000000010 0010 -> 0000000100 0011 -> 0000001000 0100 -> 0000010000 0101 -> 0000100000 0110 -> 0001000000 0111 -> 0010000000 1000 -> 0100000000 1001 -> 1000000000 @N:"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_ctrl.v":206:0:206:5|Found counter in view:work.sdr_ctrl(verilog) inst rd_cmd_cnt[10:0] @N: MF179 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":162:66:162:101|Found 14 bit by 14 bit '==' comparator, 'un6_cross_page' @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":147:0:147:5|Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[13], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[22] @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":147:0:147:5|Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[2], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[11] @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":147:0:147:5|Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[5], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[14] @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":147:0:147:5|Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[9], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[18] @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":147:0:147:5|Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[12], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[21] @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":147:0:147:5|Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[0], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[9] @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":147:0:147:5|Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[1], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[10] @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":147:0:147:5|Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[3], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[12] @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":147:0:147:5|Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[4], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[13] @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":147:0:147:5|Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[6], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[15] @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":147:0:147:5|Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[7], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[16] @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":147:0:147:5|Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[8], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[17] @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":147:0:147:5|Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[10], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[19] @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":147:0:147:5|Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[11], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[20] Encoding state machine genblk1\.state[5:0] (view:work.wb_ebr_ctrl_Z6(verilog)) original code -> new code 000 -> 000001 001 -> 000010 010 -> 000100 100 -> 001000 101 -> 010000 110 -> 100000 @N: MF179 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":295:30:295:59|Found 12 bit by 12 bit '==' comparator, 'genblk1\.un1_read_address' Encoding state machine genblk1\.wb_state[1:0] (view:work.wb_intf_Z8(verilog)) original code -> new code 00 -> 0 01 -> 1 @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\wb_intf.v":298:2:298:7|Removing instance SPIFlash.wb_intf_inst.spi_cmd_1[25], because it is equivalent to instance SPIFlash.wb_intf_inst.cmd_bytes_1[2] Encoding state machine cmd_state[3:0] (view:work.spi_flash_intf_Z9(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 Encoding state machine spi_state[6:0] (view:work.spi_flash_intf_Z9(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 @W: MO197 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/spi_flash/rtl/verilog\spi_flash_intf.v":292:2:292:9|FSM register spi_state[2] removed due to constant propagation @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2303:0:2303:5|Removing instance LM32.cpu.condition_x[2], because it is equivalent to instance LM32.cpu.logic_op_x[2] @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2303:0:2303:5|Removing instance LM32.cpu.sign_extend_x, because it is equivalent to instance LM32.cpu.logic_op_x[2] @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2303:0:2303:5|Removing instance LM32.cpu.w_result_sel_load_x, because it is equivalent to instance LM32.cpu.load_x @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2303:0:2303:5|Removing instance LM32.cpu.condition_x[1], because it is equivalent to instance LM32.cpu.logic_op_x[1] @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2303:0:2303:5|Removing instance LM32.cpu.size_x[1], because it is equivalent to instance LM32.cpu.logic_op_x[1] @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2303:0:2303:5|Removing instance LM32.cpu.condition_x[0], because it is equivalent to instance LM32.cpu.logic_op_x[0] @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2303:0:2303:5|Removing instance LM32.cpu.size_x[0], because it is equivalent to instance LM32.cpu.logic_op_x[0] @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2303:0:2303:5|Removing instance LM32.cpu.logic_op_x[3], because it is equivalent to instance LM32.cpu.direction_x Finished factoring (Real Time elapsed 0h:00m:05s; CPU Time elapsed 0h:00m:05s; Memory used current: 106MB peak: 107MB) @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":278:6:278:13|Removing sequential instance ebr.genblk1\.state[3] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 98MB peak: 108MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 93MB peak: 108MB) @W: BN132 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":281:6:281:11|Removing instance ebr.genblk1.state[4], because it is equivalent to instance ebr.genblk1.state[1] @N: FA113 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":145:24:145:31|Pipelining module next_adr[22:2] @N: MF169 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v":147:0:147:5|Register sys_A[22:2] pushed in. @N: FA113 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":324:13:324:16|Pipelining module un1_counter_2[15:0] @N: MF169 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":315:3:315:8|Register counter[15:0] pushed in. @N: MF169 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":499:3:499:8|Register divisor[15:0] pushed in. @N: MF169 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":290:14:290:30|Register cs_state[4:0] pushed in. @N: MF169 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":287:5:287:10|Register rx_idle pushed in. @N: MF169 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":653:4:653:9|Register thr_nonfifo pushed in. @N: MF169 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":653:4:653:9|Register ier pushed in. @N: MF169 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":501:3:501:8|Register rx_idle_d1 pushed in. @N: MF169 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txmitt.v":333:3:333:8|Register tsr pushed in. @N: MF169 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txmitt.v":347:9:347:14|Register tx_state pushed in. @N: MF169 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":874:2:874:7|Register cs_state pushed in. @N: MF169 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":625:2:625:7|Register data_8bit pushed in. @N: MF169 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txmitt.v":333:3:333:8|Register tx_parity pushed in. @N: MF169 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":254:7:254:12|Register rbr_datardy pushed in. @N: MF169 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":553:3:553:8|Register overrun_err_int pushed in. @N: MF169 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":553:3:553:8|Register parity_err_int pushed in. @N: MF169 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":534:3:534:8|Register rbr_rd_nonfifo pushed in. @N: FA113 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":324:13:324:16|Pipelining module un1_counter_2[15:0] @N: MF169 :|Register NoName pushed in. @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":272:6:272:13|Removing sequential instance ebr.genblk1\.state[1] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[5] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[4] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[3] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[2] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[1] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[20] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[19] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[18] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[17] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[16] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[15] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[14] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[13] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[12] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[11] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[10] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[9] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[8] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[7] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[6] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[31] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[30] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[29] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[28] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[27] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[26] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[25] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[24] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[23] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[22] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v":219:0:219:5|Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[21] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: FA113 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_multiplier.v":115:26:115:50|Pipelining module product_2[31:0] @N: MF169 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_multiplier.v":98:0:98:5|Register product[31:0] pushed in. @N: FX404 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":397:26:397:66|Found addmux in view:work.platform_rev0(verilog) inst ebr.genblk1\.pmi_address_4_0_i_m3[13:2] from ebr.un14_pmi_address_nxt[11:0] @N: FX404 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":395:26:395:66|Found addmux in view:work.platform_rev0(verilog) inst ebr.genblk1\.pmi_address_4_1_i_m3[13:1] from ebr.un7_pmi_address_nxt[12:0] @N: FX404 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v":511:12:511:23|Found addmux in view:work.platform_rev0(verilog) inst LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0[29:0] from LM32.cpu.instruction_unit.un7_pc_a[29:0] Starting Early Timing Optimization (Real Time elapsed 0h:00m:10s; CPU Time elapsed 0h:00m:09s; Memory used current: 94MB peak: 108MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 94MB peak: 108MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 93MB peak: 108MB) @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":687:1:687:3|Removing sequential instance ebr.genblk1\.state[5] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.raw_hazard in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[0] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[5] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[6] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[7] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[13] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[22] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[25] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[29] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[31] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[4] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[20] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[1] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[3] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[19] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[8] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[9] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[18] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[23] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[15] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[17] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[21] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[2] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[10] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[14] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[16] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[30] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[24] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[26] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[28] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[12] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[11] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.write_data_d[27] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[0] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_SEL_I_d[0] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[5] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[6] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[7] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[13] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_SEL_I_d[1] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[22] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_SEL_I_d[2] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[25] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_SEL_I_d[3] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[29] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[31] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[4] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[20] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[1] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[3] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[19] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[8] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[9] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[18] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[23] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[15] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[17] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[21] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[2] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[10] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[14] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[16] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[30] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[24] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[26] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[28] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[12] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[11] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N: BN362 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":422:2:422:7|Removing sequential instance ebr.genblk1\.EBR_DAT_I_d[27] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs Finished preparing to map (Real Time elapsed 0h:00m:13s; CPU Time elapsed 0h:00m:12s; Memory used current: 94MB peak: 108MB) Finished technology mapping (Real Time elapsed 0h:00m:19s; CPU Time elapsed 0h:00m:18s; Memory used current: 108MB peak: 145MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ ------------------------------------------------------------ Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:20s; CPU Time elapsed 0h:00m:19s; Memory used current: 108MB peak: 145MB) @N: FX164 |The option to pack flops in the IOB has not been specified @N: FO126 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Generating RAM LM32.cpu.registers_1[31:0] @N: FO126 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":2664:0:2664:5|Generating RAM LM32.cpu.registers[31:0] Finished restoring hierarchy (Real Time elapsed 0h:00m:22s; CPU Time elapsed 0h:00m:21s; Memory used current: 111MB peak: 145MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ 1 non-gated/non-generated clock tree(s) driving 1773 clock pin(s) of sequential element(s) 3 gated/generated clock tree(s) driving 246 clock pin(s) of sequential element(s) 0 instances converted, 246 sequential instances remain driven by gated/generated clocks ==================================== Non-Gated/Non-Generated Clocks ===================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------------------------- @K:CKID0004 clk_i port 1773 SPIFlash_spi_flash_intf_inst_CSio ========================================================================================================= ============================================================================================================================== Gated/Generated Clocks ============================================================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ @K:CKID0001 sdram.U1_pmi_pll pmi_pll_fp 223 sdram.sys_dly_cnt[15] Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements @K:CKID0002 LM32.jtag_cores.jtagconn16_lm32_inst jtagconn16 22 LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT2.tdoInt Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements @K:CKID0003 LM32.jtag_cores.jtag_lm32_inst.REG_UPDATE ORCALUT4 1 LM32.cpu.jtag.rx_toggle No clocks found on inputs ==================================================================================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Writing Analyst data base C:\work\project\artekit_demos\forza4_rev0\diamond\prj_diamond_ver0\prj_diamond_ver0_prj_diamond_ver0.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:24s; CPU Time elapsed 0h:00m:23s; Memory used current: 110MB peak: 145MB) Writing EDIF Netlist and constraint files G-2012.09L-SP1 @N: BW106 |Synplicity Constraint File capacitance units using default value of 1pF @W|Block-path constraint from CLKNET "jtag_cores|jtck" to PORT "platform_rev0|clk_i" not forward annotated in -lpf file. @W|Block-path constraint from CLKNET "wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock" to PORT "platform_rev0|clk_i" not forward annotated in -lpf file. @W|Block-path constraint from PORT "platform_rev0|clk_i" to CLKNET "jtag_cores|jtck" not forward annotated in -lpf file. @W|Block-path constraint from PORT "platform_rev0|clk_i" to CLKNET "wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock" not forward annotated in -lpf file. Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:25s; CPU Time elapsed 0h:00m:24s; Memory used current: 115MB peak: 145MB) @W: MT246 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_ebr_ctrl/rtl/verilog\wb_ebr_ctrl.v":463:2:463:4|Blackbox pmi_ram_dp_Z7 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\wb_sdr_ctrl.v":334:3:334:13|Blackbox pmi_fifo_dc_Z4 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\wb_sdr_ctrl.v":306:3:306:13|Blackbox pmi_fifo_dc_Z3 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\wb_sdr_ctrl.v":239:9:239:22|Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\wb_sdr_ctrl.v":155:1:155:10|Blackbox pmi_pll_fp is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_addsub.v":102:7:102:12|Blackbox pmi_addsub_32s_32s_off_MachXO2_pmi_addsub is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT246 :"c:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\jtag_cores.v":126:70:126:89|Blackbox jtagconn16 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W: MT420 |Found inferred clock platform_rev0|clk_i with period 1000.00ns. Please declare a user-defined clock on object "p:clk_i" @W: MT420 |Found inferred clock wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock with period 1000.00ns. Please declare a user-defined clock on object "n:sdram.sdr_clk_c" @W: MT420 |Found inferred clock jtag_cores|jtck with period 1000.00ns. Please declare a user-defined clock on object "n:LM32.jtag_cores.jtck" ##### START OF TIMING REPORT #####[ # Timing Report written on Fri Jun 21 15:16:07 2013 # Top view: platform_rev0 Requested Frequency: 1.0 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N: MT320 |Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N: MT322 |Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: 986.616 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------ jtag_cores|jtck 1.0 MHz 636.2 MHz 1000.000 1.572 998.428 inferred Inferred_clkgroup_2 platform_rev0|clk_i 1.0 MHz 74.7 MHz 1000.000 13.384 986.616 inferred Inferred_clkgroup_0 wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock 1.0 MHz 110.4 MHz 1000.000 9.061 990.939 inferred Inferred_clkgroup_1 System 1.0 MHz 380.7 MHz 1000.000 2.626 997.374 system system_clkgroup ================================================================================================================================================ Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 1000.000 997.374 | No paths - | No paths - | No paths - System platform_rev0|clk_i | 1000.000 994.534 | No paths - | No paths - | No paths - System wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock | 1000.000 994.427 | No paths - | No paths - | No paths - System jtag_cores|jtck | No paths - | No paths - | 1000.000 999.080 | No paths - platform_rev0|clk_i System | 1000.000 992.102 | No paths - | No paths - | No paths - platform_rev0|clk_i platform_rev0|clk_i | 1000.000 986.616 | No paths - | No paths - | No paths - platform_rev0|clk_i wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock | Diff grp - | No paths - | No paths - | No paths - platform_rev0|clk_i jtag_cores|jtck | No paths - | No paths - | Diff grp - | No paths - wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock System | 1000.000 991.018 | No paths - | No paths - | No paths - wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock platform_rev0|clk_i | Diff grp - | No paths - | No paths - | No paths - wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock | 1000.000 990.939 | No paths - | No paths - | No paths - jtag_cores|jtck System | No paths - | No paths - | No paths - | 1000.000 998.956 jtag_cores|jtck platform_rev0|clk_i | No paths - | No paths - | No paths - | Diff grp - jtag_cores|jtck jtag_cores|jtck | No paths - | 1000.000 998.428 | No paths - | No paths - ================================================================================================================================================================================ Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: jtag_cores|jtck ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------- LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT1.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[9] 1.044 998.428 LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT0.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[8] 1.044 998.428 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT7.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[7] 1.044 998.428 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT6.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[6] 1.044 998.428 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT5.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[5] 1.044 998.428 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT4.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[4] 1.044 998.428 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT3.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[3] 1.044 998.428 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT2.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[2] 1.044 998.428 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT1.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[1] 1.044 998.428 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT0.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[0] 1.044 998.428 ============================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------- LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT2.tdoInt jtag_cores|jtck FD1P3DX D N_37_i 1000.089 998.428 LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT1.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_8 1000.089 998.428 LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT0.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_7 1000.089 998.428 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT7.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_6 1000.089 998.428 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT6.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_5 1000.089 998.428 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT5.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_4 1000.089 998.428 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT4.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_3 1000.089 998.428 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT3.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_2 1000.089 998.428 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT2.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_1 1000.089 998.428 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT1.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_0 1000.089 998.428 ================================================================================================================================= Worst Path Information *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) = Required time: 1000.089 - Propagation time: 1.661 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 998.428 Number of logic level(s): 1 Starting point: LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT1.tdoInt / Q Ending point: LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT2.tdoInt / D The start point is clocked by jtag_cores|jtck [falling] on pin CK The end point is clocked by jtag_cores|jtck [falling] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT1.tdoInt FD1P3DX Q Out 1.044 1.044 - tdibus[9] Net - - - - 2 LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT2.tdoInt_RNO ORCALUT4 B In 0.000 1.044 - LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT2.tdoInt_RNO ORCALUT4 Z Out 0.617 1.661 - N_37_i Net - - - - 1 LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT2.tdoInt FD1P3DX D In 0.000 1.661 - ====================================================================================================================== ==================================== Detailed Report for Clock: platform_rev0|clk_i ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------- LM32.cpu.instruction_unit.instruction_d[30] platform_rev0|clk_i FD1P3DX Q instruction_d[30] 1.284 986.616 LM32.cpu.instruction_unit.instruction_d[29] platform_rev0|clk_i FD1P3DX Q direction_d 1.272 986.628 LM32.cpu.instruction_unit.instruction_d[27] platform_rev0|clk_i FD1P3DX Q size_d[1] 1.292 986.784 LM32.cpu.instruction_unit.instruction_d[28] platform_rev0|clk_i FD1P3DX Q sign_extend_d 1.284 986.792 LM32.cpu.instruction_unit.instruction_d[31] platform_rev0|clk_i FD1P3DX Q instruction_d[31] 1.321 987.771 LM32.cpu.instruction_unit.instruction_d[26] platform_rev0|clk_i FD1P3DX Q size_d[0] 1.288 987.805 LM32.cpu.multiplier.product_pipe_16 platform_rev0|clk_i FD1P3DX Q product_2_madd_24 1.044 987.855 LM32.cpu.multiplier.product_pipe_131 platform_rev0|clk_i FD1P3DX Q product_2_madd_17f[4] 1.044 987.855 arbiter.selected[1] platform_rev0|clk_i FD1S3DX Q selected[1] 1.577 987.968 LM32.cpu.multiplier.product_pipe_104 platform_rev0|clk_i FD1P3DX Q product_2_madd_16f[5] 0.972 988.070 ========================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------ LM32.cpu.instruction_unit.i_adr_o_1[31] platform_rev0|clk_i FD1P3DX D N_2939 999.894 986.616 LM32.cpu.instruction_unit.pc_f[31] platform_rev0|clk_i FD1P3BX D N_2939 999.894 986.616 LM32.cpu.instruction_unit.i_adr_o_1[29] platform_rev0|clk_i FD1P3DX D pc_a_24_1137_i_m4_0_cry_27_0_RNIO35E2 999.894 986.759 LM32.cpu.instruction_unit.i_adr_o_1[30] platform_rev0|clk_i FD1P3DX D pc_a_24_1137_i_m4_0_cry_27_0_RNI8L6E2 999.894 986.759 LM32.cpu.instruction_unit.pc_f[29] platform_rev0|clk_i FD1P3BX D pc_a_24_1137_i_m4_0_cry_27_0_RNIO35E2 999.894 986.759 LM32.cpu.instruction_unit.pc_f[30] platform_rev0|clk_i FD1P3BX D pc_a_24_1137_i_m4_0_cry_27_0_RNI8L6E2 999.894 986.759 LM32.cpu.instruction_unit.i_adr_o_1[27] platform_rev0|clk_i FD1P3DX D pc_a_24_1137_i_m4_0_cry_25_0_RNIIR2E2 999.894 986.902 LM32.cpu.instruction_unit.i_adr_o_1[28] platform_rev0|clk_i FD1P3DX D N_3533 999.894 986.902 LM32.cpu.instruction_unit.pc_f[27] platform_rev0|clk_i FD1P3BX D pc_a_24_1137_i_m4_0_cry_25_0_RNIIR2E2 999.894 986.902 LM32.cpu.instruction_unit.pc_f[28] platform_rev0|clk_i FD1P3BX D N_3533 999.894 986.902 ====================================================================================================================================================== Worst Path Information *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 999.894 - Propagation time: 13.278 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : 986.616 Number of logic level(s): 21 Starting point: LM32.cpu.instruction_unit.instruction_d[30] / Q Ending point: LM32.cpu.instruction_unit.i_adr_o_1[31] / D The start point is clocked by platform_rev0|clk_i [rising] on pin CK The end point is clocked by platform_rev0|clk_i [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------- LM32.cpu.instruction_unit.instruction_d[30] FD1P3DX Q Out 1.284 1.284 - instruction_d[30] Net - - - - 21 LM32.cpu.decoder.bi_unconditional_1 ORCALUT4 B In 0.000 1.284 - LM32.cpu.decoder.bi_unconditional_1 ORCALUT4 Z Out 1.193 2.477 - op_calli_1 Net - - - - 4 LM32.cpu.decoder.bi_unconditional ORCALUT4 B In 0.000 2.477 - LM32.cpu.decoder.bi_unconditional ORCALUT4 Z Out 1.193 3.669 - bi_unconditional Net - - - - 4 LM32.cpu.decoder.branch_0_o2_0 ORCALUT4 B In 0.000 3.669 - LM32.cpu.decoder.branch_0_o2_0 ORCALUT4 Z Out 1.273 4.942 - branch_predict_d Net - - - - 9 LM32.cpu.instruction_unit.un1_kill_f_i_o2 ORCALUT4 C In 0.000 4.942 - LM32.cpu.instruction_unit.un1_kill_f_i_o2 ORCALUT4 Z Out 1.281 6.223 - N_190 Net - - - - 11 LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_1_0_RNO_0 ORCALUT4 A In 0.000 6.223 - LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_1_0_RNO_0 ORCALUT4 Z Out 1.017 7.240 - pc_a_24_1137_i_m4_0_axb_2 Net - - - - 1 LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_1_0 CCU2D A1 In 0.000 7.240 - LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_1_0 CCU2D COUT Out 1.545 8.784 - pc_a_24_1137_i_m4_0_cry_2 Net - - - - 1 LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_3_0 CCU2D CIN In 0.000 8.784 - LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_3_0 CCU2D COUT Out 0.143 8.927 - pc_a_24_1137_i_m4_0_cry_4 Net - - - - 1 LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_5_0 CCU2D CIN In 0.000 8.927 - LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_5_0 CCU2D COUT Out 0.143 9.070 - pc_a_24_1137_i_m4_0_cry_6 Net - - - - 1 LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_7_0 CCU2D CIN In 0.000 9.070 - LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_7_0 CCU2D COUT Out 0.143 9.213 - pc_a_24_1137_i_m4_0_cry_8 Net - - - - 1 LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_9_0 CCU2D CIN In 0.000 9.213 - LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_9_0 CCU2D COUT Out 0.143 9.355 - pc_a_24_1137_i_m4_0_cry_10 Net - - - - 1 LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_11_0 CCU2D CIN In 0.000 9.355 - LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_11_0 CCU2D COUT Out 0.143 9.498 - pc_a_24_1137_i_m4_0_cry_12 Net - - - - 1 LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_13_0 CCU2D CIN In 0.000 9.498 - LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_13_0 CCU2D COUT Out 0.143 9.641 - pc_a_24_1137_i_m4_0_cry_14 Net - - - - 1 LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_15_0 CCU2D CIN In 0.000 9.641 - LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_15_0 CCU2D COUT Out 0.143 9.784 - pc_a_24_1137_i_m4_0_cry_16 Net - - - - 1 LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_17_0 CCU2D CIN In 0.000 9.784 - LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_17_0 CCU2D COUT Out 0.143 9.927 - pc_a_24_1137_i_m4_0_cry_18 Net - - - - 1 LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_19_0 CCU2D CIN In 0.000 9.927 - LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_19_0 CCU2D COUT Out 0.143 10.070 - pc_a_24_1137_i_m4_0_cry_20 Net - - - - 1 LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_21_0 CCU2D CIN In 0.000 10.070 - LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_21_0 CCU2D COUT Out 0.143 10.212 - pc_a_24_1137_i_m4_0_cry_22 Net - - - - 1 LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_23_0 CCU2D CIN In 0.000 10.212 - LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_23_0 CCU2D COUT Out 0.143 10.355 - pc_a_24_1137_i_m4_0_cry_24 Net - - - - 1 LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_25_0 CCU2D CIN In 0.000 10.355 - LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_25_0 CCU2D COUT Out 0.143 10.498 - pc_a_24_1137_i_m4_0_cry_26 Net - - - - 1 LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_27_0 CCU2D CIN In 0.000 10.498 - LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_cry_27_0 CCU2D COUT Out 0.143 10.641 - pc_a_24_1137_i_m4_0_cry_28 Net - - - - 1 LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_s_29_0 CCU2D CIN In 0.000 10.641 - LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_s_29_0 CCU2D S0 Out 1.549 12.190 - N_3454 Net - - - - 1 LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_s_29_0_RNIH1FL2 ORCALUT4 B In 0.000 12.190 - LM32.cpu.instruction_unit.pc_a_24_1137_i_m4_0_s_29_0_RNIH1FL2 ORCALUT4 Z Out 1.089 13.278 - N_2939 Net - - - - 2 LM32.cpu.instruction_unit.i_adr_o_1[31] FD1P3DX D In 0.000 13.278 - ================================================================================================================================ ==================================== Detailed Report for Clock: wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------ sdram.sdr_fifo_intf_uut.U1.cState_1[4] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX Q cState_1[4] 1.188 990.939 sdram.sdr_fifo_intf_uut.U1.cState_1[12] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX Q cState_1[12] 1.188 990.939 sdram.sdr_fifo_intf_uut.U1.cState_1[13] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX Q cState_1[13] 1.236 991.654 sdram.sdr_fifo_intf_uut.U1.cState_1[2] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX Q cState_1[2] 1.188 991.702 sdram.sdr_fifo_intf_uut.U1.cState_1[3] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX Q cState_1[3] 1.188 991.702 sdram.sdr_fifo_intf_uut.U1.cState_1[6] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX Q cState_1[6] 1.188 991.702 sdram.sdr_fifo_intf_uut.U1.cState_1[5] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX Q cState_1[5] 1.204 991.939 sdram.sdr_fifo_intf_uut.U1.cState_1[11] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX Q cState_1[11] 1.148 991.995 sdram.sdr_fifo_intf_uut.U1.cState_1[1] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX Q cState_1[1] 1.188 992.051 sdram.sdr_fifo_intf_uut.U1.cState_1[9] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX Q cState_1[9] 1.204 992.099 ================================================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------------------------- sdram.sdr_fifo_intf_uut.U1.cState_1[2] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX D N_234_i 1000.089 990.939 sdram.sdr_fifo_intf_uut.U1.cState_1[12] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX D cState_1_ns[12] 1000.089 990.939 sdram.sdr_fifo_intf_uut.U1.cState_1[13] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX D cState_1_ns[13] 1000.089 990.939 sdram.fifo_wb2sdr wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock pmi_fifo_dc_Z3 RdEn wb2sdr_re 1000.000 991.018 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_19 wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1P3DX D next_adr_0[21] 999.894 991.654 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_20 wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1P3DX D next_adr_0[22] 999.894 991.654 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_17 wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1P3DX D next_adr_0[19] 999.894 991.796 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_18 wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1P3DX D next_adr_0[20] 999.894 991.796 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_15 wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1P3DX D next_adr_0[17] 999.894 991.939 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_16 wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1P3DX D next_adr_0[18] 999.894 991.939 ============================================================================================================================================================= Worst Path Information *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) = Required time: 1000.089 - Propagation time: 9.150 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : 990.939 Number of logic level(s): 8 Starting point: sdram.sdr_fifo_intf_uut.U1.cState_1[4] / Q Ending point: sdram.sdr_fifo_intf_uut.U1.cState_1[2] / D The start point is clocked by wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock [rising] on pin CK The end point is clocked by wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------- sdram.sdr_fifo_intf_uut.U1.cState_1[4] FD1S3DX Q Out 1.188 1.188 - cState_1[4] Net - - - - 6 sdram.sdr_fifo_intf_uut.U1.cState_1_ns_i_a2_0[4] ORCALUT4 A In 0.000 1.188 - sdram.sdr_fifo_intf_uut.U1.cState_1_ns_i_a2_0[4] ORCALUT4 Z Out 1.017 2.205 - N_322 Net - - - - 1 sdram.sdr_fifo_intf_uut.U1.un1_LOAD_MODE_REGISTER_1_i_a2_3[2] ORCALUT4 A In 0.000 2.205 - sdram.sdr_fifo_intf_uut.U1.un1_LOAD_MODE_REGISTER_1_i_a2_3[2] ORCALUT4 Z Out 1.249 3.453 - N_281_3 Net - - - - 7 sdram.sdr_fifo_intf_uut.U1.un1_LOAD_MODE_REGISTER_1_i_a2[2] ORCALUT4 A In 0.000 3.453 - sdram.sdr_fifo_intf_uut.U1.un1_LOAD_MODE_REGISTER_1_i_a2[2] ORCALUT4 Z Out 0.449 3.902 - un1_LOAD_MODE_REGISTER_1_i_a2[2] Net - - - - 6 sdram.sdr_fifo_intf_uut.U3.sdr_DQM13 ORCALUT4 C In 0.000 3.902 - sdram.sdr_fifo_intf_uut.U3.sdr_DQM13 ORCALUT4 Z Out 1.333 5.235 - sdr_DQM13 Net - - - - 22 sdram.sdr_fifo_intf_uut.U2.cross_page_iv_RNO ORCALUT4 A In 0.000 5.235 - sdram.sdr_fifo_intf_uut.U2.cross_page_iv_RNO ORCALUT4 Z Out 1.017 6.252 - cross_page_1 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.cross_page_iv ORCALUT4 A In 0.000 6.252 - sdram.sdr_fifo_intf_uut.U2.cross_page_iv ORCALUT4 Z Out 1.193 7.445 - cross_page Net - - - - 4 sdram.sdr_fifo_intf_uut.U1.cState26 ORCALUT4 C In 0.000 7.445 - sdram.sdr_fifo_intf_uut.U1.cState26 ORCALUT4 Z Out 1.089 8.533 - cState26 Net - - - - 2 sdram.sdr_fifo_intf_uut.U1.cState_1_RNO[2] ORCALUT4 B In 0.000 8.533 - sdram.sdr_fifo_intf_uut.U1.cState_1_RNO[2] ORCALUT4 Z Out 0.617 9.150 - N_234_i Net - - - - 1 sdram.sdr_fifo_intf_uut.U1.cState_1[2] FD1S3DX D In 0.000 9.150 - ================================================================================================================================ ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------------------- sdram.fifo_wb2sdr System pmi_fifo_dc_Z3 Q[2] wb2sdr_q[2] 0.000 994.427 LM32.cpu.adder.addsub.genblk1\.addsub System pmi_addsub_32s_32s_off_MachXO2_pmi_addsub Result[4] adder_result_x[4] 0.000 994.534 sdram.fifo_wb2sdr System pmi_fifo_dc_Z3 Q[3] wb2sdr_q[3] 0.000 994.570 sdram.fifo_wb2sdr System pmi_fifo_dc_Z3 Q[4] wb2sdr_q[4] 0.000 994.570 sdram.fifo_wb2sdr System pmi_fifo_dc_Z3 Q[5] wb2sdr_q[5] 0.000 994.712 sdram.fifo_wb2sdr System pmi_fifo_dc_Z3 Q[6] wb2sdr_q[6] 0.000 994.712 sdram.fifo_wb2sdr System pmi_fifo_dc_Z3 Q[7] wb2sdr_q[7] 0.000 994.855 sdram.fifo_wb2sdr System pmi_fifo_dc_Z3 Q[8] wb2sdr_q[8] 0.000 994.855 LM32.cpu.adder.addsub.genblk1\.addsub System pmi_addsub_32s_32s_off_MachXO2_pmi_addsub Result[25] adder_result_x[25] 0.000 994.911 LM32.cpu.adder.addsub.genblk1\.addsub System pmi_addsub_32s_32s_off_MachXO2_pmi_addsub Result[23] adder_result_x[23] 0.000 994.956 =============================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------- sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_19 System FD1P3DX D next_adr_0[21] 999.894 994.427 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_20 System FD1P3DX D next_adr_0[22] 999.894 994.427 LM32.cpu.mc_arithmetic.a[4] System FD1P3DX D N_195 1000.089 994.534 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_17 System FD1P3DX D next_adr_0[19] 999.894 994.570 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_18 System FD1P3DX D next_adr_0[20] 999.894 994.570 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_15 System FD1P3DX D next_adr_0[17] 999.894 994.712 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_16 System FD1P3DX D next_adr_0[18] 999.894 994.712 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_13 System FD1P3DX D next_adr_0[15] 999.894 994.855 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_14 System FD1P3DX D next_adr_0[16] 999.894 994.855 LM32.cpu.mc_arithmetic.a[25] System FD1P3DX D a_12[25] 1000.089 994.911 ====================================================================================================================== Worst Path Information *********************** Path information for path number 1: Requested Period: 1000.000 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 999.894 - Propagation time: 5.468 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 994.427 Number of logic level(s): 12 Starting point: sdram.fifo_wb2sdr / Q[2] Ending point: sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_20 / D The start point is clocked by System [rising] The end point is clocked by wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- sdram.fifo_wb2sdr pmi_fifo_dc_Z3 Q[2] Out 0.000 0.000 - wb2sdr_q[2] Net - - - - 2 sdram.sdr_fifo_intf_uut.U2.sys_A_4_17_91_i_m2 ORCALUT4 C In 0.000 0.000 - sdram.sdr_fifo_intf_uut.U2.sys_A_4_17_91_i_m2 ORCALUT4 Z Out 1.089 1.089 - N_260 Net - - - - 2 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_0_0 CCU2D A1 In 0.000 1.089 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_0_0 CCU2D COUT Out 1.545 2.633 - next_adr_cry_0 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_1_0 CCU2D CIN In 0.000 2.633 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_1_0 CCU2D COUT Out 0.143 2.776 - next_adr_cry_2 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_3_0 CCU2D CIN In 0.000 2.776 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_3_0 CCU2D COUT Out 0.143 2.919 - next_adr_cry_4 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_5_0 CCU2D CIN In 0.000 2.919 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_5_0 CCU2D COUT Out 0.143 3.062 - next_adr_cry_6 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_7_0 CCU2D CIN In 0.000 3.062 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_7_0 CCU2D COUT Out 0.143 3.204 - next_adr_cry_8 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_9_0 CCU2D CIN In 0.000 3.204 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_9_0 CCU2D COUT Out 0.143 3.347 - next_adr_cry_10 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_11_0 CCU2D CIN In 0.000 3.347 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_11_0 CCU2D COUT Out 0.143 3.490 - next_adr_cry_12 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_13_0 CCU2D CIN In 0.000 3.490 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_13_0 CCU2D COUT Out 0.143 3.633 - next_adr_cry_14 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_15_0 CCU2D CIN In 0.000 3.633 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_15_0 CCU2D COUT Out 0.143 3.776 - next_adr_cry_16 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_17_0 CCU2D CIN In 0.000 3.776 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_17_0 CCU2D COUT Out 0.143 3.918 - next_adr_cry_18 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_19_0 CCU2D CIN In 0.000 3.918 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_19_0 CCU2D S1 Out 1.549 5.468 - next_adr_0[22] Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_20 FD1P3DX D In 0.000 5.468 - ====================================================================================================================== ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report Part: lcmxo2_7000hc-6 Register bits: 1979 of 6864 (29%) PIC Latch: 0 I/O cells: 47 Block Rams : 4 of 26 (15%) Details: BB: 16 CCU2D: 438 DP8KC: 4 DPR16X4C: 32 FD1P3AX: 39 FD1P3BX: 57 FD1P3DX: 1453 FD1S3BX: 25 FD1S3DX: 328 FD1S3IX: 20 FD1S3JX: 1 GSR: 1 IB: 4 IFS1P3DX: 1 INV: 20 OB: 27 OFS1P3BX: 35 OFS1P3DX: 20 ORCALUT4: 3041 PFUMX: 214 PUR: 1 VHI: 36 VLO: 41 false: 4 true: 9 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:26s; CPU Time elapsed 0h:00m:25s; Memory used current: 34MB peak: 145MB) Process took 0h:00m:26s realtime, 0h:00m:25s cputime # Fri Jun 21 15:16:08 2013 ###########################################################]