PAR: Place And Route Diamond Version 2.2.0.101.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
Fri Jun 21 15:16:27 2013

C:/lscc/diamond/2.2/ispfpga\bin\nt\par -f prj_diamond_ver0_prj_diamond_ver0.p2t
prj_diamond_ver0_prj_diamond_ver0_map.ncd prj_diamond_ver0_prj_diamond_ver0.dir
prj_diamond_ver0_prj_diamond_ver0.prf


Preference file: prj_diamond_ver0_prj_diamond_ver0.prf.

Cost Table Summary
Level/      Number      Worst       Timing      Run         NCD
Cost [ncd]  Unrouted    Slack       Score       Time        Status
----------  --------    -----       --------    -----       ------
5_1   *     0           -1.014      58541       01:47       Complete        


* : Design saved.

Total (real) run time for 1-seed: 1 mins 47 secs 

par done!

Lattice Place and Route Report for Design "prj_diamond_ver0_prj_diamond_ver0_map.ncd"
Fri Jun 21 15:16:27 2013


Best Par Run
PAR: Place And Route Diamond Version 2.2.0.101.
Command Line: par -w -l 5 -i 6 -t 1 -c 0 -e 0 -exp parUseNBR=1:parCDP=0:parCDR=0:parPathBased=OFF prj_diamond_ver0_prj_diamond_ver0_map.ncd prj_diamond_ver0_prj_diamond_ver0.dir/5_1.ncd prj_diamond_ver0_prj_diamond_ver0.prf
Preference file: prj_diamond_ver0_prj_diamond_ver0.prf.
Placement level-cost: 5-1.
Routing Iterations: 6

Loading design for application par from file prj_diamond_ver0_prj_diamond_ver0_map.ncd.
Design name: platform_rev0
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-7000HC
Package:     TQFP144
Performance: 6
Loading device for application par from file 'xo2c7000.nph' in environment: C:/lscc/diamond/2.2/ispfpga.
Package Status:                     Final          Version 1.36
Performance Hardware Data Status:   Final)         Version 23.4
License checked out.


Ignore Preference Error(s):  True

Device utilization summary:

   PIO (prelim)   47+4(JTAG)/336     13% used
                  47+4(JTAG)/115     40% bonded
   IOLOGIC           41/336          12% used

   SLICE           2292/3432         66% used

   GSR                1/1           100% used
   JTAG               1/1           100% used
   EBR               16/26           61% used
   PLL                1/2            50% used


INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.
Number of Signals: 7255
Number of Connections: 20922

Pin Constraint Summary:
   47 out of 47 pins locked (100% locked).

The following 4 signals are selected to use the primary clock routing resources:
    sdram.sdr_clk_c_c (driver: sdram/U1_pmi_pll/PLLInst_0, clk load #: 210)
    sdram/sdr_clk_io (driver: sdram/U1_pmi_pll/PLLInst_0, clk load #: 1)
    clk_i_c (driver: clk_i, clk load #: 1156)
    jtaghub16_jtck (driver: xo2chub/genblk0_genblk6_jtagf_u, clk load #: 39)

WARNING - par: Signal "clk_i_c" is selected to use Primary clock resources; however its driver comp "clk_i" is located at "3", which is not a dedicated pin for connecting to Primary clock resources.  General routing has to be used to route this signal, and it may suffer from excessive delay or skew.

The following 8 signals are selected to use the secondary clock routing resources:
    LM32/cpu/stall_m_i (driver: LM32/cpu/SLICE_1233, clk load #: 0, sr load #: 0, ce load #: 167)
    LM32/cpu/stall_x_i_0 (driver: LM32/cpu/SLICE_1198, clk load #: 0, sr load #: 0, ce load #: 145)
    LM32/cpu/stall_d_i (driver: LM32/cpu/decoder/SLICE_1915, clk load #: 0, sr load #: 0, ce load #: 48)
    counter[2] (driver: SLICE_1469, clk load #: 0, sr load #: 41, ce load #: 0)
    SPIFlash/wb_intf_inst/wb_state_0_sqmuxa (driver: SPIFlash/wb_intf_inst/SLICE_1450, clk load #: 0, sr load #: 0, ce load #: 40)
    sdram/fifo_wb2sdr/rden_i (driver: sdram/SLICE_1893, clk load #: 0, sr load #: 0, ce load #: 39)
    jtaghub16_jrstn (driver: xo2chub/genblk0_genblk6_jtagf_u, clk load #: 0, sr load #: 38, ce load #: 0)
    LM32/cpu/mc_arithmetic/N_59_i (driver: LM32/cpu/mc_arithmetic/SLICE_2342, clk load #: 0, sr load #: 0, ce load #: 36)

Signal counter[2] is selected as Global Set/Reset.
Starting Placer Phase 0.
...........
Finished Placer Phase 0.  REAL time: 14 secs 

Starting Placer Phase 1.
.....................
Placer score = 2623991.
Finished Placer Phase 1.  REAL time: 40 secs 

Starting Placer Phase 2.
.
Placer score =  2596674
Finished Placer Phase 2.  REAL time: 43 secs 



Clock Report

Global Clock Resources:
  CLK_PIN    : 0 out of 8 (0%)
  General PIO: 1 out of 336 (0%)
  PLL        : 1 out of 2 (50%)
  DCM        : 0 out of 2 (0%)
  DCC        : 0 out of 8 (0%)

Quadrants All (TL, TR, BL, BR) - Global Clocks:
  PRIMARY "sdram.sdr_clk_c_c" from CLKOP on comp "sdram/U1_pmi_pll/PLLInst_0" on PLL site "LPLL", clk load = 210
  PRIMARY "sdram/sdr_clk_io" from CLKOS on comp "sdram/U1_pmi_pll/PLLInst_0" on PLL site "LPLL", clk load = 1
  PRIMARY "clk_i_c" from comp "clk_i" on PIO site "3 (PL4A)", clk load = 1156
  PRIMARY "jtaghub16_jtck" from JTCK on comp "xo2chub/genblk0_genblk6_jtagf_u" on site "JTAG", clk load = 39
  SECONDARY "counter[2]" from Q0 on comp "SLICE_1469" on site "R21C18A", clk load = 0, ce load = 0, sr load = 41
  SECONDARY "SPIFlash/wb_intf_inst/wb_state_0_sqmuxa" from F1 on comp "SPIFlash/wb_intf_inst/SLICE_1450" on site "R14C18D", clk load = 0, ce load = 40, sr load = 0
  SECONDARY "sdram/fifo_wb2sdr/rden_i" from F1 on comp "sdram/SLICE_1893" on site "R22C9C", clk load = 0, ce load = 39, sr load = 0
  SECONDARY "LM32/cpu/stall_x_i_0" from F1 on comp "LM32/cpu/SLICE_1198" on site "R21C18C", clk load = 0, ce load = 145, sr load = 0
  SECONDARY "LM32/cpu/mc_arithmetic/N_59_i" from F1 on comp "LM32/cpu/mc_arithmetic/SLICE_2342" on site "R21C20A", clk load = 0, ce load = 36, sr load = 0
  SECONDARY "LM32/cpu/stall_m_i" from F1 on comp "LM32/cpu/SLICE_1233" on site "R21C18B", clk load = 0, ce load = 167, sr load = 0
  SECONDARY "LM32/cpu/stall_d_i" from F1 on comp "LM32/cpu/decoder/SLICE_1915" on site "R21C20C", clk load = 0, ce load = 48, sr load = 0
  SECONDARY "jtaghub16_jrstn" from JRSTN on comp "xo2chub/genblk0_genblk6_jtagf_u" on site "JTAG", clk load = 0, ce load = 0, sr load = 38

  PRIMARY  : 4 out of 8 (50%)
  SECONDARY: 8 out of 8 (100%)

Edge Clocks:
  No edge clock selected.




I/O Usage Summary (final):
   47 out of 336 (14.0%) PIO sites used.
   47 out of 115 (40.9%) bonded PIO sites used.
   Number of PIO comps: 47; differential: 0
   Number of Vref pins used: 0

I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage          | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0        | 1 / 28 (  3%)  | 3.3V       | -         |
| 1        | 27 / 29 ( 93%) | 3.3V       | -         |
| 2        | 16 / 29 ( 55%) | 3.3V       | -         |
| 3        | 0 / 9 (  0%)   | -          | -         |
| 4        | 0 / 10 (  0%)  | -          | -         |
| 5        | 3 / 10 ( 30%)  | 3.3V       | -         |
+----------+----------------+------------+-----------+

Total placer CPU time: 40 secs 

Dumping design to file prj_diamond_ver0_prj_diamond_ver0.dir/5_1.ncd.

0 connections routed; 20922 unrouted.
Starting router resource preassignment

WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
   Signal=LM32/jtag_update loads=1 clock_loads=1

Completed router resource preassignment. Real time: 51 secs 

Start NBR router at 15:17:18 06/21/13

*****************************************************************
Info: NBR allows conflicts(one node used by more than one signal)
      in the earlier iterations. In each iteration, it tries to  
      solve the conflicts while keeping the critical connections 
      routed as short as possible. The routing process is said to
      be completed when no conflicts exist and all connections   
      are routed.                                                
Note: NBR uses a different method to calculate timing slacks. The
      worst slack and total negative slack may not be the same as
      that in TRCE report. You should always run TRCE to verify  
      your design. Thanks.                                       
*****************************************************************

Start NBR special constraint process at 15:17:19 06/21/13

Start NBR section for initial routing
Level 1, iteration 1
173(0.05%) conflicts; 16062(76.77%) untouched conns; 65220 (nbr) score; 
Estimated worst slack/total negative slack: -0.894ns/-65.221ns; real time: 1 mins 11 secs 
Level 2, iteration 1
49(0.01%) conflicts; 15993(76.44%) untouched conns; 71300 (nbr) score; 
Estimated worst slack/total negative slack: -0.944ns/-71.301ns; real time: 1 mins 14 secs 
Level 3, iteration 1
48(0.01%) conflicts; 15794(75.49%) untouched conns; 75075 (nbr) score; 
Estimated worst slack/total negative slack: -0.965ns/-75.075ns; real time: 1 mins 16 secs 
Level 4, iteration 1
1075(0.28%) conflicts; 0(0.00%) untouched conn; 34961 (nbr) score; 
Estimated worst slack/total negative slack: -0.872ns/-34.961ns; real time: 1 mins 20 secs 

Info: Initial congestion level at 75% usage is 5
Info: Initial congestion area  at 75% usage is 108 (10.80%)

Start NBR section for normal routing
Level 1, iteration 1
20(0.01%) conflicts; 1568(7.49%) untouched conns; 43661 (nbr) score; 
Estimated worst slack/total negative slack: -0.791ns/-43.661ns; real time: 1 mins 27 secs 
Level 4, iteration 1
302(0.08%) conflicts; 0(0.00%) untouched conn; 39525 (nbr) score; 
Estimated worst slack/total negative slack: -0.924ns/-39.525ns; real time: 1 mins 34 secs 
Level 4, iteration 2
149(0.04%) conflicts; 0(0.00%) untouched conn; 54053 (nbr) score; 
Estimated worst slack/total negative slack: -0.878ns/-54.054ns; real time: 1 mins 35 secs 
Level 4, iteration 3
86(0.02%) conflicts; 0(0.00%) untouched conn; 44796 (nbr) score; 
Estimated worst slack/total negative slack: -0.924ns/-44.796ns; real time: 1 mins 36 secs 
Level 4, iteration 4
54(0.01%) conflicts; 0(0.00%) untouched conn; 44796 (nbr) score; 
Estimated worst slack/total negative slack: -0.924ns/-44.796ns; real time: 1 mins 36 secs 
Level 4, iteration 5
19(0.01%) conflicts; 0(0.00%) untouched conn; 52097 (nbr) score; 
Estimated worst slack/total negative slack: -1.014ns/-52.097ns; real time: 1 mins 37 secs 
Level 4, iteration 6
9(0.00%) conflicts; 0(0.00%) untouched conn; 52097 (nbr) score; 
Estimated worst slack/total negative slack: -1.014ns/-52.097ns; real time: 1 mins 37 secs 
Level 4, iteration 7
7(0.00%) conflicts; 0(0.00%) untouched conn; 51296 (nbr) score; 
Estimated worst slack/total negative slack: -1.014ns/-51.296ns; real time: 1 mins 38 secs 
Level 4, iteration 8
5(0.00%) conflicts; 0(0.00%) untouched conn; 51296 (nbr) score; 
Estimated worst slack/total negative slack: -1.014ns/-51.296ns; real time: 1 mins 38 secs 
Level 4, iteration 9
1(0.00%) conflict; 0(0.00%) untouched conn; 51296 (nbr) score; 
Estimated worst slack/total negative slack: -1.014ns/-51.296ns; real time: 1 mins 38 secs 
Level 4, iteration 10
1(0.00%) conflict; 0(0.00%) untouched conn; 51296 (nbr) score; 
Estimated worst slack/total negative slack: -1.014ns/-51.296ns; real time: 1 mins 38 secs 
Level 4, iteration 11
0(0.00%) conflict; 0(0.00%) untouched conn; 51296 (nbr) score; 
Estimated worst slack/total negative slack: -1.014ns/-51.296ns; real time: 1 mins 38 secs 

Start NBR section for performance tunning (iteration 1)
Level 4, iteration 1
5(0.00%) conflicts; 0(0.00%) untouched conn; 42365 (nbr) score; 
Estimated worst slack/total negative slack: -0.885ns/-42.365ns; real time: 1 mins 39 secs 
Level 4, iteration 2
1(0.00%) conflict; 0(0.00%) untouched conn; 43440 (nbr) score; 
Estimated worst slack/total negative slack: -0.891ns/-43.441ns; real time: 1 mins 39 secs 
Level 4, iteration 3
1(0.00%) conflict; 0(0.00%) untouched conn; 48631 (nbr) score; 
Estimated worst slack/total negative slack: -1.073ns/-48.632ns; real time: 1 mins 40 secs 

Start NBR section for re-routing
Level 4, iteration 1
0(0.00%) conflict; 0(0.00%) untouched conn; 51296 (nbr) score; 
Estimated worst slack/total negative slack: -1.014ns/-51.296ns; real time: 1 mins 41 secs 

Start NBR section for post-routing

End NBR router with 0 unrouted connection

NBR Summary
-----------
  Number of unrouted connections : 0 (0.00%)
  Number of connections with timing violations : 107 (0.51%)
  Estimated worst slack : -1.014ns
  Timing score : 58541
-----------
Notes: The timing info is calculated for SETUP only and all PAR_ADJs are ignored.



------------------------------------------------------------------------------------------------------------------------------------
WARNING - par: Hold timing correction is skipped because the worst (setup) slack(-1.014ns) is worse than the default value(0.000ns).
------------------------------------------------------------------------------------------------------------------------------------

Total CPU time 1 mins 41 secs 
Total REAL time: 1 mins 45 secs 
Completely routed.
End of route.  20922 routed (100.00%); 0 unrouted.
Checking DRC ... 
No errors found.

Hold time timing score: 0, hold timing errors: 0

Timing score: 58541 

Dumping design to file prj_diamond_ver0_prj_diamond_ver0.dir/5_1.ncd.


All signals are completely routed.


PAR_SUMMARY::Run status = completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst  slack> = -1.014
PAR_SUMMARY::Timing score> = 58.541
PAR_SUMMARY::Worst  slack> = 
PAR_SUMMARY::Timing score> = 

Total CPU  time to completion: 1 mins 43 secs 
Total REAL time to completion: 1 mins 47 secs 

par done!

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.