PAR: Place And Route Diamond Version 2.2.0.101.
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.
Fri Aug 02 09:57:53 2013

C:/lscc/diamond/2.2/ispfpga\bin\nt\par -f tftsurfer_tftsurfer.p2t
tftsurfer_tftsurfer_map.ncd tftsurfer_tftsurfer.dir tftsurfer_tftsurfer.prf


Preference file: tftsurfer_tftsurfer.prf.

Cost Table Summary
Level/      Number      Worst       Timing      Run         NCD
Cost [ncd]  Unrouted    Slack       Score       Time        Status
----------  --------    -----       --------    -----       ------
5_2   *     0           1.338       0           01:09       Complete        
5_1         0           0.114       0           01:17       Complete        


* : Design saved.

Total (real) run time for 2-seed: 2 mins 27 secs 

par done!

Lattice Place and Route Report for Design "tftsurfer_tftsurfer_map.ncd"
Fri Aug 02 09:59:11 2013


Best Par Run
PAR: Place And Route Diamond Version 2.2.0.101.
Command Line: par -w -l 5 -i 6 -t 2 -c 0 -e 0 -exp parUseNBR=0:parCDP=0:parCDR=0:parPathBased=OFF:parHold=0 tftsurfer_tftsurfer_map.ncd tftsurfer_tftsurfer.dir/5_2.ncd tftsurfer_tftsurfer.prf
Preference file: tftsurfer_tftsurfer.prf.
Placement level-cost: 5-2.
Routing Iterations: 6

Loading design for application par from file C:/DOCUME~1/FFERRARI/LOCALS~1/Temp/neo_63.
Design name: top_conMICO32
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-7000HC
Package:     TQFP144
Performance: 6
Package Status:                     Final          Version 1.36
Performance Hardware Data Status:   Final)         Version 23.4

Device utilization summary:

   PIO (prelim)   78+4(JTAG)/336     23% used
                  78+4(JTAG)/115     67% bonded
   IOLOGIC           47/336          13% used

   SLICE           2794/3432         81% used

   GSR                1/1           100% used
   OSC                1/1           100% used
   JTAG               1/1           100% used
   EBR               26/26          100% used
   PLL                1/2            50% used


INFO: Design contains pre-loadable EBR during configuration that has a requirement: Since the GSR is disabled for the EBR, make sure write enable and chip enable are inactive during wake-up, so that the pre-loaded initialization values will not be corrupted during wake-up state.
Number of Signals: 7470
Number of Connections: 21355

Pin Constraint Summary:
   78 out of 78 pins locked (100% locked).

The following 5 signals are selected to use the primary clock routing resources:
    controller_marco.sys_clk_sig_c (driver: controller_marco/PLL_BLOCK_INST/PLLInst_0, clk load #: 380)
    ext_osc_clk_c (driver: ext_osc_clk, clk load #: 999)
    tft_clk_c_c (driver: controller_marco/PLL_BLOCK_INST/PLLInst_0, clk load #: 285)
    jtaghub16_jtck (driver: xo2chub/genblk0_genblk6_jtagf_u, clk load #: 40)
    controller_marco/osch_clk_sig_c (driver: controller_marco/OSCH_INST, clk load #: 17)

WARNING - par: Signal "ext_osc_clk_c" is selected to use Primary clock resources; however its driver comp "ext_osc_clk" is located at "3", which is not a dedicated pin for connecting to Primary clock resources.  General routing has to be used to route this signal, and it may suffer from excessive delay or skew.

The following 8 signals are selected to use the secondary clock routing resources:
    lm32_inst/platform_u/counter[2] (driver: lm32_inst/platform_u/SLICE_1996, clk load #: 0, sr load #: 750, ce load #: 0)
    lm32_inst/platform_u/LM32/cpu/stall_d_i (driver: lm32_inst/platform_u/LM32/cpu/instruction_unit/SLICE_2439, clk load #: 0, sr load #: 0, ce load #: 65)
    lm32_inst/platform_u/LM32/cpu/stall_x_i_1 (driver: lm32_inst/platform_u/LM32/cpu/instruction_unit/SLICE_2555, clk load #: 0, sr load #: 0, ce load #: 59)
    lm32_inst/platform_u/LM32/cpu/stall_m_i_1 (driver: lm32_inst/platform_u/LM32/cpu/SLICE_1551, clk load #: 0, sr load #: 0, ce load #: 53)
    lm32_inst/platform_u/LM32/cpu/stall_x_i (driver: lm32_inst/platform_u/LM32/cpu/SLICE_2443, clk load #: 0, sr load #: 0, ce load #: 52)
    lm32_inst/platform_u/LM32/cpu/stall_x_i_2 (driver: lm32_inst/platform_u/LM32/cpu/instruction_unit/SLICE_2555, clk load #: 0, sr load #: 0, ce load #: 51)
    lm32_inst/platform_u/LM32/cpu/stall_m_i (driver: lm32_inst/platform_u/LM32/cpu/SLICE_2445, clk load #: 0, sr load #: 0, ce load #: 50)
    lm32_inst/platform_u/ebr/read_enable4 (driver: lm32_inst/platform_u/ebr/SLICE_1998, clk load #: 0, sr load #: 0, ce load #: 46)

Signal rst_button_c is selected as Global Set/Reset.
Starting Placer Phase 0.
...........
Finished Placer Phase 0.  REAL time: 14 secs 

Starting Placer Phase 1.
.........................
Placer score = 1696643.
Finished Placer Phase 1.  REAL time: 42 secs 

Starting Placer Phase 2.
.
Placer score =  1674132
Finished Placer Phase 2.  REAL time: 45 secs 



Clock Report

Global Clock Resources:
  CLK_PIN    : 0 out of 8 (0%)
  General PIO: 1 out of 336 (0%)
  PLL        : 1 out of 2 (50%)
  DCM        : 0 out of 2 (0%)
  DCC        : 0 out of 8 (0%)

Quadrants All (TL, TR, BL, BR) - Global Clocks:
  PRIMARY "controller_marco.sys_clk_sig_c" from CLKOP on comp "controller_marco/PLL_BLOCK_INST/PLLInst_0" on PLL site "LPLL", clk load = 380
  PRIMARY "ext_osc_clk_c" from comp "ext_osc_clk" on PIO site "3 (PL4A)", clk load = 999
  PRIMARY "tft_clk_c_c" from CLKOS3 on comp "controller_marco/PLL_BLOCK_INST/PLLInst_0" on PLL site "LPLL", clk load = 285
  PRIMARY "jtaghub16_jtck" from JTCK on comp "xo2chub/genblk0_genblk6_jtagf_u" on site "JTAG", clk load = 40
  PRIMARY "controller_marco/osch_clk_sig_c" from OSC on comp "controller_marco/OSCH_INST" on site "OSC", clk load = 17
  SECONDARY "lm32_inst/platform_u/LM32/cpu/stall_d_i" from F0 on comp "lm32_inst/platform_u/LM32/cpu/instruction_unit/SLICE_2439" on site "R21C18D", clk load = 0, ce load = 65, sr load = 0
  SECONDARY "lm32_inst/platform_u/LM32/cpu/stall_x_i_1" from F0 on comp "lm32_inst/platform_u/LM32/cpu/instruction_unit/SLICE_2555" on site "R14C20B", clk load = 0, ce load = 59, sr load = 0
  SECONDARY "lm32_inst/platform_u/LM32/cpu/stall_x_i_2" from F1 on comp "lm32_inst/platform_u/LM32/cpu/instruction_unit/SLICE_2555" on site "R14C20B", clk load = 0, ce load = 51, sr load = 0
  SECONDARY "lm32_inst/platform_u/LM32/cpu/stall_x_i" from F0 on comp "lm32_inst/platform_u/LM32/cpu/SLICE_2443" on site "R14C18B", clk load = 0, ce load = 52, sr load = 0
  SECONDARY "lm32_inst/platform_u/LM32/cpu/stall_m_i_1" from F1 on comp "lm32_inst/platform_u/LM32/cpu/SLICE_1551" on site "R14C20D", clk load = 0, ce load = 53, sr load = 0
  SECONDARY "lm32_inst/platform_u/counter[2]" from Q0 on comp "lm32_inst/platform_u/SLICE_1996" on site "R4C40C", clk load = 0, ce load = 0, sr load = 750
  SECONDARY "lm32_inst/platform_u/LM32/cpu/stall_m_i" from F0 on comp "lm32_inst/platform_u/LM32/cpu/SLICE_2445" on site "R14C20A", clk load = 0, ce load = 50, sr load = 0
  SECONDARY "lm32_inst/platform_u/ebr/read_enable4" from F1 on comp "lm32_inst/platform_u/ebr/SLICE_1998" on site "R21C20C", clk load = 0, ce load = 46, sr load = 0

  PRIMARY  : 5 out of 8 (62%)
  SECONDARY: 8 out of 8 (100%)

Edge Clocks:
  No edge clock selected.




I/O Usage Summary (final):
   78 out of 336 (23.2%) PIO sites used.
   78 out of 115 (67.8%) bonded PIO sites used.
   Number of PIO comps: 78; differential: 0
   Number of Vref pins used: 0

I/O Bank Usage Summary:
+----------+----------------+------------+-----------+
| I/O Bank | Usage          | Bank Vccio | Bank Vref |
+----------+----------------+------------+-----------+
| 0        | 20 / 28 ( 71%) | 3.3V       | -         |
| 1        | 28 / 29 ( 96%) | 3.3V       | -         |
| 2        | 19 / 29 ( 65%) | 3.3V       | -         |
| 3        | 6 / 9 ( 66%)   | 3.3V       | -         |
| 4        | 0 / 10 (  0%)  | -          | -         |
| 5        | 5 / 10 ( 50%)  | 3.3V       | -         |
+----------+----------------+------------+-----------+

Total placer CPU time: 45 secs 

Dumping design to file tftsurfer_tftsurfer.dir/5_2.ncd.

0 connections routed; 21355 unrouted.
Starting router resource preassignment

WARNING - par: The following clock signals will be routed by using generic routing resource and may suffer from excessive delay and/or skew.
   Signal=lm32_inst/platform_u/LM32/jtag_update loads=1 clock_loads=1

Completed router resource preassignment. Real time: 54 secs 
Starting iterative routing.

For each routing iteration the number inside the parenthesis is the
total time (in picoseconds) the design is failing the timing constraints.
For each routing iteration the router will attempt to reduce this number
until the number of routing iterations is completed or the value is 0
meaning the design has fully met the timing constraints.

End of iteration 1
21355 successful; 0 unrouted; (0) real time: 1 mins 5 secs 
Dumping design to file tftsurfer_tftsurfer.dir/5_2.ncd.
Total CPU time 1 mins 6 secs 
Total REAL time: 1 mins 7 secs 
Completely routed.
End of route.  21355 routed (100.00%); 0 unrouted.
Checking DRC ... 
No errors found.

Timing score: 0 

Dumping design to file tftsurfer_tftsurfer.dir/5_2.ncd.


All signals are completely routed.


PAR_SUMMARY::Run status = completed
PAR_SUMMARY::Number of unrouted conns = 0
PAR_SUMMARY::Worst  slack> = 1.338
PAR_SUMMARY::Timing score> = 0.000
PAR_SUMMARY::Worst  slack> = 
PAR_SUMMARY::Timing score> = 

Total CPU  time to completion: 1 mins 9 secs 
Total REAL time to completion: 1 mins 10 secs 

par done!

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation,  All rights reserved.