#INFO: (ST-1216) Setting log file to 'C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/tftsurfer/hdldiagram_gen_hierarchy.html'. FileList::LoadDesign #-- (VHDL-1504) The default vhdl library search path is now "c:/lscc/diamond/2.0/cae_library/vhdl_packages/vdbs" #-- (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.vhd #-- (VHDL-1493) Restoring VHDL parse-tree ieee.std_logic_1164 from c:/lscc/diamond/2.0/cae_library/vhdl_packages/vdbs/ieee/std_logic_1164.vdb #-- (VHDL-1493) Restoring VHDL parse-tree std.standard from c:/lscc/diamond/2.0/cae_library/vhdl_packages/vdbs/std/standard.vdb #-- (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/monster_manager.vhd #-- (VHDL-1493) Restoring VHDL parse-tree ieee.std_logic_unsigned from c:/lscc/diamond/2.0/cae_library/vhdl_packages/vdbs/ieee/std_logic_unsigned.vdb #-- (VHDL-1493) Restoring VHDL parse-tree ieee.std_logic_arith from c:/lscc/diamond/2.0/cae_library/vhdl_packages/vdbs/ieee/std_logic_arith.vdb #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/monster_manager.vhd(48,8-48,23) INFO: (VHDL-1012) analyzing entity monster_manager #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/monster_manager.vhd(105,14-105,33) INFO: (VHDL-1010) analyzing architecture rtl_monster_manager #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/pixel_addr_data_fifo.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/pixel_addr_data_fifo.vhd(44,8-44,28) INFO: (VHDL-1012) analyzing entity pixel_addr_data_fifo #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/pixel_addr_data_fifo.vhd(64,14-64,38) INFO: (VHDL-1010) analyzing architecture rtl_pixel_addr_data_fifo #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/power_manager.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/power_manager.vhd(52,8-52,21) INFO: (VHDL-1012) analyzing entity power_manager #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/power_manager.vhd(72,14-72,31) INFO: (VHDL-1010) analyzing architecture rtl_power_manager #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/sdram_pkg.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/sdram_pkg.vhd(22,9-22,18) INFO: (VHDL-1014) analyzing package sdram_pkg #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/sdram_ctrl.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/sdram_ctrl.vhd(24,8-24,18) INFO: (VHDL-1012) analyzing entity sdram_ctrl #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/sdram_ctrl.vhd(62,14-62,28) INFO: (VHDL-1010) analyzing architecture rtl_sdram_ctrl #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/tft_on_off_button_ctrl.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tft_on_off_button_ctrl.vhd(45,8-45,30) INFO: (VHDL-1012) analyzing entity tft_on_off_button_ctrl #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tft_on_off_button_ctrl.vhd(56,14-56,40) INFO: (VHDL-1010) analyzing architecture rtl_tft_on_off_button_ctrl #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/tft_pkg.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tft_pkg.vhd(71,9-71,16) INFO: (VHDL-1014) analyzing package tft_pkg #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/tft_timing_ctrl.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tft_timing_ctrl.vhd(75,8-75,23) INFO: (VHDL-1012) analyzing entity tft_timing_ctrl #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tft_timing_ctrl.vhd(107,14-107,33) INFO: (VHDL-1010) analyzing architecture rtl_tft_timing_ctrl #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/ipexpress/pixel_addr_fifo.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_addr_fifo.vhd(14,8-14,23) INFO: (VHDL-1012) analyzing entity pixel_addr_fifo #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_addr_fifo.vhd(28,14-28,23) INFO: (VHDL-1010) analyzing architecture structure #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_addr_fifo.vhd(979,15-979,28) INFO: (VHDL-1011) analyzing configuration structure_con #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/ipexpress/pixel_data_fifo.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_data_fifo.vhd(14,8-14,23) INFO: (VHDL-1012) analyzing entity pixel_data_fifo #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_data_fifo.vhd(29,14-29,23) INFO: (VHDL-1010) analyzing architecture structure #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_data_fifo.vhd(943,15-943,28) INFO: (VHDL-1011) analyzing configuration structure_con #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_data_fifo.vhd(943,15-943,28) WARNING: (VHDL-1177) overwriting existing primary unit structure_con #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/ipexpress/pll_block.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pll_block.vhd(14,8-14,17) INFO: (VHDL-1012) analyzing entity pll_block #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pll_block.vhd(26,14-26,23) INFO: (VHDL-1010) analyzing architecture structure #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pll_block.vhd(166,15-166,28) INFO: (VHDL-1011) analyzing configuration structure_con #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pll_block.vhd(166,15-166,28) WARNING: (VHDL-1177) overwriting existing primary unit structure_con #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/tft_pixel_rgb_pipeliner.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tft_pixel_rgb_pipeliner.vhd(44,8-44,31) INFO: (VHDL-1012) analyzing entity tft_pixel_rgb_pipeliner #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tft_pixel_rgb_pipeliner.vhd(62,14-62,41) INFO: (VHDL-1010) analyzing architecture rtl_tft_pixel_rgb_pipeliner #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/ipexpress/pixel_rgb_fifo.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_rgb_fifo.vhd(14,8-14,22) INFO: (VHDL-1012) analyzing entity pixel_rgb_fifo #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_rgb_fifo.vhd(28,14-28,23) INFO: (VHDL-1010) analyzing architecture structure #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_rgb_fifo.vhd(885,15-885,28) INFO: (VHDL-1011) analyzing configuration structure_con #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_rgb_fifo.vhd(885,15-885,28) WARNING: (VHDL-1177) overwriting existing primary unit structure_con #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/img_mover_viewer.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/img_mover_viewer.vhd(19,8-19,24) INFO: (VHDL-1012) analyzing entity img_mover_viewer #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/img_mover_viewer.vhd(46,14-46,34) INFO: (VHDL-1010) analyzing architecture rtl_img_mover_viewer #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/micro_emulator.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/micro_emulator.vhd(19,8-19,22) INFO: (VHDL-1012) analyzing entity micro_emulator #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/micro_emulator.vhd(36,14-36,32) INFO: (VHDL-1010) analyzing architecture rtl_micro_emulator #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/spi_flash_reader.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/spi_flash_reader.vhd(19,8-19,24) INFO: (VHDL-1012) analyzing entity spi_flash_reader #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/spi_flash_reader.vhd(39,14-39,34) INFO: (VHDL-1010) analyzing architecture rtl_spi_flash_reader #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/tftsurfer_demo.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/tftsurfer_demo.vhd(18,8-18,22) INFO: (VHDL-1012) analyzing entity tftsurfer_demo #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/tftsurfer_demo.vhd(41,14-41,32) INFO: (VHDL-1010) analyzing architecture rtl_tftsurfer_demo #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_imager/img_spi_sector_rom.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_imager/img_spi_sector_rom.vhd(14,8-14,26) INFO: (VHDL-1012) analyzing entity img_spi_sector_rom #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_imager/img_spi_sector_rom.vhd(23,14-23,23) INFO: (VHDL-1010) analyzing architecture structure #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_imager/img_spi_sector_rom.vhd(140,15-140,28) INFO: (VHDL-1011) analyzing configuration structure_con #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_imager/img_spi_sector_rom.vhd(140,15-140,28) WARNING: (VHDL-1177) overwriting existing primary unit structure_con #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/wb_interface.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/wb_interface.vhd(6,8-6,20) INFO: (VHDL-1012) analyzing entity wb_interface #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/wb_interface.vhd(36,14-36,30) INFO: (VHDL-1010) analyzing architecture rtl_wb_interface #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/tftsurfer_top.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tftsurfer_top.vhd(48,8-48,21) INFO: (VHDL-1012) analyzing entity tftsurfer_top #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tftsurfer_top.vhd(108,14-108,31) INFO: (VHDL-1010) analyzing architecture rtl_tftsurfer_top #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src_spi/SPI_top.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src_spi/spi_top.vhd(6,8-6,15) INFO: (VHDL-1012) analyzing entity spi_top #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src_spi/spi_top.vhd(36,14-36,25) INFO: (VHDL-1010) analyzing architecture rtl_spi_top #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/mico32_ver0/top_conMICO32vhd.vhd #c:/work/project/artekit/mico32_ver0/top_conmico32vhd.vhd(4,8-4,21) INFO: (VHDL-1012) analyzing entity top_conmico32 #c:/work/project/artekit/mico32_ver0/top_conmico32vhd.vhd(44,14-44,29) INFO: (VHDL-1010) analyzing architecture top_conmico32_a #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src_spi/memoria.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src_spi/memoria.vhd(14,8-14,15) INFO: (VHDL-1012) analyzing entity memoria #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src_spi/memoria.vhd(25,14-25,23) INFO: (VHDL-1010) analyzing architecture structure #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src_spi/memoria.vhd(124,15-124,28) INFO: (VHDL-1011) analyzing configuration structure_con #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src_spi/memoria.vhd(124,15-124,28) WARNING: (VHDL-1177) overwriting existing primary unit structure_con #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/wb_add_fifo.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_d12/wb_add_fifo.vhd(14,8-14,19) INFO: (VHDL-1012) analyzing entity wb_add_fifo #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_d12/wb_add_fifo.vhd(28,14-28,23) INFO: (VHDL-1010) analyzing architecture structure #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_d12/wb_add_fifo.vhd(574,15-574,28) INFO: (VHDL-1011) analyzing configuration structure_con #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_d12/wb_add_fifo.vhd(574,15-574,28) WARNING: (VHDL-1177) overwriting existing primary unit structure_con #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/wb_data_fifo.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_d12/wb_data_fifo.vhd(14,8-14,20) INFO: (VHDL-1012) analyzing entity wb_data_fifo #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_d12/wb_data_fifo.vhd(28,14-28,23) INFO: (VHDL-1010) analyzing architecture structure #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_d12/wb_data_fifo.vhd(514,15-514,28) INFO: (VHDL-1011) analyzing configuration structure_con #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_d12/wb_data_fifo.vhd(514,15-514,28) WARNING: (VHDL-1177) overwriting existing primary unit structure_con #-- (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.vhd #-- (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/monster_manager.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/monster_manager.vhd(48,8-48,23) INFO: (VHDL-1012) analyzing entity monster_manager #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/monster_manager.vhd(105,14-105,33) INFO: (VHDL-1010) analyzing architecture rtl_monster_manager #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/pixel_addr_data_fifo.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/pixel_addr_data_fifo.vhd(44,8-44,28) INFO: (VHDL-1012) analyzing entity pixel_addr_data_fifo #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/pixel_addr_data_fifo.vhd(64,14-64,38) INFO: (VHDL-1010) analyzing architecture rtl_pixel_addr_data_fifo #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/power_manager.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/power_manager.vhd(52,8-52,21) INFO: (VHDL-1012) analyzing entity power_manager #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/power_manager.vhd(72,14-72,31) INFO: (VHDL-1010) analyzing architecture rtl_power_manager #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/sdram_pkg.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/sdram_pkg.vhd(22,9-22,18) INFO: (VHDL-1014) analyzing package sdram_pkg #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/sdram_ctrl.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/sdram_ctrl.vhd(24,8-24,18) INFO: (VHDL-1012) analyzing entity sdram_ctrl #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/sdram_ctrl.vhd(62,14-62,28) INFO: (VHDL-1010) analyzing architecture rtl_sdram_ctrl #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/tft_on_off_button_ctrl.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tft_on_off_button_ctrl.vhd(45,8-45,30) INFO: (VHDL-1012) analyzing entity tft_on_off_button_ctrl #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tft_on_off_button_ctrl.vhd(56,14-56,40) INFO: (VHDL-1010) analyzing architecture rtl_tft_on_off_button_ctrl #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/tft_pkg.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tft_pkg.vhd(71,9-71,16) INFO: (VHDL-1014) analyzing package tft_pkg #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/tft_timing_ctrl.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tft_timing_ctrl.vhd(75,8-75,23) INFO: (VHDL-1012) analyzing entity tft_timing_ctrl #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tft_timing_ctrl.vhd(107,14-107,33) INFO: (VHDL-1010) analyzing architecture rtl_tft_timing_ctrl #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/ipexpress/pixel_addr_fifo.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_addr_fifo.vhd(14,8-14,23) INFO: (VHDL-1012) analyzing entity pixel_addr_fifo #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_addr_fifo.vhd(28,14-28,23) INFO: (VHDL-1010) analyzing architecture structure #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_addr_fifo.vhd(979,15-979,28) INFO: (VHDL-1011) analyzing configuration structure_con #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_addr_fifo.vhd(979,15-979,28) WARNING: (VHDL-1177) overwriting existing primary unit structure_con #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/ipexpress/pixel_data_fifo.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_data_fifo.vhd(14,8-14,23) INFO: (VHDL-1012) analyzing entity pixel_data_fifo #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_data_fifo.vhd(29,14-29,23) INFO: (VHDL-1010) analyzing architecture structure #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_data_fifo.vhd(943,15-943,28) INFO: (VHDL-1011) analyzing configuration structure_con #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_data_fifo.vhd(943,15-943,28) WARNING: (VHDL-1177) overwriting existing primary unit structure_con #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/ipexpress/pll_block.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pll_block.vhd(14,8-14,17) INFO: (VHDL-1012) analyzing entity pll_block #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pll_block.vhd(26,14-26,23) INFO: (VHDL-1010) analyzing architecture structure #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pll_block.vhd(166,15-166,28) INFO: (VHDL-1011) analyzing configuration structure_con #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pll_block.vhd(166,15-166,28) WARNING: (VHDL-1177) overwriting existing primary unit structure_con #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/tft_pixel_rgb_pipeliner.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tft_pixel_rgb_pipeliner.vhd(44,8-44,31) INFO: (VHDL-1012) analyzing entity tft_pixel_rgb_pipeliner #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tft_pixel_rgb_pipeliner.vhd(62,14-62,41) INFO: (VHDL-1010) analyzing architecture rtl_tft_pixel_rgb_pipeliner #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/ipexpress/pixel_rgb_fifo.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_rgb_fifo.vhd(14,8-14,22) INFO: (VHDL-1012) analyzing entity pixel_rgb_fifo #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_rgb_fifo.vhd(28,14-28,23) INFO: (VHDL-1010) analyzing architecture structure #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_rgb_fifo.vhd(885,15-885,28) INFO: (VHDL-1011) analyzing configuration structure_con #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_rgb_fifo.vhd(885,15-885,28) WARNING: (VHDL-1177) overwriting existing primary unit structure_con #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/img_mover_viewer.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/img_mover_viewer.vhd(19,8-19,24) INFO: (VHDL-1012) analyzing entity img_mover_viewer #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/img_mover_viewer.vhd(46,14-46,34) INFO: (VHDL-1010) analyzing architecture rtl_img_mover_viewer #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/micro_emulator.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/micro_emulator.vhd(19,8-19,22) INFO: (VHDL-1012) analyzing entity micro_emulator #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/micro_emulator.vhd(36,14-36,32) INFO: (VHDL-1010) analyzing architecture rtl_micro_emulator #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/spi_flash_reader.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/spi_flash_reader.vhd(19,8-19,24) INFO: (VHDL-1012) analyzing entity spi_flash_reader #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/spi_flash_reader.vhd(39,14-39,34) INFO: (VHDL-1010) analyzing architecture rtl_spi_flash_reader #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/tftsurfer_demo.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/tftsurfer_demo.vhd(18,8-18,22) INFO: (VHDL-1012) analyzing entity tftsurfer_demo #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/tftsurfer_demo.vhd(41,14-41,32) INFO: (VHDL-1010) analyzing architecture rtl_tftsurfer_demo #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_imager/img_spi_sector_rom.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_imager/img_spi_sector_rom.vhd(14,8-14,26) INFO: (VHDL-1012) analyzing entity img_spi_sector_rom #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_imager/img_spi_sector_rom.vhd(23,14-23,23) INFO: (VHDL-1010) analyzing architecture structure #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_imager/img_spi_sector_rom.vhd(140,15-140,28) INFO: (VHDL-1011) analyzing configuration structure_con #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_imager/img_spi_sector_rom.vhd(140,15-140,28) WARNING: (VHDL-1177) overwriting existing primary unit structure_con #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/wb_interface.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/wb_interface.vhd(6,8-6,20) INFO: (VHDL-1012) analyzing entity wb_interface #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/wb_interface.vhd(36,14-36,30) INFO: (VHDL-1010) analyzing architecture rtl_wb_interface #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src/tftsurfer_top.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tftsurfer_top.vhd(48,8-48,21) INFO: (VHDL-1012) analyzing entity tftsurfer_top #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tftsurfer_top.vhd(108,14-108,31) INFO: (VHDL-1010) analyzing architecture rtl_tftsurfer_top #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src_spi/SPI_top.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src_spi/spi_top.vhd(6,8-6,15) INFO: (VHDL-1012) analyzing entity spi_top #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src_spi/spi_top.vhd(36,14-36,25) INFO: (VHDL-1010) analyzing architecture rtl_spi_top #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/mico32_ver0/top_conMICO32vhd.vhd #c:/work/project/artekit/mico32_ver0/top_conmico32vhd.vhd(4,8-4,21) INFO: (VHDL-1012) analyzing entity top_conmico32 #c:/work/project/artekit/mico32_ver0/top_conmico32vhd.vhd(44,14-44,29) INFO: (VHDL-1010) analyzing architecture top_conmico32_a #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/src_spi/memoria.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src_spi/memoria.vhd(14,8-14,15) INFO: (VHDL-1012) analyzing entity memoria #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src_spi/memoria.vhd(25,14-25,23) INFO: (VHDL-1010) analyzing architecture structure #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src_spi/memoria.vhd(124,15-124,28) INFO: (VHDL-1011) analyzing configuration structure_con #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src_spi/memoria.vhd(124,15-124,28) WARNING: (VHDL-1177) overwriting existing primary unit structure_con #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/wb_add_fifo.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_d12/wb_add_fifo.vhd(14,8-14,19) INFO: (VHDL-1012) analyzing entity wb_add_fifo #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_d12/wb_add_fifo.vhd(28,14-28,23) INFO: (VHDL-1010) analyzing architecture structure #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_d12/wb_add_fifo.vhd(574,15-574,28) INFO: (VHDL-1011) analyzing configuration structure_con #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_d12/wb_add_fifo.vhd(574,15-574,28) WARNING: (VHDL-1177) overwriting existing primary unit structure_con #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/wb_data_fifo.vhd #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_d12/wb_data_fifo.vhd(14,8-14,20) INFO: (VHDL-1012) analyzing entity wb_data_fifo #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_d12/wb_data_fifo.vhd(28,14-28,23) INFO: (VHDL-1010) analyzing architecture structure #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_d12/wb_data_fifo.vhd(514,15-514,28) INFO: (VHDL-1011) analyzing configuration structure_con #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_d12/wb_data_fifo.vhd(514,15-514,28) WARNING: (VHDL-1177) overwriting existing primary unit structure_con #-- (VERI-1482) Analyzing Verilog file C:/work/project/artekit/mico32_ver0/platform/soc/platform.v #c:/work/project/artekit/mico32_ver0/platform/soc/platform.v(46,10-46,25) -- (VERI-1328) analyzing included file C:/work/project/artekit/mico32_ver0/platform/soc/system_conf.v #c:/work/project/artekit/mico32_ver0/platform/soc/platform.v(327,10-327,65) -- (VERI-1328) analyzing included file C:/work/project/artekit/mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_include_all.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(52,10-52,21) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/pmi_def.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(54,10-54,25) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/system_conf.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(57,12-57,54) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/er1.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(58,12-58,56) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/typeb.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(59,12-59,56) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/typea.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(60,12-60,61) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/jtag_cores.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/jtag_cores.v(53,10-53,25) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/system_conf.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/jtag_cores.v(54,10-54,26) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_include.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include.v(60,10-60,25) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/system_conf.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(61,12-61,60) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/jtag_lm32.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(62,12-62,60) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_jtag.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_jtag.v(52,10-52,26) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_include.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(65,10-65,60) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_addsub.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_addsub.v(49,10-49,26) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_include.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(66,10-66,59) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_adder.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_adder.v(50,10-50,26) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_include.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(67,10-67,57) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_cpu.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_cpu.v(94,10-94,26) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_include.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_cpu.v(791,10-791,28) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_functions.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_functions.v(54,9-54,14) WARNING: (VERI-1214) assignment to input value #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(68,10-68,60) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_dcache.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_dcache.v(52,10-52,26) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_include.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(69,10-69,59) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_debug.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_debug.v(53,10-53,26) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_include.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_debug.v(186,10-186,28) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_functions.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(70,10-70,61) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_decoder.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_decoder.v(56,10-56,26) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_include.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_decoder.v(336,10-336,28) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_functions.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(71,10-71,60) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_icache.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_icache.v(57,10-57,26) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_include.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(72,10-72,70) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_instruction_unit.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_instruction_unit.v(71,10-71,26) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_include.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_instruction_unit.v(380,10-380,28) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_functions.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(73,10-73,63) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_interrupt.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_interrupt.v(50,10-50,26) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_include.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(74,10-74,69) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_load_store_unit.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_load_store_unit.v(63,10-63,26) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_include.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_load_store_unit.v(283,10-283,28) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_functions.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(75,10-75,62) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_logic_op.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_logic_op.v(50,10-50,26) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_include.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(77,10-77,67) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_mc_arithmetic.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_mc_arithmetic.v(50,10-50,26) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_include.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(80,12-80,66) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_multiplier.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_multiplier.v(50,10-50,26) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_include.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(85,10-85,57) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_top.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_top.v(52,10-52,26) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_include.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_top.v(277,10-277,28) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_functions.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(87,12-87,63) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_monitor.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_monitor.v(50,10-50,25) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/system_conf.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_monitor.v(51,10-51,26) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_include.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(88,12-88,67) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_monitor_ram.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_monitor_ram.v(51,10-51,25) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/system_conf.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_include_all.v(105,12-105,61) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_trace.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_trace.v(52,10-52,26) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/../components/lm32_top/rtl/verilog/lm32_include.v #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_trace.v(53,10-53,25) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/system_conf.v #c:/work/project/artekit/mico32_ver0/platform/soc/platform.v(328,10-328,49) -- (VERI-1328) analyzing included file C:/work/project/artekit/mico32_ver0/platform/soc/../components/gpio/rtl/verilog/gpio.v #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(76,10-76,25) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/system_conf.v #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(205,6-212,11) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(215,9-222,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(226,9-233,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(237,9-244,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(250,6-257,11) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(260,9-267,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(271,9-278,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(282,9-289,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(301,6-308,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(311,9-318,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(322,9-329,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(333,9-340,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(343,6-350,11) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(353,9-360,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(364,9-371,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(375,9-382,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(388,6-395,11) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(398,9-405,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(409,9-416,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(420,9-427,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(430,6-437,11) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(440,9-447,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(451,9-458,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(462,9-469,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1021,6-1028,11) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1031,9-1038,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1042,9-1049,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1053,9-1060,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1064,6-1071,11) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1074,9-1081,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1085,9-1092,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1096,9-1103,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1110,6-1117,11) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1120,9-1127,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1131,9-1138,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1142,9-1149,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1153,6-1160,11) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1163,9-1170,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1174,9-1181,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1185,9-1192,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1213,6-1222,11) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1225,9-1234,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1238,9-1247,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1251,9-1260,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1268,6-1277,11) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1280,9-1289,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1293,9-1302,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1306,9-1315,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1337,13-1357,18) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1361,16-1381,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1386,16-1406,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1411,16-1431,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1438,13-1458,18) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1462,16-1482,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1487,16-1507,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1512,16-1532,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1549,6-1558,11) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1561,9-1570,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1574,9-1583,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1587,9-1596,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1604,6-1613,11) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1616,9-1625,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1629,9-1638,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1642,9-1651,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1673,6-1693,11) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1696,9-1716,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1720,9-1740,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1744,9-1764,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1771,6-1791,11) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1794,9-1814,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1818,9-1838,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(1842,9-1862,7) WARNING: (VERI-1212) block identifier is required on this block #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(173,4-173,23) WARNING: (VERI-1199) parameter declaration becomes local in gpio with formal parameter declaration list #c:/work/project/artekit/mico32_ver0/platform/soc/platform.v(329,10-329,49) -- (VERI-1328) analyzing included file C:/work/project/artekit/mico32_ver0/platform/soc/../components/gpio/rtl/verilog/tpio.v #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/tpio.v(62,10-62,25) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/system_conf.v #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/tpio.v(84,4-84,23) WARNING: (VERI-1199) parameter declaration becomes local in TRI_PIO with formal parameter declaration list #c:/work/project/artekit/mico32_ver0/platform/soc/platform.v(330,10-330,63) -- (VERI-1328) analyzing included file C:/work/project/artekit/mico32_ver0/platform/soc/../components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v #c:/work/project/artekit/mico32_ver0/platform/components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(82,11-82,26) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/system_conf.v #c:/work/project/artekit/mico32_ver0/platform/components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(122,4-122,43) WARNING: (VERI-1199) parameter declaration becomes local in wb_ebr_ctrl with formal parameter declaration list #c:/work/project/artekit/mico32_ver0/platform/components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(123,4-123,23) WARNING: (VERI-1199) parameter declaration becomes local in wb_ebr_ctrl with formal parameter declaration list #c:/work/project/artekit/mico32_ver0/platform/components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(124,4-124,89) WARNING: (VERI-1199) parameter declaration becomes local in wb_ebr_ctrl with formal parameter declaration list #c:/work/project/artekit/mico32_ver0/platform/components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(125,4-125,71) WARNING: (VERI-1199) parameter declaration becomes local in wb_ebr_ctrl with formal parameter declaration list #c:/work/project/artekit/mico32_ver0/platform/components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(126,4-126,32) WARNING: (VERI-1199) parameter declaration becomes local in wb_ebr_ctrl with formal parameter declaration list #c:/work/project/artekit/mico32_ver0/platform/components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(127,4-127,32) WARNING: (VERI-1199) parameter declaration becomes local in wb_ebr_ctrl with formal parameter declaration list #c:/work/project/artekit/mico32_ver0/platform/components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(128,4-128,32) WARNING: (VERI-1199) parameter declaration becomes local in wb_ebr_ctrl with formal parameter declaration list #c:/work/project/artekit/mico32_ver0/platform/components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(129,4-129,32) WARNING: (VERI-1199) parameter declaration becomes local in wb_ebr_ctrl with formal parameter declaration list #c:/work/project/artekit/mico32_ver0/platform/components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(130,4-130,32) WARNING: (VERI-1199) parameter declaration becomes local in wb_ebr_ctrl with formal parameter declaration list #c:/work/project/artekit/mico32_ver0/platform/components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(131,4-131,32) WARNING: (VERI-1199) parameter declaration becomes local in wb_ebr_ctrl with formal parameter declaration list #c:/work/project/artekit/mico32_ver0/platform/soc/platform.v(331,10-331,69) -- (VERI-1328) analyzing included file C:/work/project/artekit/mico32_ver0/platform/soc/../components/slave_passthru/rtl/verilog/slave_passthru.v #c:/work/project/artekit/mico32_ver0/platform/components/slave_passthru/rtl/verilog/slave_passthru.v(51,10-51,25) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/system_conf.v #c:/work/project/artekit/mico32_ver0/platform/soc/platform.v(332,10-332,63) -- (VERI-1328) analyzing included file C:/work/project/artekit/mico32_ver0/platform/soc/../components/slave_passthru/rtl/verilog/passthru.v #c:/work/project/artekit/mico32_ver0/platform/components/slave_passthru/rtl/verilog/passthru.v(51,10-51,25) -- (VERI-1328) analyzing included file C:/work/project/artekit/tftsurfer_demo_v003_versione_EAS_TFTSURFER_demo_OSC_DELL_CLKOP/par_d12/../../mico32_ver0/platform/soc/system_conf.v #-- (VERI-1482) Analyzing Verilog file C:/work/project/artekit/mico32_ver0/platform/soc/platform_PUR.v #c:/work/project/artekit/mico32_ver0/platform/soc/platform_pur.v(46,10-46,25) -- (VERI-1328) analyzing included file C:/work/project/artekit/mico32_ver0/platform/soc/system_conf.v #--Elaborating Design #c:/work/project/artekit/mico32_ver0/platform/soc/pmi_def.v(24,8-24,29) INFO: (VERI-1018) compiling module pmi_distributed_dpram #c:/work/project/artekit/mico32_ver0/platform/soc/pmi_def.v(94,8-94,23) INFO: (VERI-1018) compiling module pmi_ram_dp_true #c:/work/project/artekit/mico32_ver0/platform/soc/pmi_def.v(130,8-130,18) INFO: (VERI-1018) compiling module pmi_ram_dq #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/er1.v(65,8-65,11) INFO: (VERI-1018) compiling module ER1 #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/er1.v(65,1-251,10) INFO: (VERI-9000) elaborating module 'ER1' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/typeb.v(51,1-78,10) INFO: (VERI-9000) elaborating module 'TYPEB' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA' #c:/work/project/artekit/mico32_ver0/top_conmico32vhd.vhd(4,8-4,21) INFO: (VHDL-1067) elaborating top_conMICO32(top_conMICO32_a) #-- (VHDL-1493) Restoring VHDL parse-tree vl.vl_types from c:/lscc/diamond/2.0/cae_library/vhdl_packages/vdbs/vl/vl_types.vdb #c:/work/project/artekit/mico32_ver0/top_conmico32vhd.vhd(184,1-222,6) -- (VHDL-1399) going to verilog side to elaborate module platform_PUR #c:/work/project/artekit/mico32_ver0/platform/soc/platform_pur.v(53,8-53,20) INFO: (VERI-1018) compiling module platform_PUR #-- (VERI-1482) Analyzing Verilog file C:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v #-- (VERI-1489) Resolving module DP8KC #-- (VERI-1489) Resolving module VHI #-- (VERI-1489) Resolving module VLO #-- (VERI-1489) Resolving module BB #-- (VERI-1489) Resolving module GSR #-- (VERI-1489) Resolving module PUR #-- (VERI-1482) Analyzing Verilog file C:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v #c:/work/project/artekit/mico32_ver0/platform/soc/platform_pur.v(53,1-176,10) INFO: (VERI-9000) elaborating module 'platform_PUR' #c:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v(494,1-496,10) INFO: (VERI-9000) elaborating module 'GSR' #c:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v(1032,1-1035,10) INFO: (VERI-9000) elaborating module 'PUR' #c:/work/project/artekit/mico32_ver0/platform/soc/platform.v(335,1-866,10) INFO: (VERI-9000) elaborating module 'platform' #c:/work/project/artekit/mico32_ver0/platform/soc/platform.v(48,1-325,10) INFO: (VERI-9000) elaborating module 'arbiter2_default' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_top.v(58,1-435,10) INFO: (VERI-9000) elaborating module 'lm32_top' #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(77,1-1884,10) INFO: (VERI-9000) elaborating module 'gpio(DATA_WIDTH=32'h4,INPUT_WIDTH=32'h1,OUTPUT_WIDTH=32'h1,EDGE=1,POSE_EDGE_IRQ=1,INPUT_PORTS_ONLY=0,OUTPUT_PORTS_ONLY=1)' #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(77,1-1884,10) INFO: (VERI-9000) elaborating module 'gpio(DATA_WIDTH=32'h8,INPUT_WIDTH=32'h1,OUTPUT_WIDTH=32'h1,EDGE=1,POSE_EDGE_IRQ=1,INPUT_PORTS_ONLY=0,OUTPUT_PORTS_ONLY=1)' #c:/work/project/artekit/mico32_ver0/platform/components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(83,1-483,10) INFO: (VERI-9000) elaborating module 'wb_ebr_ctrl(SIZE=22528,INIT_FILE_NAME="C:/work/project/artekit/mico32_ver0/software/init_mem.mem")' #c:/work/project/artekit/mico32_ver0/platform/components/slave_passthru/rtl/verilog/slave_passthru.v(52,1-136,10) INFO: (VERI-9000) elaborating module 'slave_passthru' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_cpu.v(100,1-2788,10) INFO: (VERI-9000) elaborating module 'lm32_cpu' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_monitor.v(57,1-190,10) INFO: (VERI-9000) elaborating module 'lm32_monitor' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/jtag_cores.v(75,23-154,10) INFO: (VERI-9000) elaborating module 'jtag_cores' #c:/work/project/artekit/mico32_ver0/platform/components/slave_passthru/rtl/verilog/passthru.v(52,1-119,10) INFO: (VERI-9000) elaborating module 'passthru' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_instruction_unit.v(77,1-889,10) INFO: (VERI-9000) elaborating module 'lm32_instruction_unit(associativity=1,sets=512,bytes_per_line=16,base_address=0,limit=0)' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_decoder.v(113,1-603,10) INFO: (VERI-9000) elaborating module 'lm32_decoder' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_load_store_unit.v(69,1-827,10) INFO: (VERI-9000) elaborating module 'lm32_load_store_unit(associativity=1,sets=512,bytes_per_line=16,base_address=0,limit=0)' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_adder.v(56,1-135,10) INFO: (VERI-9000) elaborating module 'lm32_adder' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_logic_op.v(56,1-96,10) INFO: (VERI-9000) elaborating module 'lm32_logic_op' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_multiplier.v(56,1-120,10) INFO: (VERI-9000) elaborating module 'lm32_multiplier' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_mc_arithmetic.v(64,1-309,10) INFO: (VERI-9000) elaborating module 'lm32_mc_arithmetic' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_interrupt.v(56,1-355,10) INFO: (VERI-9000) elaborating module 'lm32_interrupt_default' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_jtag.v(87,1-587,10) INFO: (VERI-9000) elaborating module 'lm32_jtag' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_debug.v(69,1-367,10) INFO: (VERI-9000) elaborating module 'lm32_debug(breakpoints=0,watchpoints=32'b00000000000000000000000000000000)' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_monitor_ram.v(53,1-1986,10) INFO: (VERI-9000) elaborating module 'lm32_monitor_ram_default' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/jtag_cores.v(60,1-69,10) INFO: (VERI-9000) elaborating module 'jtagconn16' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/jtag_lm32.v(51,1-3083,10) INFO: (VERI-9000) elaborating module 'jtag_lm32' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_addsub.v(55,1-114,10) INFO: (VERI-9000) elaborating module 'lm32_addsub' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA' #c:/work/project/artekit/mico32_ver0/platform/soc/platform_pur.v(53,1-176,10) INFO: (VERI-9000) elaborating module 'platform_PUR' #c:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v(494,1-496,10) INFO: (VERI-9000) elaborating module 'GSR' #c:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v(1032,1-1035,10) INFO: (VERI-9000) elaborating module 'PUR' #c:/work/project/artekit/mico32_ver0/platform/soc/platform.v(335,1-866,10) INFO: (VERI-9000) elaborating module 'platform' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_top.v(58,1-435,10) INFO: (VERI-9000) elaborating module 'lm32_top' #c:/work/project/artekit/mico32_ver0/platform/components/slave_passthru/rtl/verilog/slave_passthru.v(52,1-136,10) INFO: (VERI-9000) elaborating module 'slave_passthru' #c:/work/project/artekit/mico32_ver0/platform/soc/platform.v(48,1-325,10) INFO: (VERI-9000) elaborating module 'arbiter2_default' #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(77,1-1884,10) INFO: (VERI-9000) elaborating module 'gpio(DATA_WIDTH=32'h4,INPUT_WIDTH=32'h1,OUTPUT_WIDTH=32'h1,EDGE=1,POSE_EDGE_IRQ=1,INPUT_PORTS_ONLY=0,OUTPUT_PORTS_ONLY=1)' #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(77,1-1884,10) INFO: (VERI-9000) elaborating module 'gpio(DATA_WIDTH=32'h8,INPUT_WIDTH=32'h1,OUTPUT_WIDTH=32'h1,EDGE=1,POSE_EDGE_IRQ=1,INPUT_PORTS_ONLY=0,OUTPUT_PORTS_ONLY=1)' #c:/work/project/artekit/mico32_ver0/platform/components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(83,1-483,10) INFO: (VERI-9000) elaborating module 'wb_ebr_ctrl(SIZE=22528,INIT_FILE_NAME="C:/work/project/artekit/mico32_ver0/software/init_mem.mem")' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_cpu.v(100,1-2788,10) INFO: (VERI-9000) elaborating module 'lm32_cpu' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_monitor.v(57,1-190,10) INFO: (VERI-9000) elaborating module 'lm32_monitor' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/jtag_cores.v(75,23-154,10) INFO: (VERI-9000) elaborating module 'jtag_cores' #c:/work/project/artekit/mico32_ver0/platform/components/slave_passthru/rtl/verilog/passthru.v(52,1-119,10) INFO: (VERI-9000) elaborating module 'passthru' #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/tpio.v(63,1-186,10) INFO: (VERI-9000) elaborating module 'TRI_PIO(DATA_WIDTH=1,IRQ_MODE=0,LEVEL=0,EDGE=1,POSE_EDGE_IRQ=1,NEGE_EDGE_IRQ=0,EITHER_EDGE_IRQ=0)' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_decoder.v(113,1-603,10) INFO: (VERI-9000) elaborating module 'lm32_decoder' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_adder.v(56,1-135,10) INFO: (VERI-9000) elaborating module 'lm32_adder' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_logic_op.v(56,1-96,10) INFO: (VERI-9000) elaborating module 'lm32_logic_op' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_multiplier.v(56,1-120,10) INFO: (VERI-9000) elaborating module 'lm32_multiplier' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_mc_arithmetic.v(64,1-309,10) INFO: (VERI-9000) elaborating module 'lm32_mc_arithmetic' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_jtag.v(87,1-587,10) INFO: (VERI-9000) elaborating module 'lm32_jtag' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/jtag_cores.v(60,1-69,10) INFO: (VERI-9000) elaborating module 'jtagconn16' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/jtag_lm32.v(51,1-3083,10) INFO: (VERI-9000) elaborating module 'jtag_lm32' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_instruction_unit.v(77,1-889,10) INFO: (VERI-9000) elaborating module 'lm32_instruction_unit(associativity=1,sets=512,bytes_per_line=16,base_address=0,limit=0)' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_load_store_unit.v(69,1-827,10) INFO: (VERI-9000) elaborating module 'lm32_load_store_unit(associativity=1,sets=512,bytes_per_line=16,base_address=0,limit=0)' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_interrupt.v(56,1-355,10) INFO: (VERI-9000) elaborating module 'lm32_interrupt_default' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_debug.v(69,1-367,10) INFO: (VERI-9000) elaborating module 'lm32_debug(breakpoints=0,watchpoints=32'b00000000000000000000000000000000)' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_monitor_ram.v(53,1-1986,10) INFO: (VERI-9000) elaborating module 'lm32_monitor_ram_default' #c:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v(82,1-87,10) INFO: (VERI-9000) elaborating module 'BB' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_addsub.v(55,1-114,10) INFO: (VERI-9000) elaborating module 'lm32_addsub' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA' #c:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC(DATA_WIDTH_A=9,DATA_WIDTH_B=9,REGMODE_A="NOREG",REGMODE_B="NOREG",CSDECODE_A="0b000",CSDECODE_B="0b000",WRITEMODE_A="NORMAL",WRITEMODE_B="NORMAL",GSR="ENABLED",RESETMODE="SYNC",ASYNC_RESET_RELEASE="SYNC",INIT_DATA="STATIC",INITVAL_00="0x10CDC008001082A000000CCE400800108320000012CEC008001083A0000000000000000003E00000",INITVAL_01="0x07CBC008001080A0000008CC400800108120000009CCC008001081A000000ACD4008001082200000",INITVAL_02="0x0D0640C05C0B0540A04C090440803C070340602C050240401C030140200C010000006038A003E800",INITVAL_03="0x0200C010003400000878000880020100201002FF34094000900008C0009C00098000800F8740E06C",INITVAL_04="0x00094000900008C100780E06C0D0640C05C0B0540A04C090440803C070340602C050240401C03014",INITVAL_05="0x0E06C0D0640C05C0B0540A04C090440803C070340602C050240401C030140200C010000E88400098",INITVAL_06="0x009F4000003FE00000020A8003FE001FE001FE003FD00000000E8840009800094000900008C0F878",INITVAL_07="0x0281803820049DC00008009DD011DF013E1015E301608009F80000C00808011E7013E9015EB017ED",INI... #c:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC(DATA_WIDTH_A=9,DATA_WIDTH_B=9,REGMODE_A="NOREG",REGMODE_B="NOREG",CSDECODE_A="0b000",CSDECODE_B="0b000",WRITEMODE_A="NORMAL",WRITEMODE_B="NORMAL",GSR="ENABLED",RESETMODE="SYNC",ASYNC_RESET_RELEASE="SYNC",INIT_DATA="STATIC",INITVAL_00="0x00000100043000000000000001000420000000000000010004300000000000000000000000000000",INITVAL_01="0x00000100042000000000000001000420000000000000010004200000000000000100042000000000",INITVAL_02="0x10000301001000030100100003010010000301001000030100100003010010000000833FF8000670",INITVAL_03="0x30100100001F87000080100801008010080100801F88000880008800088000880009802000030100",INITVAL_04="0x20100201002010030080301001000030100100003010010000301001000030100100003010010000",INITVAL_05="0x30100100003010010000301001000030100100003010010000301001000030100100000010020100",INITVAL_06="0x1007F001000FE0800000100800FE0810000100000FE8001000001802010030180301803018020080",INITVAL_07="0x30100100003007F00000101FF101FF101FF101FF100801007F0000010080101FF101FF101FF101FF",INI... #c:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC(DATA_WIDTH_A=9,DATA_WIDTH_B=9,REGMODE_A="NOREG",REGMODE_B="NOREG",CSDECODE_A="0b000",CSDECODE_B="0b000",WRITEMODE_A="NORMAL",WRITEMODE_B="NORMAL",GSR="ENABLED",RESETMODE="SYNC",ASYNC_RESET_RELEASE="SYNC",INIT_DATA="STATIC",INITVAL_00="0x00000210E01CE001D00000000210E01CE001D00000000210E01CE001D00020100201002000001000",INITVAL_01="0x00000210E01CE001D00000000210E01CE001D00000000210E01CE001D00000000210E01CE001D000",INITVAL_02="0x1DCEE1DAED1DAED1D8EC1D8EC1D6EB1D6EB1D4EA1D4EA1D2E91D2E91D0E81D0001D1EF1FF073CEE8",INITVAL_03="0x1C0E01C0E83DEE81D0E81D0E80100801008010083D0E8000E8090E8070E8020E8010EF1DEEF1DCEE",INITVAL_04="0x00EE709EE707EE71CEE71CCE61CCE61CAE51CAE51C8E41C8E41C6E31C6E31C4E21C4E21C2E11C2E1",INITVAL_05="0x1CCE61CCE61CAE51CAE51C8E41C8E41C6E31C6E31C4E21C4E21C2E11C2E11C0E01C0F01CEE701EE7",INITVAL_06="0x1CFE71D070220701D1082107022070010E802078210100F0F81CEE701EE700EE709EE707EE71CEE7",INITVAL_07="0x1C6E31C6E31C5E71D1E71CEFF1C0FF1C0FF1C0FF1C0E01CFE71D1E71CEE01C0FF1C0FF1C0FF1C0FF",INI... #c:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC(DATA_WIDTH_A=9,DATA_WIDTH_B=9,REGMODE_A="NOREG",REGMODE_B="NOREG",CSDECODE_A="0b000",CSDECODE_B="0b000",WRITEMODE_A="NORMAL",WRITEMODE_B="NORMAL",GSR="ENABLED",RESETMODE="SYNC",ASYNC_RESET_RELEASE="SYNC",INIT_DATA="STATIC",INITVAL_00="0x0381F00C170161F02E130381F00C170161F02E130381F00C170161F02E1300C0600C0600C1F03413",INITVAL_01="0x0381F00C170161F02E130381F00C170161F02E130381F00C170161F02E130381F00C170161F02E13",INITVAL_02="0x0160B0160B0160B0160B0160B0160B0160B0160B0160B0160B0160B0160B01613016060380600C17",INITVAL_03="0x00A0500A1800C170160B00A0B00000000000000400C0B0240B0240B0240B0240B0240B0160B0160B",INITVAL_04="0x03405034050340500A0500A0500A0500A0500A0500A0500A0500A0500A0500A0500A0500A0500A05",INITVAL_05="0x00A0500A0500A0500A0500A0500A0500A0500A0500A0500A0500A0500A0500A0500A1800A0503405",INITVAL_06="0x016060301A016120300801E1A01612008180081A010040241800A050340503405034050340500A05",INITVAL_07="0x0160B0160B016060300600A1F0101F0101F0101F0100B016060300600A0500C1F00C1F00C1F00C1F",INI... #c:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) INFO: (VERI-9000) elaborating module 'VHI' #c:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) INFO: (VERI-9000) elaborating module 'VLO' #c:/work/project/artekit/mico32_ver0/top_conmico32vhd.vhd(184,1-222,6) -- (VHDL-1400) back to vhdl to continue elaboration #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tftsurfer_top.vhd(48,8-48,21) INFO: (VHDL-1067) elaborating tftsurfer_top_default(rtl_tftsurfer_top) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(7259,8-7259,12) INFO: (VHDL-1067) elaborating \osch("10.23")(1,5)\(blackbox) #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pll_block.vhd(14,8-14,17) INFO: (VHDL-1067) elaborating pll_block_default(Structure) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(4864,8-4864,11) INFO: (VHDL-1067) elaborating vlo_default(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(7140,8-7140,15) INFO: (VHDL-1067) elaborating \ehxpllj(1,5,4,4,7,14,"ENABLED","ENABLED","ENABLED","ENABLED","DISABLED","DISABLED","DISABLED","DISABLED",3,5,6,13,0,0,0,0,"CLKOP","DISABLED",0,"RISING",0,"RISING",0,"DISABLED",0,0,0,0,"DIVA","DIVB","DIVC","DIVD",0,"DISABLED","DISABLED","DISABLED","DISABLED","DISABLED","DISABLED","DISABLED")(1,7,1,7,1,7,1,7,1,8,1,8,1,8,1,8,1,5,1,8,1,6,1,6,1,8,1,4,1,4,1,4,1,4,1,8,1,8,1,8,1,8,1,8,1,8,1,8)\(blackbox) #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tft_on_off_button_ctrl.vhd(45,8-45,30) INFO: (VHDL-1067) elaborating tft_on_off_button_ctrl_default(rtl_tft_on_off_button_ctrl) #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/power_manager.vhd(52,8-52,21) INFO: (VHDL-1067) elaborating power_manager_default(rtl_power_manager) #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/tftsurfer_demo.vhd(18,8-18,22) INFO: (VHDL-1067) elaborating tftsurfer_demo_default(rtl_tftsurfer_demo) #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/micro_emulator.vhd(19,8-19,22) INFO: (VHDL-1067) elaborating micro_emulator_default(rtl_micro_emulator) #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/img_mover_viewer.vhd(19,8-19,24) INFO: (VHDL-1067) elaborating img_mover_viewer_default(rtl_img_mover_viewer) #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_imager/img_spi_sector_rom.vhd(14,8-14,26) INFO: (VHDL-1067) elaborating img_spi_sector_rom_default(Structure) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(763,8-763,15) INFO: (VHDL-1067) elaborating \fd1p3dx("ENABLED")(1,7)\(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(4593,8-4593,16) INFO: (VHDL-1067) elaborating \rom16x1a("0000000000000000")\(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(4593,8-4593,16) INFO: (VHDL-1067) elaborating \rom16x1a("0000000011110000")\(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(4593,8-4593,16) INFO: (VHDL-1067) elaborating \rom16x1a("0000000011001100")\(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(4593,8-4593,16) INFO: (VHDL-1067) elaborating \rom16x1a("0000000010101010")\(blackbox) #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/spi_flash_reader.vhd(19,8-19,24) INFO: (VHDL-1067) elaborating spi_flash_reader_default(rtl_spi_flash_reader) #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/pixel_addr_data_fifo.vhd(44,8-44,28) INFO: (VHDL-1067) elaborating pixel_addr_data_fifo_default(rtl_pixel_addr_data_fifo) #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_addr_fifo.vhd(14,8-14,23) INFO: (VHDL-1067) elaborating pixel_addr_fifo_default(Structure) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(142,8-142,12) INFO: (VHDL-1067) elaborating and2_default(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(2328,8-2328,11) INFO: (VHDL-1067) elaborating inv_default(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(4148,8-4148,11) INFO: (VHDL-1067) elaborating or2_default(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(4899,8-4899,12) INFO: (VHDL-1067) elaborating xor2_default(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(4593,8-4593,16) INFO: (VHDL-1067) elaborating \rom16x1a("1000000000000000")\(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(4593,8-4593,16) INFO: (VHDL-1067) elaborating \rom16x1a("0110100110010110")\(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(4593,8-4593,16) INFO: (VHDL-1067) elaborating \rom16x1a("0000010000010000")\(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(4593,8-4593,16) INFO: (VHDL-1067) elaborating \rom16x1a("0001000000000100")\(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(4593,8-4593,16) INFO: (VHDL-1067) elaborating \rom16x1a("0000000101000000")\(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(4593,8-4593,16) INFO: (VHDL-1067) elaborating \rom16x1a("0100000000000001")\(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(722,8-722,15) INFO: (VHDL-1067) elaborating \fd1p3bx("ENABLED")(1,7)\(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(1237,8-1237,15) INFO: (VHDL-1067) elaborating \fd1s3dx("ENABLED")(1,7)\(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(1197,8-1197,15) INFO: (VHDL-1067) elaborating \fd1s3bx("ENABLED")(1,7)\(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(563,8-563,14) INFO: (VHDL-1067) elaborating fadd2b_default(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(525,8-525,11) INFO: (VHDL-1067) elaborating cu2_default(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(4829,8-4829,11) INFO: (VHDL-1067) elaborating vhi_default(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(28,8-28,13) INFO: (VHDL-1067) elaborating ageb2_default(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(5490,8-5490,16) INFO: (VHDL-1067) elaborating \dpr16x4c("0x0000000000000000")(1,18)\(blackbox) #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_data_fifo.vhd(14,8-14,23) INFO: (VHDL-1067) elaborating pixel_data_fifo_default(Structure) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(1945,8-1945,14) INFO: (VHDL-1067) elaborating fsub2b_default(blackbox) #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/monster_manager.vhd(48,8-48,23) INFO: (VHDL-1067) elaborating monster_manager_default(rtl_monster_manager) #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_d12/wb_add_fifo.vhd(14,8-14,19) INFO: (VHDL-1067) elaborating wb_add_fifo_default(Structure) #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/par_d12/wb_data_fifo.vhd(14,8-14,20) INFO: (VHDL-1067) elaborating wb_data_fifo_default(Structure) #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/wb_interface.vhd(6,8-6,20) INFO: (VHDL-1067) elaborating wb_interface_default(rtl_wb_interface) #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/sdram_ctrl.vhd(24,8-24,18) INFO: (VHDL-1067) elaborating sdram_ctrl_default(rtl_sdram_ctrl) #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tft_pixel_rgb_pipeliner.vhd(44,8-44,31) INFO: (VHDL-1067) elaborating tft_pixel_rgb_pipeliner_default(rtl_tft_pixel_rgb_pipeliner) #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/ipexpress/pixel_rgb_fifo.vhd(14,8-14,22) INFO: (VHDL-1067) elaborating pixel_rgb_fifo_default(Structure) #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src/tft_timing_ctrl.vhd(75,8-75,23) INFO: (VHDL-1067) elaborating tft_timing_ctrl_default(rtl_tft_timing_ctrl) #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src_spi/spi_top.vhd(6,8-6,15) INFO: (VHDL-1067) elaborating SPI_top_default(rtl_SPI_top) #c:/work/project/artekit/tftsurfer_demo_v003_versione_eas_tftsurfer_demo_osc_dell_clkop/src_spi/memoria.vhd(14,8-14,15) INFO: (VHDL-1067) elaborating memoria_default(Structure) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(5490,8-5490,16) INFO: (VHDL-1067) elaborating \dpr16x4c("0xA9876543210FEA51")(1,18)\(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(5490,8-5490,16) INFO: (VHDL-1067) elaborating \dpr16x4c("0xB9876543210FEB62")(1,18)\(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(5490,8-5490,16) INFO: (VHDL-1067) elaborating \dpr16x4c("0xA9876543210FEC73")(1,18)\(blackbox) #c:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg(5490,8-5490,16) INFO: (VHDL-1067) elaborating \dpr16x4c("0xB9876543210FED84")(1,18)\(blackbox) #c:/work/project/artekit/mico32_ver0/platform/soc/platform_pur.v(53,1-176,10) INFO: (VERI-9000) elaborating module 'platform_PUR' #c:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v(494,1-496,10) INFO: (VERI-9000) elaborating module 'GSR' #c:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v(1032,1-1035,10) INFO: (VERI-9000) elaborating module 'PUR' #c:/work/project/artekit/mico32_ver0/platform/soc/platform.v(335,1-866,10) INFO: (VERI-9000) elaborating module 'platform' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_top.v(58,1-435,10) INFO: (VERI-9000) elaborating module 'lm32_top' #c:/work/project/artekit/mico32_ver0/platform/components/slave_passthru/rtl/verilog/slave_passthru.v(52,1-136,10) INFO: (VERI-9000) elaborating module 'slave_passthru' #c:/work/project/artekit/mico32_ver0/platform/soc/platform.v(48,1-325,10) INFO: (VERI-9000) elaborating module 'arbiter2_default' #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(77,1-1884,10) INFO: (VERI-9000) elaborating module 'gpio(DATA_WIDTH=32'h4,INPUT_WIDTH=32'h1,OUTPUT_WIDTH=32'h1,EDGE=1,POSE_EDGE_IRQ=1,INPUT_PORTS_ONLY=0,OUTPUT_PORTS_ONLY=1)' #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/gpio.v(77,1-1884,10) INFO: (VERI-9000) elaborating module 'gpio(DATA_WIDTH=32'h8,INPUT_WIDTH=32'h1,OUTPUT_WIDTH=32'h1,EDGE=1,POSE_EDGE_IRQ=1,INPUT_PORTS_ONLY=0,OUTPUT_PORTS_ONLY=1)' #c:/work/project/artekit/mico32_ver0/platform/components/wb_ebr_ctrl/rtl/verilog/wb_ebr_ctrl.v(83,1-483,10) INFO: (VERI-9000) elaborating module 'wb_ebr_ctrl(SIZE=22528,INIT_FILE_NAME="C:/work/project/artekit/mico32_ver0/software/init_mem.mem")' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_cpu.v(100,1-2788,10) INFO: (VERI-9000) elaborating module 'lm32_cpu' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_monitor.v(57,1-190,10) INFO: (VERI-9000) elaborating module 'lm32_monitor' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/jtag_cores.v(75,23-154,10) INFO: (VERI-9000) elaborating module 'jtag_cores' #c:/work/project/artekit/mico32_ver0/platform/components/slave_passthru/rtl/verilog/passthru.v(52,1-119,10) INFO: (VERI-9000) elaborating module 'passthru' #c:/work/project/artekit/mico32_ver0/platform/components/gpio/rtl/verilog/tpio.v(63,1-186,10) INFO: (VERI-9000) elaborating module 'TRI_PIO(DATA_WIDTH=1,IRQ_MODE=0,LEVEL=0,EDGE=1,POSE_EDGE_IRQ=1,NEGE_EDGE_IRQ=0,EITHER_EDGE_IRQ=0)' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_decoder.v(113,1-603,10) INFO: (VERI-9000) elaborating module 'lm32_decoder' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_adder.v(56,1-135,10) INFO: (VERI-9000) elaborating module 'lm32_adder' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_logic_op.v(56,1-96,10) INFO: (VERI-9000) elaborating module 'lm32_logic_op' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_multiplier.v(56,1-120,10) INFO: (VERI-9000) elaborating module 'lm32_multiplier' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_mc_arithmetic.v(64,1-309,10) INFO: (VERI-9000) elaborating module 'lm32_mc_arithmetic' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_jtag.v(87,1-587,10) INFO: (VERI-9000) elaborating module 'lm32_jtag' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/jtag_cores.v(60,1-69,10) INFO: (VERI-9000) elaborating module 'jtagconn16' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/jtag_lm32.v(51,1-3083,10) INFO: (VERI-9000) elaborating module 'jtag_lm32' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_instruction_unit.v(77,1-889,10) INFO: (VERI-9000) elaborating module 'lm32_instruction_unit(associativity=1,sets=512,bytes_per_line=16,base_address=0,limit=0)' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_load_store_unit.v(69,1-827,10) INFO: (VERI-9000) elaborating module 'lm32_load_store_unit(associativity=1,sets=512,bytes_per_line=16,base_address=0,limit=0)' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_interrupt.v(56,1-355,10) INFO: (VERI-9000) elaborating module 'lm32_interrupt_default' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_debug.v(69,1-367,10) INFO: (VERI-9000) elaborating module 'lm32_debug(breakpoints=0,watchpoints=32'b00000000000000000000000000000000)' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_monitor_ram.v(53,1-1986,10) INFO: (VERI-9000) elaborating module 'lm32_monitor_ram_default' #c:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v(82,1-87,10) INFO: (VERI-9000) elaborating module 'BB' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_addsub.v(55,1-114,10) INFO: (VERI-9000) elaborating module 'lm32_addsub' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/typea.v(65,1-102,10) INFO: (VERI-9000) elaborating module 'TYPEA' #c:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v(1120,1-1122,10) INFO: (VERI-9000) elaborating module 'VHI' #c:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v(1124,1-1126,10) INFO: (VERI-9000) elaborating module 'VLO' #c:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC(DATA_WIDTH_A=9,DATA_WIDTH_B=9,REGMODE_A="NOREG",REGMODE_B="NOREG",CSDECODE_A="0b000",CSDECODE_B="0b000",WRITEMODE_A="NORMAL",WRITEMODE_B="NORMAL",GSR="ENABLED",RESETMODE="SYNC",ASYNC_RESET_RELEASE="SYNC",INIT_DATA="STATIC",INITVAL_00="0x10CDC008001082A000000CCE400800108320000012CEC008001083A0000000000000000003E00000",INITVAL_01="0x07CBC008001080A0000008CC400800108120000009CCC008001081A000000ACD4008001082200000",INITVAL_02="0x0D0640C05C0B0540A04C090440803C070340602C050240401C030140200C010000006038A003E800",INITVAL_03="0x0200C010003400000878000880020100201002FF34094000900008C0009C00098000800F8740E06C",INITVAL_04="0x00094000900008C100780E06C0D0640C05C0B0540A04C090440803C070340602C050240401C03014",INITVAL_05="0x0E06C0D0640C05C0B0540A04C090440803C070340602C050240401C030140200C010000E88400098",INITVAL_06="0x009F4000003FE00000020A8003FE001FE001FE003FD00000000E8840009800094000900008C0F878",INITVAL_07="0x0281803820049DC00008009DD011DF013E1015E301608009F80000C00808011E7013E9015EB017ED",INI... #c:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC(DATA_WIDTH_A=9,DATA_WIDTH_B=9,REGMODE_A="NOREG",REGMODE_B="NOREG",CSDECODE_A="0b000",CSDECODE_B="0b000",WRITEMODE_A="NORMAL",WRITEMODE_B="NORMAL",GSR="ENABLED",RESETMODE="SYNC",ASYNC_RESET_RELEASE="SYNC",INIT_DATA="STATIC",INITVAL_00="0x00000100043000000000000001000420000000000000010004300000000000000000000000000000",INITVAL_01="0x00000100042000000000000001000420000000000000010004200000000000000100042000000000",INITVAL_02="0x10000301001000030100100003010010000301001000030100100003010010000000833FF8000670",INITVAL_03="0x30100100001F87000080100801008010080100801F88000880008800088000880009802000030100",INITVAL_04="0x20100201002010030080301001000030100100003010010000301001000030100100003010010000",INITVAL_05="0x30100100003010010000301001000030100100003010010000301001000030100100000010020100",INITVAL_06="0x1007F001000FE0800000100800FE0810000100000FE8001000001802010030180301803018020080",INITVAL_07="0x30100100003007F00000101FF101FF101FF101FF100801007F0000010080101FF101FF101FF101FF",INI... #c:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC(DATA_WIDTH_A=9,DATA_WIDTH_B=9,REGMODE_A="NOREG",REGMODE_B="NOREG",CSDECODE_A="0b000",CSDECODE_B="0b000",WRITEMODE_A="NORMAL",WRITEMODE_B="NORMAL",GSR="ENABLED",RESETMODE="SYNC",ASYNC_RESET_RELEASE="SYNC",INIT_DATA="STATIC",INITVAL_00="0x00000210E01CE001D00000000210E01CE001D00000000210E01CE001D00020100201002000001000",INITVAL_01="0x00000210E01CE001D00000000210E01CE001D00000000210E01CE001D00000000210E01CE001D000",INITVAL_02="0x1DCEE1DAED1DAED1D8EC1D8EC1D6EB1D6EB1D4EA1D4EA1D2E91D2E91D0E81D0001D1EF1FF073CEE8",INITVAL_03="0x1C0E01C0E83DEE81D0E81D0E80100801008010083D0E8000E8090E8070E8020E8010EF1DEEF1DCEE",INITVAL_04="0x00EE709EE707EE71CEE71CCE61CCE61CAE51CAE51C8E41C8E41C6E31C6E31C4E21C4E21C2E11C2E1",INITVAL_05="0x1CCE61CCE61CAE51CAE51C8E41C8E41C6E31C6E31C4E21C4E21C2E11C2E11C0E01C0F01CEE701EE7",INITVAL_06="0x1CFE71D070220701D1082107022070010E802078210100F0F81CEE701EE700EE709EE707EE71CEE7",INITVAL_07="0x1C6E31C6E31C5E71D1E71CEFF1C0FF1C0FF1C0FF1C0E01CFE71D1E71CEE01C0FF1C0FF1C0FF1C0FF",INI... #c:/lscc/diamond/2.0/cae_library/synthesis/verilog/machxo2.v(1291,1-1358,10) INFO: (VERI-9000) elaborating module 'DP8KC(DATA_WIDTH_A=9,DATA_WIDTH_B=9,REGMODE_A="NOREG",REGMODE_B="NOREG",CSDECODE_A="0b000",CSDECODE_B="0b000",WRITEMODE_A="NORMAL",WRITEMODE_B="NORMAL",GSR="ENABLED",RESETMODE="SYNC",ASYNC_RESET_RELEASE="SYNC",INIT_DATA="STATIC",INITVAL_00="0x0381F00C170161F02E130381F00C170161F02E130381F00C170161F02E1300C0600C0600C1F03413",INITVAL_01="0x0381F00C170161F02E130381F00C170161F02E130381F00C170161F02E130381F00C170161F02E13",INITVAL_02="0x0160B0160B0160B0160B0160B0160B0160B0160B0160B0160B0160B0160B01613016060380600C17",INITVAL_03="0x00A0500A1800C170160B00A0B00000000000000400C0B0240B0240B0240B0240B0240B0160B0160B",INITVAL_04="0x03405034050340500A0500A0500A0500A0500A0500A0500A0500A0500A0500A0500A0500A0500A05",INITVAL_05="0x00A0500A0500A0500A0500A0500A0500A0500A0500A0500A0500A0500A0500A0500A1800A0503405",INITVAL_06="0x016060301A016120300801E1A01612008180081A010040241800A050340503405034050340500A05",INITVAL_07="0x0160B0160B016060300600A1F0101F0101F0101F0100B016060300600A0500C1F00C1F00C1F00C1F",INI... #c:/work/project/artekit/mico32_ver0/platform/soc/platform.v(643,1-676,35) -- (VERI-1453) port PIO_IN is not connected to this instance #c:/work/project/artekit/mico32_ver0/platform/soc/platform.v(755,1-788,35) -- (VERI-1453) port PIO_IN is not connected to this instance #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/jtag_lm32.v(80,20) WARNING: (ST-5001) Inferring scalar net 'clk_enable' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/jtag_lm32.v(85,20) WARNING: (ST-5001) Inferring scalar net 'captureDr' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_cpu.v(1002,30) WARNING: (ST-5001) Inferring scalar net 'load_q_m' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_cpu.v(1003,30) WARNING: (ST-5001) Inferring scalar net 'store_q_m' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_cpu.v(1247,30) WARNING: (ST-5001) Inferring scalar net 'bp_match' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_cpu.v(1248,30) WARNING: (ST-5001) Inferring scalar net 'wp_match' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_monitor_ram.v(125,73) WARNING: (ST-5001) Inferring scalar net 'scuba_vlo' #c:/work/project/artekit/mico32_ver0/platform/components/lm32_top/rtl/verilog/lm32_monitor_ram.v(128,71) WARNING: (ST-5001) Inferring scalar net 'scuba_vhi' #-- (ST-1001) Root modules/entities/cells (2): #-- ER1 #-- top_conmico32 #Design load finished with (0) errors, and (108) warnings.