Synthesis and Ngdbuild  Report
#Build: Synplify Pro E-2010.09L-SP2, Build 081R, Feb 16 2011
#install: C:\lscc\diamond\1.2\synpbase
#OS: Windows_NT

#Hostname: LMOBILE06

$ Start of Compile
#Sun Sep 18 14:48:34 2011

Synopsys VHDL Compiler, version comp520rcp2, Build 118R, built Feb 11 2011
@N|Running in 32-bit mode
Copyright (C) 1994-2011 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

@N: CD720 :"C:\lscc\diamond\1.2\synpbase\lib\vhd\std.vhd":123:18:123:21|Setting time resolution to ns
@N:"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\tftsurfer_demo.vhd":18:7:18:20|Top entity is set to tftsurfer_demo.
VHDL syntax check successful!
Options changed - recompiling
@N: CD630 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\tftsurfer_demo.vhd":18:7:18:20|Synthesizing work.tftsurfer_demo.rtl_tftsurfer_demo 
@N: CD630 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\spi_flash_reader.vhd":19:7:19:22|Synthesizing work.spi_flash_reader.rtl_spi_flash_reader 
@N: CD231 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\spi_flash_reader.vhd":41:21:41:22|Using onehot encoding for type spi_rd_state (idle="10000")
@W: CD604 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\spi_flash_reader.vhd":212:12:212:25|OTHERS clause is not synthesized 
Post processing for work.spi_flash_reader.rtl_spi_flash_reader
@N: CL177 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\spi_flash_reader.vhd":162:6:162:7|Sharing sequential element rst_d_cnt.
@W: CL190 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Optimizing register bit spi_d_sr(0) to a constant 0
@W: CL260 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Pruning Register bit 0 of spi_d_sr(31 downto 0)  
@N: CD630 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\par_imager\..\img_mover_viewer.vhd":19:7:19:22|Synthesizing work.img_mover_viewer.rtl_img_mover_viewer 
@N: CD231 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\par_imager\..\img_mover_viewer.vhd":61:24:61:25|Using onehot encoding for type move_view_state (idle="100000000000")
@W: CD604 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\par_imager\..\img_mover_viewer.vhd":194:4:194:17|OTHERS clause is not synthesized 
@N: CD630 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\par_imager\img_spi_sector_rom.vhd":14:7:14:24|Synthesizing work.img_spi_sector_rom.structure 
@N: CD630 :"C:\lscc\diamond\1.2\cae_library\synthesis\vhdl\machxo2.vhd":233:10:233:16|Synthesizing work.fd1p3dx.syn_black_box 
Post processing for work.fd1p3dx.syn_black_box
@N: CD630 :"C:\lscc\diamond\1.2\cae_library\synthesis\vhdl\machxo2.vhd":1406:10:1406:17|Synthesizing work.rom16x1a.syn_black_box 
Post processing for work.rom16x1a.syn_black_box
@N: CD630 :"C:\lscc\diamond\1.2\cae_library\synthesis\vhdl\machxo2.vhd":1488:10:1488:12|Synthesizing work.vlo.syn_black_box 
Post processing for work.vlo.syn_black_box
Post processing for work.img_spi_sector_rom.structure
Post processing for work.img_mover_viewer.rtl_img_mover_viewer
@W: CL190 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\par_imager\..\img_mover_viewer.vhd":123:6:123:7|Optimizing register bit tft_sect(0) to a constant 0
@W: CL190 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\par_imager\..\img_mover_viewer.vhd":123:6:123:7|Optimizing register bit tft_sect(1) to a constant 0
@W: CL190 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\par_imager\..\img_mover_viewer.vhd":123:6:123:7|Optimizing register bit tft_sect(2) to a constant 0
@W: CL169 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\par_imager\..\img_mover_viewer.vhd":123:6:123:7|Pruning Register tft_sect(2 downto 0)  
@N: CD630 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\micro_emulator.vhd":19:7:19:20|Synthesizing work.micro_emulator.rtl_micro_emulator 
@N: CD231 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\micro_emulator.vhd":38:23:38:24|Using onehot encoding for type demo_fsm_state (idle="1000000")
@W: CD604 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\micro_emulator.vhd":133:12:133:25|OTHERS clause is not synthesized 
Post processing for work.micro_emulator.rtl_micro_emulator
Post processing for work.tftsurfer_demo.rtl_tftsurfer_demo
@N: CL201 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\micro_emulator.vhd":81:6:81:7|Trying to extract state machine for register demo_fsm_st
Extracted state machine for register demo_fsm_st
State machine has 7 reachable states with original encodings of:
   0000001
   0000010
   0000100
   0001000
   0010000
   0100000
   1000000
@N: CL201 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\par_imager\..\img_mover_viewer.vhd":123:6:123:7|Trying to extract state machine for register move_view_st
Extracted state machine for register move_view_st
State machine has 12 reachable states with original encodings of:
   000000000001
   000000000010
   000000000100
   000000001000
   000000010000
   000000100000
   000001000000
   000010000000
   000100000000
   001000000000
   010000000000
   100000000000
@W: CL246 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\par_imager\..\img_mover_viewer.vhd":27:6:27:11|Input port bits 3 to 2 of img_nr(3 downto 0) are unused 
@W: CL246 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\par_imager\..\img_mover_viewer.vhd":41:6:41:13|Input port bits 1 to 0 of spi_byte(7 downto 0) are unused 
@N: CL135 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\spi_flash_reader.vhd":230:6:230:7|Found seqShift spi_end_rd, depth=4, width=1
@W: CL190 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Optimizing register bit spi_d_sr(1) to a constant 0
@W: CL260 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Pruning Register bit 1 of spi_d_sr(31 downto 1)  
@W: CL190 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Optimizing register bit spi_d_sr(2) to a constant 0
@W: CL260 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Pruning Register bit 2 of spi_d_sr(31 downto 2)  
@W: CL190 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Optimizing register bit spi_d_sr(3) to a constant 0
@W: CL260 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Pruning Register bit 3 of spi_d_sr(31 downto 3)  
@W: CL190 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Optimizing register bit spi_d_sr(4) to a constant 0
@W: CL260 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Pruning Register bit 4 of spi_d_sr(31 downto 4)  
@N: CL201 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\spi_flash_reader.vhd":162:6:162:7|Trying to extract state machine for register spi_rd_st
Extracted state machine for register spi_rd_st
State machine has 5 reachable states with original encodings of:
   00001
   00010
   00100
   01000
   10000
@W: CL190 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Optimizing register bit spi_d_sr(5) to a constant 0
@W: CL260 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Pruning Register bit 5 of spi_d_sr(31 downto 5)  
@W: CL190 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Optimizing register bit spi_d_sr(6) to a constant 0
@W: CL260 :"C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Pruning Register bit 6 of spi_d_sr(31 downto 6)  
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Sep 18 14:48:35 2011

###########################################################]
Synopsys Lattice Technology Constraint Extraction, Version maplat, Build 064R, Built Feb 17 2011 10:52:05
Copyright (C) 1994-2011, Synopsys Inc.  All Rights Reserved
Product Version E-2010.09L-SP2
@N: MF249 |Running in 32-bit mode.
@N: MF257 |Gated clock conversion enabled 
Finished Timing Extraction Phase. (Time elapsed 0h:00m:00s; Memory used current: 75MB peak: 78MB)

Timing Extraction successful!
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Sep 18 14:48:36 2011

###########################################################]
Synopsys Lattice Technology Mapper, Version maplat, Build 064R, Built Feb 17 2011 10:52:05
Copyright (C) 1994-2011, Synopsys Inc.  All Rights Reserved
Product Version E-2010.09L-SP2
@N: MF249 |Running in 32-bit mode.
@N: MF257 |Gated clock conversion enabled 
@N: MF203 |Set autoconstraint_io 


Available hyper_sources - for debug and ip models
	None Found

Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 78MB)

Encoding state machine work.micro_emulator(rtl_micro_emulator)-demo_fsm_st[0:6]
original code -> new code
   0000001 -> 0000001
   0000010 -> 0000010
   0000100 -> 0000100
   0001000 -> 0001000
   0010000 -> 0010000
   0100000 -> 0100000
   1000000 -> 1000000
@N:"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\micro_emulator.vhd":81:6:81:7|Found counter in view:work.micro_emulator(rtl_micro_emulator) inst img_nr_cnt[3:0]
@W: BN132 :"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\micro_emulator.vhd":81:6:81:7|Removing sequential instance MICRO_EMULATOR_INST.img_view,  because it is equivalent to instance MICRO_EMULATOR_INST.demo_fsm_st[5]
@W: BN132 :"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\micro_emulator.vhd":81:6:81:7|Removing sequential instance MICRO_EMULATOR_INST.img_start_move,  because it is equivalent to instance MICRO_EMULATOR_INST.demo_fsm_st[2]
Encoding state machine work.img_mover_viewer(rtl_img_mover_viewer)-move_view_st[0:11]
original code -> new code
   000000000001 -> 000000000001
   000000000010 -> 000000000010
   000000000100 -> 000000000100
   000000001000 -> 000000001000
   000000010000 -> 000000010000
   000000100000 -> 000000100000
   000001000000 -> 000001000000
   000010000000 -> 000010000000
   000100000000 -> 000100000000
   001000000000 -> 001000000000
   010000000000 -> 010000000000
   100000000000 -> 100000000000
@N:"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\par_imager\..\img_mover_viewer.vhd":123:6:123:7|Found counter in view:work.img_mover_viewer(rtl_img_mover_viewer) inst pixel_addr[21:0]
@W: BN132 :"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\par_imager\..\img_mover_viewer.vhd":123:6:123:7|Removing sequential instance IMG_MOVER_VIEWER_INST.addr_data_wr,  because it is equivalent to instance IMG_MOVER_VIEWER_INST.move_view_st[1]
@W: BN132 :"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\par_imager\..\img_mover_viewer.vhd":212:6:212:7|Removing sequential instance IMG_MOVER_VIEWER_INST.addr_data_wr_reg,  because it is equivalent to instance IMG_MOVER_VIEWER_INST.move_view_st[0]
@W: BN132 :"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\par_imager\..\img_mover_viewer.vhd":123:6:123:7|Removing sequential instance IMG_MOVER_VIEWER_INST.spi_start_rd,  because it is equivalent to instance IMG_MOVER_VIEWER_INST.move_view_st[10]
Encoding state machine work.spi_flash_reader(rtl_spi_flash_reader)-spi_rd_st[0:4]
original code -> new code
   00001 -> 00001
   00010 -> 00010
   00100 -> 00100
   01000 -> 01000
   10000 -> 10000
@N:"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\spi_flash_reader.vhd":148:6:148:7|Found counter in view:work.spi_flash_reader(rtl_spi_flash_reader) inst spi_byte_cnt[20:0]
@N:"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\spi_flash_reader.vhd":120:6:120:7|Found counter in view:work.spi_flash_reader(rtl_spi_flash_reader) inst d_cnt[4:0]
@N: BN116 :"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Removing sequential instance spi_d_sr[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N: BN116 :"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\spi_flash_reader.vhd":230:6:230:7|Removing sequential instance SPI_FLASH_READER_INST.spi_byte[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N: BN116 :"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\spi_flash_reader.vhd":230:6:230:7|Removing sequential instance SPI_FLASH_READER_INST.spi_byte[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N: BN116 :"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Removing sequential instance SPI_FLASH_READER_INST.spi_d_sr[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N: BN116 :"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\spi_flash_reader.vhd":162:6:162:7|Removing sequential instance SPI_FLASH_READER_INST.rgb_byte[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N: BN116 :"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\spi_flash_reader.vhd":162:6:162:7|Removing sequential instance SPI_FLASH_READER_INST.rgb_byte[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N: BN116 :"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\micro_emulator.vhd":81:6:81:7|Removing sequential instance MICRO_EMULATOR_INST.demo_sel of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 78MB)

@N: BN116 :"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Removing sequential instance SPI_FLASH_READER_INST.spi_d_sr[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N: BN116 :"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Removing sequential instance SPI_FLASH_READER_INST.spi_d_sr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 


#################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[

======================================================================================
                                Instance:Pin        Generated Clock Optimization Status
======================================================================================
       SPI_FLASH_READER_INST.rgb_byte_en:C              Not Done


##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################]

Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 78MB)


@N: BN116 :"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Removing sequential instance SPI_FLASH_READER_INST.spi_d_sr[11] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 78MB)

Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 78MB)

Finished Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 78MB)

Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 78MB)

@N: BN116 :"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Removing sequential instance SPI_FLASH_READER_INST.spi_d_sr[12] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N: BN116 :"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Removing sequential instance SPI_FLASH_READER_INST.spi_d_sr[13] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N: BN116 :"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Removing sequential instance SPI_FLASH_READER_INST.spi_d_sr[14] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
@N: BN116 :"c:\work\lscc\tftsurfer\vhdl\tftsurfer_demo_v001\spi_flash_reader.vhd":79:6:79:7|Removing sequential instance SPI_FLASH_READER_INST.spi_d_sr[15] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs 
Finished preparing to map (Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 78MB)

Finished technology mapping (Time elapsed 0h:00m:00s; Memory used current: 76MB peak: 78MB)

Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
Pass		 CPU time		Worst Slack		Luts / Registers
------------------------------------------------------------
------------------------------------------------------------

Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 78MB)

@N: FX164 |The option to pack flops in the IOB has not been specified 
---------------------------------------
Resource Usage Report
Part: lcmxo2_1200hc-6

Register bits: 196 of 1280 (15%)
PIC Latch:       0
I/O cells:       52


Details:
CCU2D:          26
FD1P3AX:        21
FD1P3DX:        82
FD1S3AX:        5
FD1S3BX:        5
FD1S3DX:        37
FD1S3IX:        3
GSR:            1
IB:             4
IFS1P3DX:       2
INV:            4
OB:             48
OFS1P3BX:       1
OFS1P3DX:       40
ORCALUT4:       74
PUR:            1
ROM16X1A:       8
VHI:            1
VLO:            1
Finished restoring hierarchy (Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 78MB)

Writing Analyst data base C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v001\par_imager\image\image_image.srm
Finished Writing Netlist Databases (Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 78MB)

Writing EDIF Netlist and constraint files
E-2010.09L-SP2
Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:01s; Memory used current: 80MB peak: 81MB)

Writing Verilog Simulation files
Finished Writing Verilog Simulation files (Time elapsed 0h:00m:01s; Memory used current: 80MB peak: 81MB)

Writing VHDL Simulation files
Finished Writing VHDL Simulation files (Time elapsed 0h:00m:01s; Memory used current: 81MB peak: 82MB)

Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:01s; Memory used current: 81MB peak: 82MB)

@N: MF276 |Gated clock conversion enabled, but no gated clocks found in design 
Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:01s; Memory used current: 81MB peak: 82MB)

Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:01s; Memory used current: 81MB peak: 82MB)

@N: MF333 |Generated clock conversion enabled, but no generated clocks found in design 
Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:01s; Memory used current: 81MB peak: 82MB)

@W: MT420 |Found inferred clock tftsurfer_demo|tft_clk with period 1000.00ns. A user-defined clock should be declared on object "p:tft_clk"



##### START OF TIMING REPORT #####[
# Timing Report written on Sun Sep 18 14:48:38 2011
#


Top view:               tftsurfer_demo
Requested Frequency:    1.0 MHz
Wire load mode:         top
Paths requested:        3
Constraint File(s):    
@N: MT320 |This timing report estimates place and route data. Please look at the place and route timing report for final timing..


Performance Summary 
*******************


Worst slack in design: 493.800

                           Requested     Estimated     Requested     Estimated                 Clock        Clock              
Starting Clock             Frequency     Frequency     Period        Period        Slack       Type         Group              
-------------------------------------------------------------------------------------------------------------------------------
tftsurfer_demo|tft_clk     1.0 MHz       80.6 MHz      1000.000      12.400        493.800     inferred     Inferred_clkgroup_0
System                     1.0 MHz       135.2 MHz     1000.000      7.398         992.602     system       system_clkgroup    
===============================================================================================================================





Clock Relationships
*******************

Clocks                                          |    rise  to  rise     |    fall  to  fall     |    rise  to  fall     |    fall  to  rise   
----------------------------------------------------------------------------------------------------------------------------------------------
Starting                Ending                  |  constraint  slack    |  constraint  slack    |  constraint  slack    |  constraint  slack  
----------------------------------------------------------------------------------------------------------------------------------------------
System                  System                  |  1000.000    992.602  |  No paths    -        |  No paths    -        |  No paths    -      
System                  tftsurfer_demo|tft_clk  |  1000.000    997.915  |  No paths    -        |  No paths    -        |  No paths    -      
tftsurfer_demo|tft_clk  System                  |  1000.000    995.008  |  No paths    -        |  No paths    -        |  1000.000    994.055
tftsurfer_demo|tft_clk  tftsurfer_demo|tft_clk  |  1000.000    993.657  |  1000.000    994.329  |  500.000     493.800  |  500.000     498.309
==============================================================================================================================================
 Note: 'No paths' indicates there are no paths in the design for that pair of clock edges.
       'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups.



Interface Information 
*********************



Input Ports: 

Port           Starting            User           Arrival     Required          
Name           Reference           Constraint     Time        Time         Slack
               Clock                                                            
--------------------------------------------------------------------------------
demo_start     System (rising)     NA             0.000       997.915           
spi_q          System (rising)     NA             0.000       997.915           
sys_rst        NA                  NA             NA          NA           NA   
tft_clk        System (rising)     NA             0.000       992.602           
================================================================================


Output Ports: 

Port                Starting                             User           Arrival     Required          
Name                Reference                            Constraint     Time        Time         Slack
                    Clock                                                                             
------------------------------------------------------------------------------------------------------
fifo_wr_add[0]      tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_add[1]      tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_add[2]      tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_add[3]      tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_add[4]      tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_add[5]      tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_add[6]      tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_add[7]      tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_add[8]      tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_add[9]      tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_add[10]     tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_add[11]     tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_add[12]     tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_add[13]     tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_add[14]     tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_add[15]     tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_add[16]     tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_add[17]     tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_add[18]     tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_add[19]     tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_add[20]     tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_add[21]     tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_req         tftsurfer_demo|tft_clk (rising)      NA             4.992       1000.000          
fifo_wr_rgb[0]      tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_rgb[1]      tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_rgb[2]      tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_rgb[3]      tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_rgb[4]      tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_rgb[5]      tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_rgb[6]      tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_rgb[7]      tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_rgb[8]      tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_rgb[9]      tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_rgb[10]     tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_rgb[11]     tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_rgb[12]     tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_rgb[13]     tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_rgb[14]     tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
fifo_wr_rgb[15]     tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
spi_clk             NA                                   NA             NA          NA           NA   
spi_csn             tftsurfer_demo|tft_clk (falling)     NA             4.856       1000.000          
spi_d               tftsurfer_demo|tft_clk (falling)     NA             5.945       1000.000          
test_pt             tftsurfer_demo|tft_clk (rising)      NA             4.928       1000.000          
tft_bank[0]         tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
tft_bank[1]         tftsurfer_demo|tft_clk (rising)      NA             4.856       1000.000          
tft_sect[0]         NA                                   NA             NA          NA           NA   
tft_sect[1]         NA                                   NA             NA          NA           NA   
tft_sect[2]         NA                                   NA             NA          NA           NA   
======================================================================================================


##### END OF TIMING REPORT #####]

Mapper successful!
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Sep 18 14:48:38 2011

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