Map TRACE Report
Loading design for application trce from file tftsurfer_tftsurfer_map.ncd.
Design name: top_conMICO32
NCD version: 3.2
Vendor: LATTICE
Device: LCMXO2-7000HC
Package: TQFP144
Performance: 6
Loading device for application trce from file 'xo2c7000.nph' in environment: C:/lscc/diamond/2.0/ispfpga.
Package Status: Final Version 1.30
Performance Hardware Data Status: Final) Version 22.4
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond Version 2.0.0.154
Thu Jan 31 12:26:02 2013
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2012 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o tftsurfer_tftsurfer.tw1 tftsurfer_tftsurfer_map.ncd tftsurfer_tftsurfer.prf
Design file: tftsurfer_tftsurfer_map.ncd
Preference file: tftsurfer_tftsurfer.prf
Device,speed: LCMXO2-7000HC,6
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "controller_marco.sys_clk_sig_c" 125.000000 MHz (0 errors) 2488 items scored, 0 timing errors detected.
Report: 126.518MHz is the maximum frequency for this preference.
FREQUENCY NET "tft_clk_c_c" 35.714286 MHz (0 errors) 3354 items scored, 0 timing errors detected.
Report: 93.914MHz is the maximum frequency for this preference.
FREQUENCY NET "controller_marco/osch_clk_sig_c" 10.230000 MHz (0 errors) 310 items scored, 0 timing errors detected.
Report: 209.644MHz is the maximum frequency for this preference.
FREQUENCY NET "ext_osc_clk_c" 25.000000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
Report: 71.510MHz is the maximum frequency for this preference.
FREQUENCY PORT "ext_osc_clk" 25.000000 MHz (0 errors) 0 items scored, 0 timing errors detected.
Report: 150.150MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "controller_marco.sys_clk_sig_c" 125.000000 MHz ;
2488 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.096ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/SDRAM_CTRL_INST/init_auto_ref_flag (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco_SDRAM_CTRL_INST_sdram_a_regio[5] (to controller_marco.sys_clk_sig_c +)
Delay: 7.783ns (30.9% logic, 69.1% route), 6 logic levels.
Constraint Details:
7.783ns physical path delay controller_marco/SDRAM_CTRL_INST/SLICE_789 to sdram_a[5]_MGIOL meets
8.000ns delay constraint less
0.121ns DO_SET requirement (totaling 7.879ns) by 0.096ns
Physical Path Details:
Data path controller_marco/SDRAM_CTRL_INST/SLICE_789 to sdram_a[5]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 *SLICE_789.CLK to */SLICE_789.Q0 controller_marco/SDRAM_CTRL_INST/SLICE_789 (from controller_marco.sys_clk_sig_c)
ROUTE 4 e 0.896 */SLICE_789.Q0 to *SLICE_2435.A0 controller_marco/SDRAM_CTRL_INST/init_auto_ref_flag
CTOF_DEL --- 0.408 *SLICE_2435.A0 to *SLICE_2435.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2435
ROUTE 1 e 0.896 *SLICE_2435.F0 to *SLICE_2078.B1 controller_marco/SDRAM_CTRL_INST/sdram_a_reg_9_ss0_i_0_a2_0
CTOF_DEL --- 0.408 *SLICE_2078.B1 to *SLICE_2078.F1 controller_marco/SDRAM_CTRL_INST/SLICE_2078
ROUTE 14 e 0.896 *SLICE_2078.F1 to *SLICE_2427.A0 controller_marco/SDRAM_CTRL_INST/sdram_a_reg_9_ss0_i_0_a7
CTOF_DEL --- 0.408 *SLICE_2427.A0 to *SLICE_2427.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2427
ROUTE 1 e 0.896 *SLICE_2427.F0 to *SLICE_2087.C0 controller_marco/SDRAM_CTRL_INST/sdram_a_reg_9_m0[5]
CTOF_DEL --- 0.408 *SLICE_2087.C0 to *SLICE_2087.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2087
ROUTE 1 e 0.896 *SLICE_2087.F0 to *SLICE_2085.C0 controller_marco/SDRAM_CTRL_INST/sdram_a_reg_9_i_tz_0_0[5]
CTOF_DEL --- 0.408 *SLICE_2085.C0 to *SLICE_2085.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2085
ROUTE 1 e 0.896 *SLICE_2085.F0 to *5]_MGIOL.OPOS controller_marco.N_378_i (to controller_marco.sys_clk_sig_c)
--------
7.783 (30.9% logic, 69.1% route), 6 logic levels.
Report: 126.518MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "tft_clk_c_c" 35.714286 MHz ;
3354 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 2.478ns (weighted slack = 17.346ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/FF_74 (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/FF_15 (to tft_clk_c_c +)
Delay: 1.263ns (29.1% logic, 70.9% route), 1 logic levels.
Constraint Details:
1.263ns physical path delay controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/SLICE_722 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/SLICE_725 meets
(delay constraint based on source clock period of 8.000ns and destination clock period of 27.999ns)
3.999ns delay constraint less
0.258ns M_SET requirement (totaling 3.741ns) by 2.478ns
Physical Path Details:
Data path controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/SLICE_722 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/SLICE_725:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 *SLICE_722.CLK to */SLICE_722.Q1 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/SLICE_722 (from controller_marco.sys_clk_sig_c)
ROUTE 1 e 0.896 */SLICE_722.Q1 to */SLICE_725.M1 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/r_gcount_1 (to tft_clk_c_c)
--------
1.263 (29.1% logic, 70.9% route), 1 logic levels.
Report: 93.914MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "controller_marco/osch_clk_sig_c" 10.230000 MHz ;
310 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 92.981ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/timer_cnt_rst (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/timer_cnt[14] (to controller_marco/osch_clk_sig_c +)
Delay: 4.637ns (61.2% logic, 38.8% route), 10 logic levels.
Constraint Details:
4.637ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_775 to controller_marco/POWER_MANAGER_INST/SLICE_144 meets
97.751ns delay constraint less
0.133ns DIN_SET requirement (totaling 97.618ns) by 92.981ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_775 to controller_marco/POWER_MANAGER_INST/SLICE_144:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 *SLICE_775.CLK to */SLICE_775.Q0 controller_marco/POWER_MANAGER_INST/SLICE_775 (from controller_marco/osch_clk_sig_c)
ROUTE 1 e 0.896 */SLICE_775.Q0 to *SLICE_2561.A0 controller_marco/POWER_MANAGER_INST/timer_cnt_rst
CTOF_DEL --- 0.408 *SLICE_2561.A0 to *SLICE_2561.F0 controller_marco/POWER_MANAGER_INST/SLICE_2561
ROUTE 16 e 0.896 *SLICE_2561.F0 to */SLICE_151.B0 controller_marco/POWER_MANAGER_INST/timer_cnt_rst_i
C0TOFCO_DE --- 0.787 */SLICE_151.B0 to *SLICE_151.FCO controller_marco/POWER_MANAGER_INST/SLICE_151
ROUTE 1 e 0.001 *SLICE_151.FCO to *SLICE_150.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[0]
FCITOFCO_D --- 0.130 *SLICE_150.FCI to *SLICE_150.FCO controller_marco/POWER_MANAGER_INST/SLICE_150
ROUTE 1 e 0.001 *SLICE_150.FCO to *SLICE_149.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[2]
FCITOFCO_D --- 0.130 *SLICE_149.FCI to *SLICE_149.FCO controller_marco/POWER_MANAGER_INST/SLICE_149
ROUTE 1 e 0.001 *SLICE_149.FCO to *SLICE_148.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[4]
FCITOFCO_D --- 0.130 *SLICE_148.FCI to *SLICE_148.FCO controller_marco/POWER_MANAGER_INST/SLICE_148
ROUTE 1 e 0.001 *SLICE_148.FCO to *SLICE_147.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[6]
FCITOFCO_D --- 0.130 *SLICE_147.FCI to *SLICE_147.FCO controller_marco/POWER_MANAGER_INST/SLICE_147
ROUTE 1 e 0.001 *SLICE_147.FCO to *SLICE_146.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[8]
FCITOFCO_D --- 0.130 *SLICE_146.FCI to *SLICE_146.FCO controller_marco/POWER_MANAGER_INST/SLICE_146
ROUTE 1 e 0.001 *SLICE_146.FCO to *SLICE_145.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[10]
FCITOFCO_D --- 0.130 *SLICE_145.FCI to *SLICE_145.FCO controller_marco/POWER_MANAGER_INST/SLICE_145
ROUTE 1 e 0.001 *SLICE_145.FCO to *SLICE_144.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[12]
FCITOF1_DE --- 0.495 *SLICE_144.FCI to */SLICE_144.F1 controller_marco/POWER_MANAGER_INST/SLICE_144
ROUTE 1 e 0.001 */SLICE_144.F1 to *SLICE_144.DI1 controller_marco/POWER_MANAGER_INST/timer_cnt_s[14] (to controller_marco/osch_clk_sig_c)
--------
4.637 (61.2% logic, 38.8% route), 10 logic levels.
Report: 209.644MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "ext_osc_clk_c" 25.000000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 26.016ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm32_inst/LM32/cpu/adder_op_x (from ext_osc_clk_c +)
Destination: FF Data in lm32_inst/LM32/cpu/mc_arithmetic/a[15] (to ext_osc_clk_c +)
Delay: 13.851ns (41.7% logic, 58.3% route), 18 logic levels.
Constraint Details:
13.851ns physical path delay lm32_inst/LM32/cpu/SLICE_1134 to lm32_inst/LM32/cpu/mc_arithmetic/SLICE_1357 meets
40.000ns delay constraint less
0.133ns DIN_SET requirement (totaling 39.867ns) by 26.016ns
Physical Path Details:
Data path lm32_inst/LM32/cpu/SLICE_1134 to lm32_inst/LM32/cpu/mc_arithmetic/SLICE_1357:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 *LICE_1134.CLK to *SLICE_1134.Q0 lm32_inst/LM32/cpu/SLICE_1134 (from ext_osc_clk_c)
ROUTE 2 e 0.896 *SLICE_1134.Q0 to *SLICE_2707.A0 lm32_inst/LM32/cpu/adder_op_x
CTOF_DEL --- 0.408 *SLICE_2707.A0 to *SLICE_2707.F0 lm32_inst/LM32/cpu/adder/addsub/genblk1.addsub/SLICE_2707
ROUTE 1 e 0.896 *SLICE_2707.F0 to */SLICE_471.B0 lm32_inst/LM32/cpu/adder/addsub/genblk1.addsub/ci_k
C0TOFCO_DE --- 0.787 */SLICE_471.B0 to *SLICE_471.FCO lm32_inst/LM32/cpu/adder/addsub/genblk1.addsub/SLICE_471
ROUTE 1 e 0.001 *SLICE_471.FCO to *SLICE_472.FCI lm32_inst/LM32/cpu/adder/addsub/genblk1.addsub/co0
FCITOFCO_D --- 0.130 *SLICE_472.FCI to *SLICE_472.FCO lm32_inst/LM32/cpu/adder/addsub/genblk1.addsub/SLICE_472
ROUTE 1 e 0.001 *SLICE_472.FCO to *SLICE_473.FCI lm32_inst/LM32/cpu/adder/addsub/genblk1.addsub/co1
FCITOFCO_D --- 0.130 *SLICE_473.FCI to *SLICE_473.FCO lm32_inst/LM32/cpu/adder/addsub/genblk1.addsub/SLICE_473
ROUTE 1 e 0.001 *SLICE_473.FCO to *SLICE_474.FCI lm32_inst/LM32/cpu/adder/addsub/genblk1.addsub/co2
FCITOFCO_D --- 0.130 *SLICE_474.FCI to *SLICE_474.FCO lm32_inst/LM32/cpu/adder/addsub/genblk1.addsub/SLICE_474
ROUTE 1 e 0.001 *SLICE_474.FCO to *SLICE_475.FCI lm32_inst/LM32/cpu/adder/addsub/genblk1.addsub/co3
FCITOFCO_D --- 0.130 *SLICE_475.FCI to *SLICE_475.FCO lm32_inst/LM32/cpu/adder/addsub/genblk1.addsub/SLICE_475
ROUTE 1 e 0.001 *SLICE_475.FCO to *SLICE_476.FCI lm32_inst/LM32/cpu/adder/addsub/genblk1.addsub/co4
FCITOFCO_D --- 0.130 *SLICE_476.FCI to *SLICE_476.FCO lm32_inst/LM32/cpu/adder/addsub/genblk1.addsub/SLICE_476
ROUTE 1 e 0.001 *SLICE_476.FCO to *SLICE_477.FCI lm32_inst/LM32/cpu/adder/addsub/genblk1.addsub/co5
FCITOFCO_D --- 0.130 *SLICE_477.FCI to *SLICE_477.FCO lm32_inst/LM32/cpu/adder/addsub/genblk1.addsub/SLICE_477
ROUTE 1 e 0.001 *SLICE_477.FCO to *SLICE_478.FCI lm32_inst/LM32/cpu/adder/addsub/genblk1.addsub/co6
FCITOFCO_D --- 0.130 *SLICE_478.FCI to *SLICE_478.FCO lm32_inst/LM32/cpu/adder/addsub/genblk1.addsub/SLICE_478
ROUTE 1 e 0.001 *SLICE_478.FCO to *SLICE_479.FCI lm32_inst/LM32/cpu/adder/addsub/genblk1.addsub/co7
FCITOF0_DE --- 0.450 *SLICE_479.FCI to */SLICE_479.F0 lm32_inst/LM32/cpu/adder/addsub/genblk1.addsub/SLICE_479
ROUTE 1 e 0.896 */SLICE_479.F0 to *SLICE_2898.B0 lm32_inst/LM32/cpu/adder_result_x[15]
CTOF_DEL --- 0.408 *SLICE_2898.B0 to *SLICE_2898.F0 lm32_inst/LM32/cpu/SLICE_2898
ROUTE 1 e 0.896 *SLICE_2898.F0 to *SLICE_2135.D1 lm32_inst/LM32/cpu/x_result_1_0_iv_0[15]
CTOF_DEL --- 0.408 *SLICE_2135.D1 to *SLICE_2135.F1 lm32_inst/LM32/cpu/SLICE_2135
ROUTE 1 e 0.896 *SLICE_2135.F1 to *SLICE_2305.D0 lm32_inst/LM32/cpu/x_result_1_0_iv_2[15]
CTOF_DEL --- 0.408 *SLICE_2305.D0 to *SLICE_2305.F0 lm32_inst/LM32/cpu/SLICE_2305
ROUTE 2 e 0.896 *SLICE_2305.F0 to *SLICE_1527.C1 lm32_inst/LM32/cpu/x_result_1_0_iv_3[15]
CTOF_DEL --- 0.408 *SLICE_1527.C1 to *SLICE_1527.F1 lm32_inst/LM32/cpu/SLICE_1527
ROUTE 2 e 0.896 *SLICE_1527.F1 to *SLICE_2839.C0 lm32_inst/LM32/cpu/x_result_1[15]
CTOF_DEL --- 0.408 *SLICE_2839.C0 to *SLICE_2839.F0 lm32_inst/LM32/cpu/SLICE_2839
ROUTE 2 e 0.896 *SLICE_2839.F0 to *SLICE_1458.A1 lm32_inst/LM32/cpu/bypass_data_0[15]
CTOF_DEL --- 0.408 *SLICE_1458.A1 to *SLICE_1458.F1 lm32_inst/LM32/cpu/SLICE_1458
ROUTE 2 e 0.896 *SLICE_1458.F1 to *SLICE_1357.B1 lm32_inst/LM32/cpu/d_result_0_i_m3[15]
CTOF_DEL --- 0.408 *SLICE_1357.B1 to *SLICE_1357.F1 lm32_inst/LM32/cpu/mc_arithmetic/SLICE_1357
ROUTE 1 e 0.001 *SLICE_1357.F1 to *LICE_1357.DI1 lm32_inst/LM32/cpu/mc_arithmetic/N_208 (to ext_osc_clk_c)
--------
13.851 (41.7% logic, 58.3% route), 18 logic levels.
Report: 71.510MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY PORT "ext_osc_clk" 25.000000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 33.340ns
The internal maximum frequency of the following component is 150.150 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD ext_osc_clk
Delay: 6.660ns -- based on Minimum Pulse Width
Report: 150.150MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET | | |
"controller_marco.sys_clk_sig_c" | | |
125.000000 MHz ; | 125.000 MHz| 126.518 MHz| 6
| | |
FREQUENCY NET "tft_clk_c_c" 35.714286 | | |
MHz ; | 35.714 MHz| 93.914 MHz| 1
| | |
FREQUENCY NET | | |
"controller_marco/osch_clk_sig_c" | | |
10.230000 MHz ; | 10.230 MHz| 209.644 MHz| 10
| | |
FREQUENCY NET "ext_osc_clk_c" 25.000000 | | |
MHz ; | 25.000 MHz| 71.510 MHz| 18
| | |
FREQUENCY PORT "ext_osc_clk" 25.000000 | | |
MHz ; | 25.000 MHz| 150.150 MHz| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 6 clocks:
Clock Domain: controller_marco.sys_clk_sig_c Source: controller_marco/PLL_BLOCK_INST/PLLInst_0.CLKOP Loads: 313
Covered under: FREQUENCY NET "controller_marco.sys_clk_sig_c" 125.000000 MHz ;
Data transfers from:
Clock Domain: tft_clk_c_c Source: controller_marco/PLL_BLOCK_INST/PLLInst_0.CLKOS3
Covered under: FREQUENCY NET "controller_marco.sys_clk_sig_c" 125.000000 MHz ; Transfers: 71
Clock Domain: controller_marco/osch_clk_sig_c Source: controller_marco/OSCH_INST.OSC
Not reported because source and destination domains are unrelated.
Clock Domain: ext_osc_clk_c Source: ext_osc_clk.PAD
Covered under: FREQUENCY NET "controller_marco.sys_clk_sig_c" 125.000000 MHz ; Transfers: 26
Clock Domain: tft_clk_c_c Source: controller_marco/PLL_BLOCK_INST/PLLInst_0.CLKOS3 Loads: 271
Covered under: FREQUENCY NET "tft_clk_c_c" 35.714286 MHz ;
Data transfers from:
Clock Domain: controller_marco.sys_clk_sig_c Source: controller_marco/PLL_BLOCK_INST/PLLInst_0.CLKOP
Covered under: FREQUENCY NET "tft_clk_c_c" 35.714286 MHz ; Transfers: 33
Clock Domain: controller_marco/osch_clk_sig_c Source: controller_marco/OSCH_INST.OSC Loads: 17
Covered under: FREQUENCY NET "controller_marco/osch_clk_sig_c" 10.230000 MHz ;
Clock Domain: ext_osc_clk_c Source: ext_osc_clk.PAD Loads: 886
Covered under: FREQUENCY NET "ext_osc_clk_c" 25.000000 MHz ;
Data transfers from:
Clock Domain: controller_marco.sys_clk_sig_c Source: controller_marco/PLL_BLOCK_INST/PLLInst_0.CLKOP
Covered under: FREQUENCY NET "ext_osc_clk_c" 25.000000 MHz ; Transfers: 25
Clock Domain: lm32_inst/LM32/jtag_update Source: lm32_inst/LM32/jtag_cores/jtag_lm32_inst/SLICE_3033.F0
Not reported because source and destination domains are unrelated.
Clock Domain: jtaghub16_jtck Source: xo2chub/genblk0_genblk6_jtagf_u.JTCK
Not reported because source and destination domains are unrelated.
Clock Domain: lm32_inst/LM32/jtag_update Source: lm32_inst/LM32/jtag_cores/jtag_lm32_inst/SLICE_3033.F0 Loads: 1
No transfer within this clock domain is found
Clock Domain: jtaghub16_jtck Source: xo2chub/genblk0_genblk6_jtagf_u.JTCK Loads: 40
No transfer within this clock domain is found
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 16599272 paths, 6 nets, and 18274 connections (91.9% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond Version 2.0.0.154
Thu Jan 31 12:26:04 2013
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2012 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o tftsurfer_tftsurfer.tw1 tftsurfer_tftsurfer_map.ncd tftsurfer_tftsurfer.prf
Design file: tftsurfer_tftsurfer_map.ncd
Preference file: tftsurfer_tftsurfer.prf
Device,speed: LCMXO2-7000HC,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "controller_marco.sys_clk_sig_c" 125.000000 MHz (0 errors) 2488 items scored, 0 timing errors detected.
FREQUENCY NET "tft_clk_c_c" 35.714286 MHz (0 errors) 3354 items scored, 0 timing errors detected.
FREQUENCY NET "controller_marco/osch_clk_sig_c" 10.230000 MHz (0 errors) 310 items scored, 0 timing errors detected.
FREQUENCY NET "ext_osc_clk_c" 25.000000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
FREQUENCY PORT "ext_osc_clk" 25.000000 MHz (0 errors) 0 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "controller_marco.sys_clk_sig_c" 125.000000 MHz ;
2488 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.285ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_1/RAM0 (from tft_clk_c_c +)
Destination: FF Data in controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/FF_32 (to controller_marco.sys_clk_sig_c +)
Delay: 0.272ns (99.6% logic, 0.4% route), 1 logic levels.
Constraint Details:
0.272ns physical path delay controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_1 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_1 meets
(delay constraint based on source clock period of 27.999ns and destination clock period of 8.000ns)
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.285ns
Physical Path Details:
Data path controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_1 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_1:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 *o_pfu_0_1.WCK to *fo_pfu_0_1.F0 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_1 (from tft_clk_c_c)
ROUTE 1 e 0.001 *fo_pfu_0_1.F0 to *o_pfu_0_1.DI0 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/rdataout16 (to controller_marco.sys_clk_sig_c)
--------
0.272 (99.6% logic, 0.4% route), 1 logic levels.
================================================================================
Preference: FREQUENCY NET "tft_clk_c_c" 35.714286 MHz ;
3354 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.285ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_0/RAM1 (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/FF_22 (to tft_clk_c_c +)
Delay: 0.272ns (99.6% logic, 0.4% route), 1 logic levels.
Constraint Details:
0.272ns physical path delay controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_0.38 to controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_0.38 meets
(delay constraint based on source clock period of 8.000ns and destination clock period of 27.999ns)
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.285ns
Physical Path Details:
Data path controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_0.38 to controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_0.38:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 *fu_0_0.38.WCK to *pfu_0_0.38.F1 controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_0.38 (from controller_marco.sys_clk_sig_c)
ROUTE 1 e 0.001 *pfu_0_0.38.F1 to *fu_0_0.38.DI1 controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/rdataout15 (to tft_clk_c_c)
--------
0.272 (99.6% logic, 0.4% route), 1 logic levels.
================================================================================
Preference: FREQUENCY NET "controller_marco/osch_clk_sig_c" 10.230000 MHz ;
310 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.349ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/pll_lock_reg0 (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/pll_lock_reg1 (to controller_marco/osch_clk_sig_c +)
Delay: 0.330ns (39.7% logic, 60.3% route), 1 logic levels.
Constraint Details:
0.330ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_772 to controller_marco/POWER_MANAGER_INST/SLICE_772 meets
-0.019ns M_HLD and
0.000ns delay constraint requirement (totaling -0.019ns) by 0.349ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_772 to controller_marco/POWER_MANAGER_INST/SLICE_772:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 *SLICE_772.CLK to */SLICE_772.Q0 controller_marco/POWER_MANAGER_INST/SLICE_772 (from controller_marco/osch_clk_sig_c)
ROUTE 1 e 0.199 */SLICE_772.Q0 to */SLICE_772.M1 controller_marco/POWER_MANAGER_INST/pll_lock_reg0 (to controller_marco/osch_clk_sig_c)
--------
0.330 (39.7% logic, 60.3% route), 1 logic levels.
================================================================================
Preference: FREQUENCY NET "ext_osc_clk_c" 25.000000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.285ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q controller_marco/inst_wb_data_fifo/fifo_pfu_0_0/RAM0 (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco/inst_wb_data_fifo/FF_13 (to ext_osc_clk_c +)
Delay: 0.272ns (99.6% logic, 0.4% route), 1 logic levels.
Constraint Details:
0.272ns physical path delay controller_marco/inst_wb_data_fifo/fifo_pfu_0_0.12 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_0.12 meets
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.285ns
Physical Path Details:
Data path controller_marco/inst_wb_data_fifo/fifo_pfu_0_0.12 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_0.12:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 *fu_0_0.12.WCK to *pfu_0_0.12.F0 controller_marco/inst_wb_data_fifo/fifo_pfu_0_0.12 (from controller_marco.sys_clk_sig_c)
ROUTE 1 e 0.001 *pfu_0_0.12.F0 to *fu_0_0.12.DI0 controller_marco/inst_wb_data_fifo/rdataout12 (to ext_osc_clk_c)
--------
0.272 (99.6% logic, 0.4% route), 1 logic levels.
================================================================================
Preference: FREQUENCY PORT "ext_osc_clk" 25.000000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET | | |
"controller_marco.sys_clk_sig_c" | | |
125.000000 MHz ; | -| -| 1
| | |
FREQUENCY NET "tft_clk_c_c" 35.714286 | | |
MHz ; | -| -| 1
| | |
FREQUENCY NET | | |
"controller_marco/osch_clk_sig_c" | | |
10.230000 MHz ; | -| -| 1
| | |
FREQUENCY NET "ext_osc_clk_c" 25.000000 | | |
MHz ; | -| -| 1
| | |
FREQUENCY PORT "ext_osc_clk" 25.000000 | | |
MHz ; | -| -| 0
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 6 clocks:
Clock Domain: controller_marco.sys_clk_sig_c Source: controller_marco/PLL_BLOCK_INST/PLLInst_0.CLKOP Loads: 313
Covered under: FREQUENCY NET "controller_marco.sys_clk_sig_c" 125.000000 MHz ;
Data transfers from:
Clock Domain: tft_clk_c_c Source: controller_marco/PLL_BLOCK_INST/PLLInst_0.CLKOS3
Covered under: FREQUENCY NET "controller_marco.sys_clk_sig_c" 125.000000 MHz ; Transfers: 71
Clock Domain: controller_marco/osch_clk_sig_c Source: controller_marco/OSCH_INST.OSC
Not reported because source and destination domains are unrelated.
Clock Domain: ext_osc_clk_c Source: ext_osc_clk.PAD
Covered under: FREQUENCY NET "controller_marco.sys_clk_sig_c" 125.000000 MHz ; Transfers: 26
Clock Domain: tft_clk_c_c Source: controller_marco/PLL_BLOCK_INST/PLLInst_0.CLKOS3 Loads: 271
Covered under: FREQUENCY NET "tft_clk_c_c" 35.714286 MHz ;
Data transfers from:
Clock Domain: controller_marco.sys_clk_sig_c Source: controller_marco/PLL_BLOCK_INST/PLLInst_0.CLKOP
Covered under: FREQUENCY NET "tft_clk_c_c" 35.714286 MHz ; Transfers: 33
Clock Domain: controller_marco/osch_clk_sig_c Source: controller_marco/OSCH_INST.OSC Loads: 17
Covered under: FREQUENCY NET "controller_marco/osch_clk_sig_c" 10.230000 MHz ;
Clock Domain: ext_osc_clk_c Source: ext_osc_clk.PAD Loads: 886
Covered under: FREQUENCY NET "ext_osc_clk_c" 25.000000 MHz ;
Data transfers from:
Clock Domain: controller_marco.sys_clk_sig_c Source: controller_marco/PLL_BLOCK_INST/PLLInst_0.CLKOP
Covered under: FREQUENCY NET "ext_osc_clk_c" 25.000000 MHz ; Transfers: 25
Clock Domain: lm32_inst/LM32/jtag_update Source: lm32_inst/LM32/jtag_cores/jtag_lm32_inst/SLICE_3033.F0
Not reported because source and destination domains are unrelated.
Clock Domain: jtaghub16_jtck Source: xo2chub/genblk0_genblk6_jtagf_u.JTCK
Not reported because source and destination domains are unrelated.
Clock Domain: lm32_inst/LM32/jtag_update Source: lm32_inst/LM32/jtag_cores/jtag_lm32_inst/SLICE_3033.F0 Loads: 1
No transfer within this clock domain is found
Clock Domain: jtaghub16_jtck Source: xo2chub/genblk0_genblk6_jtagf_u.JTCK Loads: 40
No transfer within this clock domain is found
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 16599272 paths, 6 nets, and 19100 connections (96.0% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------