#INFO: (ST-1216) Setting log file to 'C:/work/project/artekit/periferica_SPI/prj/hdldiagram_gen_hierarchy.html'. FileList::LoadDesign #-- (VHDL-1504) The default vhdl library search path is now "c:/lscc/diamond/2.0/cae_library/vhdl_packages/vdbs" #-- (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.vhd #-- (VHDL-1493) Restoring VHDL parse-tree ieee.std_logic_1164 from c:/lscc/diamond/2.0/cae_library/vhdl_packages/vdbs/ieee/std_logic_1164.vdb #-- (VHDL-1493) Restoring VHDL parse-tree std.standard from c:/lscc/diamond/2.0/cae_library/vhdl_packages/vdbs/std/standard.vdb #-- (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/2.0/cae_library/synthesis/vhdl/machxo2.pkg #-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/periferica_SPI/SPI_top.vhd #-- (VHDL-1493) Restoring VHDL parse-tree ieee.std_logic_unsigned from c:/lscc/diamond/2.0/cae_library/vhdl_packages/vdbs/ieee/std_logic_unsigned.vdb #-- (VHDL-1493) Restoring VHDL parse-tree ieee.std_logic_arith from c:/lscc/diamond/2.0/cae_library/vhdl_packages/vdbs/ieee/std_logic_arith.vdb #c:/work/project/artekit/periferica_spi/spi_top.vhd(6,8-6,15) INFO: (VHDL-1012) analyzing entity spi_top #c:/work/project/artekit/periferica_spi/spi_top.vhd(35,14-35,25) INFO: (VHDL-1010) analyzing architecture rtl_spi_top #--Elaborating Design #c:/work/project/artekit/periferica_spi/spi_top.vhd(6,8-6,15) INFO: (VHDL-1067) elaborating SPI_top(rtl_SPI_top) #-- (ST-1001) Root modules/entities/cells (1): #-- spi_top #Design load finished with (0) errors, and (0) warnings.