Lattice Mapping Report File for Design Module 'SPI_top' Design Information Command line: map -a MachXO2 -p LCMXO2-7000HC -t FPBGA484 -s 5 -oc Commercial prj_prj.ngd -o prj_prj_map.ncd -pr prj_prj.prf -mp prj_prj.mrp C:/work/project/artekit/periferica_SPI/prj.lpf -c 0 Target Vendor: LATTICE Target Device: LCMXO2-7000HCFPBGA484 Target Performance: 5 Mapper: xo2c00, version: Diamond Version 2.0.0.154 Mapped on: 03/29/13 13:58:16 Design Summary Number of registers: 44 PFU registers: 40 PIO registers: 4 Number of SLICEs: 25 out of 3432 (1%) SLICEs(logic/ROM): 13 out of 858 (2%) SLICEs(logic/ROM/RAM): 12 out of 2574 (0%) As RAM: 12 out of 2574 (0%) As Logic/ROM: 0 out of 2574 (0%) Number of logic LUT4s: 9 Number of distributed RAM: 12 (24 LUT4s) Number of ripple logic: 0 (0 LUT4s) Number of shift registers: 0 Total number of LUT4s: 33 Number of PIO sites used: 46 out of 335 (14%) Number of block RAMs: 0 out of 26 (0%) Number of GSRs: 1 out of 1 (100%) EFB used : No JTAG used : No Readback used : No Oscillator used : No Startup used : No POR : On Bandgap : On Number of Power Controller: 0 out of 1 (0%) Number of Dynamic Bank Controller (BCINRD): 0 out of 6 (0%) Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%) Number of DCCA: 0 out of 8 (0%) Number of DCMA: 0 out of 2 (0%) Number of PLLs: 0 out of 2 (0%) Number of DQSDLLs: 0 out of 2 (0%) Number of CLKDIVC: 0 out of 4 (0%) Number of ECLKSYNCA: 0 out of 4 (0%) Number of ECLKBRIDGECS: 0 out of 2 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 1 Net WB_CLK_c: 33 loads, 33 rising, 0 falling (Driver: PIO WB_CLK ) Number of Clock Enables: 5 Net rst_c: 4 loads, 2 LSLICEs Net un4_u_spi_clk_smp2_0: 9 loads, 8 LSLICEs Net Datace[8]: 4 loads, 4 LSLICEs Net WrAddress_0_sqmuxa_1: 2 loads, 2 LSLICEs Net Datace[0]: 4 loads, 4 LSLICEs Number of local set/reset loads for net rst_c merged into GSR: 18 Number of LSRs: 0 Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: Net WB_ADR_I_c[0]: 16 loads Net WB_ADR_I_c[1]: 16 loads Net WB_ADR_I_c[2]: 16 loads Net WB_ADR_I_c[3]: 16 loads Net un4_u_spi_clk_smp2_0: 9 loads Net rst_c: 8 loads Net WE: 8 loads Net input_SR[8]: 5 loads Net input_SR[9]: 5 loads Net Datace[8]: 4 loads Number of warnings: 74 Number of errors: 0 Design Errors/Warnings WARNING: Using local reset signal 'rst_c' to infer global GSR net. WARNING: IO buffer missing for top level port clk...logic will be discarded. WARNING: IO buffer missing for top level port WB_RST...logic will be discarded. WARNING: IO buffer missing for top level port WB_CTI_I[2:0](2)...logic will be discarded. WARNING: IO buffer missing for top level port WB_CTI_I[2:0](1)...logic will be discarded. WARNING: IO buffer missing for top level port WB_CTI_I[2:0](0)...logic will be discarded. WARNING: IO buffer missing for top level port WB_BTE_I[1:0](1)...logic will be discarded. WARNING: IO buffer missing for top level port WB_BTE_I[1:0](0)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](31)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](30)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](29)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](28)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](27)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](26)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](25)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](24)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](23)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](22)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](21)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](20)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](19)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](18)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](17)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](16)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](15)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](14)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](13)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](12)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](11)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](10)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](9)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](8)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](7)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](6)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](5)...logic will be discarded. WARNING: IO buffer missing for top level port WB_ADR_I[31:0](4)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](31)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](30)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](29)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](28)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](27)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](26)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](25)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](24)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](23)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](22)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](21)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](20)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](19)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](18)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](17)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](16)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](15)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](14)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](13)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](12)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](11)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](10)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](9)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](8)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](7)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](6)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](5)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](4)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](3)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](2)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](1)...logic will be discarded. WARNING: IO buffer missing for top level port WB_DAT_I[31:0](0)...logic will be discarded. WARNING: IO buffer missing for top level port WB_SEL_I[3:0](3)...logic will be discarded. WARNING: IO buffer missing for top level port WB_SEL_I[3:0](2)...logic will be discarded. WARNING: IO buffer missing for top level port WB_SEL_I[3:0](1)...logic will be discarded. WARNING: IO buffer missing for top level port WB_SEL_I[3:0](0)...logic will be discarded. WARNING: IO buffer missing for top level port WB_WE_I...logic will be discarded. WARNING: IO buffer missing for top level port WB_CYC_I...logic will be discarded. IO (PIO) Attributes +---------------------+-----------+-----------+------------+ | IO Name | Direction | Levelmode | IO | | | | IO_TYPE | Register | +---------------------+-----------+-----------+------------+ | u_spi_q | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | rst | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_RTY_O | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_ERR_O | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[31] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[30] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[29] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[28] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[27] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[26] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[25] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[24] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[23] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[22] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[21] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[20] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[19] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[18] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[17] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[16] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[15] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[14] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[13] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[12] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[11] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[10] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[9] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[8] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[7] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[6] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[5] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[4] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[3] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[2] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[1] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_DAT_O[0] | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_ACK_O | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_STB_I | INPUT | LVCMOS25 | IN | +---------------------+-----------+-----------+------------+ | WB_ADR_I[3] | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_ADR_I[2] | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_ADR_I[1] | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_ADR_I[0] | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | WB_CLK | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | u_spi_d | INPUT | LVCMOS25 | IN | +---------------------+-----------+-----------+------------+ | u_spi_clk | INPUT | LVCMOS25 | IN | +---------------------+-----------+-----------+------------+ | u_spi_csn | INPUT | LVCMOS25 | IN | +---------------------+-----------+-----------+------------+ Removed logic Signal rst_c_i was merged into signal rst_c Signal inst_memoria/dec0_wre3 was merged into signal WE Signal VCC undriven or does not drive anything - clipped. Block rst_pad_RNI1068 was optimized away. Block inst_memoria/LUT4_0 was optimized away. Block VCC was optimized away. Memory Usage /inst_memoria: EBRs: 0 RAM SLICEs: 12 Logic SLICEs: 0 PFU Registers: 16 GSR Usage --------- GSR Component: The local reset signal 'rst_c' of the design has been inferred as Global Set Reset (GSR). The reset signal used for GSR control is 'rst_c'. GSR Property: The design components with GSR property set to ENABLED will respond to global set reset while the components with GSR property set to DISABLED will not. Components on inferred reset domain with GSR Property disabled -------------------------------------------------------------- These components have the GSR property set to DISABLED and are on the inferred reset domain. The components will respond to the reset signal 'rst_c' via the local reset on the component and not the GSR component. Type and number of components of the type: Register = 6 Type and instance name of component: Register : WE Register : u_spi_clk_smp2 Register : u_spi_csn_smp2 Register : u_spi_csn_smp3 Register : u_spi_clk_smp1_0io Register : u_spi_csn_smp1_0io Run Time and Memory Usage ------------------------- Total CPU Time: 0 secs Total REAL Time: 0 secs Peak Memory Usage: 29 MB Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2012 Lattice Semiconductor Corporation, All rights reserved.