Setting log file to 'C:/work/project/artekit/periferica_SPI/prj/hdla_gen_hierarchy.html'.
INFO: (VHDL-1504) The default vhdl library search path is now "C:/lscc/diamond/2.1/cae_library/vhdl_packages/vdbs"
-- (VHDL-1481) Analyzing VHDL file C:/lscc/diamond/2.1/cae_library/synthesis/vhdl/machxo2.pkg
-- (VHDL-1493) Restoring VHDL parse-tree ieee.std_logic_1164 from C:/lscc/diamond/2.1/cae_library/vhdl_packages/vdbs/ieee/std_logic_1164.vdb
-- (VHDL-1493) Restoring VHDL parse-tree std.standard from C:/lscc/diamond/2.1/cae_library/vhdl_packages/vdbs/std/standard.vdb
-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/periferica_SPI/SPI_top.vhd
-- (VHDL-1493) Restoring VHDL parse-tree ieee.std_logic_unsigned from C:/lscc/diamond/2.1/cae_library/vhdl_packages/vdbs/ieee/std_logic_unsigned.vdb
-- (VHDL-1493) Restoring VHDL parse-tree ieee.std_logic_arith from C:/lscc/diamond/2.1/cae_library/vhdl_packages/vdbs/ieee/std_logic_arith.vdb
C:/work/project/artekit/periferica_SPI/SPI_top.vhd(6,8-6,15) INFO: (VHDL-1012) analyzing entity spi_top
C:/work/project/artekit/periferica_SPI/SPI_top.vhd(36,14-36,25) INFO: (VHDL-1010) analyzing architecture rtl_spi_top
-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/periferica_SPI/memoria.vhd
C:/work/project/artekit/periferica_SPI/memoria.vhd(14,8-14,15) INFO: (VHDL-1012) analyzing entity memoria
C:/work/project/artekit/periferica_SPI/memoria.vhd(25,14-25,23) INFO: (VHDL-1010) analyzing architecture structure
-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/periferica_SPI/SPI_top_RW.vhd
C:/work/project/artekit/periferica_SPI/SPI_top_RW.vhd(6,8-6,18) INFO: (VHDL-1012) analyzing entity spi_top_rw
C:/work/project/artekit/periferica_SPI/SPI_top_RW.vhd(34,5-34,12) ERROR: (VHDL-1135) mismatch on label ; expected spi_top_rw
C:/work/project/artekit/periferica_SPI/SPI_top_RW.vhd(6,1-34,13) ERROR: (VHDL-1284) unit spi_top_rw ignored due to previous errors
-- (VHDL-1482) VHDL file C:/work/project/artekit/periferica_SPI/SPI_top_RW.vhd ignored due to errors
-- (VHDL-1481) Analyzing VHDL file C:/work/project/artekit/periferica_SPI/memoriadp.vhd
C:/work/project/artekit/periferica_SPI/memoriadp.vhd(14,8-14,17) INFO: (VHDL-1012) analyzing entity memoriadp
C:/work/project/artekit/periferica_SPI/memoriadp.vhd(34,14-34,23) INFO: (VHDL-1010) analyzing architecture structure
C:/work/project/artekit/periferica_SPI/SPI_top.vhd(6,8-6,15) INFO: (VHDL-1067) elaborating SPI_top(rtl_SPI_top)
C:/work/project/artekit/periferica_SPI/memoria.vhd(14,8-14,15) INFO: (VHDL-1067) elaborating memoria_uniq_0(Structure)
C:/work/project/artekit/periferica_SPI/memoria.vhd(73,5-74,33) WARNING: (VHDL-1250) vlo remains a black-box since it has no binding entity
C:/work/project/artekit/periferica_SPI/memoria.vhd(76,5-77,33) WARNING: (VHDL-1250) vhi remains a black-box since it has no binding entity
C:/work/project/artekit/periferica_SPI/memoria.vhd(79,5-82,45) WARNING: (VHDL-1250) rom16x1a remains a black-box since it has no binding entity
C:/work/project/artekit/periferica_SPI/memoria.vhd(84,5-91,49) WARNING: (VHDL-1250) dpr16x4c remains a black-box since it has no binding entity
C:/work/project/artekit/periferica_SPI/memoria.vhd(93,5-100,37) WARNING: (VHDL-1250) dpr16x4c remains a black-box since it has no binding entity
C:/work/project/artekit/periferica_SPI/memoria.vhd(102,5-109,24) WARNING: (VHDL-1250) dpr16x4c remains a black-box since it has no binding entity
C:/work/project/artekit/periferica_SPI/memoria.vhd(111,5-118,24) WARNING: (VHDL-1250) dpr16x4c remains a black-box since it has no binding entity
C:/work/project/artekit/periferica_SPI/memoriadp.vhd(14,8-14,17) INFO: (VHDL-1067) elaborating memoriadp(Structure)
C:/work/project/artekit/periferica_SPI/memoriadp.vhd(117,5-178,26) WARNING: (VHDL-1250) dp8kc remains a black-box since it has no binding entity
C:/work/project/artekit/periferica_SPI/memoriadp.vhd(180,5-181,33) WARNING: (VHDL-1250) vhi remains a black-box since it has no binding entity
C:/work/project/artekit/periferica_SPI/memoriadp.vhd(183,5-184,33) WARNING: (VHDL-1250) vlo remains a black-box since it has no binding entity
C:/work/project/artekit/periferica_SPI/memoriadp.vhd(186,5-247,26) WARNING: (VHDL-1250) dp8kc remains a black-box since it has no binding entity
Design load finished with (2) errors, and (11) warnings.