Map TRACE Report

Loading design for application trce from file prj_prj_map.ncd.
Design name: SPI_top
NCD version: 3.2
Vendor:      LATTICE
Device:      LCMXO2-7000HC
Package:     FPBGA484
Performance: 5
Loading device for application trce from file 'xo2c7000.nph' in environment: C:/lscc/diamond/2.0/ispfpga.
Package Status:                     Final          Version 1.30
Performance Hardware Data Status:   Final)         Version 22.4
Setup and Hold Report

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Lattice TRACE Report - Setup, Version Diamond Version 2.0.0.154
Fri Mar 29 13:58:17 2013

Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp.   All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc.  All rights reserved.
Copyright (c) 2001 Agere Systems   All rights reserved.
Copyright (c) 2002-2012 Lattice Semiconductor Corporation,  All rights reserved.

Report Information
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Command line:    trce -v 1 -gt -mapchkpnt 0 -sethld -o prj_prj.tw1 prj_prj_map.ncd prj_prj.prf 
Design file:     prj_prj_map.ncd
Preference file: prj_prj.prf
Device,speed:    LCMXO2-7000HC,5
Report level:    verbose report, limited to 1 item per preference
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Preference Summary

  • FREQUENCY NET "WB_CLK_c" 323.311000 MHz (124 errors)
  • 223 items scored, 124 timing errors detected. Warning: 163.026MHz is the maximum frequency for this preference. Report Type: based on TRACE automatically generated preferences BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "WB_CLK_c" 323.311000 MHz ; 223 items scored, 124 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 3.042ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q input_SR[11] (from WB_CLK_c +) Destination: FF Data in WrAddress[3] (to WB_CLK_c +) FF WrAddress[2] Delay: 5.885ns (30.0% logic, 70.0% route), 4 logic levels. Constraint Details: 5.885ns physical path delay SLICE_29 to SLICE_34 exceeds 3.092ns delay constraint less 0.249ns CE_SET requirement (totaling 2.843ns) by 3.042ns Physical Path Details: Data path SLICE_29 to SLICE_34: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.409 SLICE_29.CLK to SLICE_29.Q0 SLICE_29 (from WB_CLK_c) ROUTE 2 e 1.030 SLICE_29.Q0 to SLICE_33.A1 input_SR[11] CTOF_DEL --- 0.452 SLICE_33.A1 to SLICE_33.F1 SLICE_33 ROUTE 1 e 1.030 SLICE_33.F1 to SLICE_34.D1 un1_WrAddress_0_sqmuxa_0_a2_0_4 CTOF_DEL --- 0.452 SLICE_34.D1 to SLICE_34.F1 SLICE_34 ROUTE 4 e 1.030 SLICE_34.F1 to SLICE_35.A1 N_104 CTOF_DEL --- 0.452 SLICE_35.A1 to SLICE_35.F1 SLICE_35 ROUTE 2 e 1.030 SLICE_35.F1 to SLICE_34.CE WrAddress_0_sqmuxa_1 (to WB_CLK_c) -------- 5.885 (30.0% logic, 70.0% route), 4 logic levels. Warning: 163.026MHz is the maximum frequency for this preference. Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "WB_CLK_c" 323.311000 MHz | | | ; | 323.311 MHz| 163.026 MHz| 4 * | | | ---------------------------------------------------------------------------- 1 preference(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- N_104 | 4| 88| 70.97% | | | un1_WrAddress_0_sqmuxa_0_a2_0_4 | 1| 44| 35.48% | | | Datace[0] | 4| 40| 32.26% | | | Datace[8] | 4| 40| 32.26% | | | un1_WrAddress_0_sqmuxa_0_a2_0_3 | 1| 22| 17.74% | | | WrAddress_0_sqmuxa_1 | 2| 20| 16.13% | | | un4_u_spi_clk_smp2_0 | 9| 16| 12.90% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: WB_CLK_c Source: WB_CLK.PAD Loads: 33 Covered under: FREQUENCY NET "WB_CLK_c" 323.311000 MHz ; Timing summary (Setup): --------------- Timing errors: 124 Score: 209031 Cumulative negative slack: 209031 Constraints cover 223 paths, 1 nets, and 207 connections (65.3% coverage) -------------------------------------------------------------------------------- Lattice TRACE Report - Hold, Version Diamond Version 2.0.0.154 Fri Mar 29 13:58:17 2013 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2012 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o prj_prj.tw1 prj_prj_map.ncd prj_prj.prf Design file: prj_prj_map.ncd Preference file: prj_prj.prf Device,speed: LCMXO2-7000HC,M Report level: verbose report, limited to 1 item per preference -------------------------------------------------------------------------------- Preference Summary
  • FREQUENCY NET "WB_CLK_c" 323.311000 MHz (0 errors)
  • 223 items scored, 0 timing errors detected. BLOCK ASYNCPATHS BLOCK RESETPATHS -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "WB_CLK_c" 323.311000 MHz ; 223 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.349ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q input_SR[10] (from WB_CLK_c +) Destination: FF Data in input_SR[11] (to WB_CLK_c +) Delay: 0.330ns (39.7% logic, 60.3% route), 1 logic levels. Constraint Details: 0.330ns physical path delay SLICE_29 to SLICE_29 meets -0.019ns M_HLD and 0.000ns delay constraint requirement (totaling -0.019ns) by 0.349ns Physical Path Details: Data path SLICE_29 to SLICE_29: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 SLICE_29.CLK to SLICE_29.Q1 SLICE_29 (from WB_CLK_c) ROUTE 2 e 0.199 SLICE_29.Q1 to SLICE_29.M0 input_SR[10] (to WB_CLK_c) -------- 0.330 (39.7% logic, 60.3% route), 1 logic levels. Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "WB_CLK_c" 323.311000 MHz | | | ; | -| -| 1 | | | ---------------------------------------------------------------------------- All preferences were met. Clock Domains Analysis ------------------------ Found 1 clocks: Clock Domain: WB_CLK_c Source: WB_CLK.PAD Loads: 33 Covered under: FREQUENCY NET "WB_CLK_c" 323.311000 MHz ; Timing summary (Hold): --------------- Timing errors: 0 Score: 0 Cumulative negative slack: 0 Constraints cover 223 paths, 1 nets, and 207 connections (65.3% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 124 (setup), 0 (hold) Score: 209031 (setup), 0 (hold) Cumulative negative slack: 209031 (209031+0) -------------------------------------------------------------------------------- --------------------------------------------------------------------------------