#Build: Synplify Pro E-2010.09L-SP2, Build 081R, Feb 16 2011
#install: C:\lscc\diamond\1.2\synpbase
#OS:  6.1
#Hostname: LMOBILE06

#Implementation: tftsurfer

#Sun Sep 18 00:45:36 2011

$ Start of Compile
#Sun Sep 18 00:45:36 2011

Synopsys VHDL Compiler, version comp520rcp2, Build 118R, built Feb 11 2011
@N: :  | Running in 32-bit mode 
Copyright (C) 1994-2011 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

@N:CD720 : std.vhd(123) | Setting time resolution to ns
@N: : tftsurfer_top.vhd(48) | Top entity is set to tftsurfer_top.
VHDL syntax check successful!
File C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v0\par_d12\..\src\sdram_ctrl.vhd changed - recompiling
@N:CD630 : tftsurfer_top.vhd(48) | Synthesizing work.tftsurfer_top.rtl_tftsurfer_top 
@N:CD630 : machxo2.vhd(2289) | Synthesizing work.osch.syn_black_box 
Post processing for work.osch.syn_black_box
@N:CD630 : machxo2.vhd(2032) | Synthesizing work.oddrxe.syn_black_box 
Post processing for work.oddrxe.syn_black_box
@W:CD638 : tftsurfer_top.vhd(404) | Signal tft_bank_sig is undriven 
@W:CD638 : tftsurfer_top.vhd(405) | Signal tft_sect_sig is undriven 
@N:CD630 : tx_lvds_71.vhd(14) | Synthesizing work.tx_lvds_71.structure 
@N:CD630 : machxo2.vhd(1406) | Synthesizing work.rom16x1a.syn_black_box 
Post processing for work.rom16x1a.syn_black_box
@N:CD630 : machxo2.vhd(221) | Synthesizing work.fd1p3bx.syn_black_box 
Post processing for work.fd1p3bx.syn_black_box
@N:CD630 : machxo2.vhd(233) | Synthesizing work.fd1p3dx.syn_black_box 
Post processing for work.fd1p3dx.syn_black_box
@N:CD630 : machxo2.vhd(2068) | Synthesizing work.oddrx71a.syn_black_box 
Post processing for work.oddrx71a.syn_black_box
@N:CD630 : machxo2.vhd(1902) | Synthesizing work.clkdivc.syn_black_box 
Post processing for work.clkdivc.syn_black_box
@N:CD630 : machxo2.vhd(1181) | Synthesizing work.ob.syn_black_box 
Post processing for work.ob.syn_black_box
@N:CD630 : machxo2.vhd(1922) | Synthesizing work.eclksynca.syn_black_box 
Post processing for work.eclksynca.syn_black_box
@N:CD630 : machxo2.vhd(1488) | Synthesizing work.vlo.syn_black_box 
Post processing for work.vlo.syn_black_box
@N:CD630 : machxo2.vhd(1481) | Synthesizing work.vhi.syn_black_box 
Post processing for work.vhi.syn_black_box
Post processing for work.tx_lvds_71.structure
@N:CD630 : tft_timing_ctrl.vhd(75) | Synthesizing work.tft_timing_ctrl.rtl_tft_timing_ctrl 
@N:CD233 : tft_timing_ctrl.vhd(158) | Using sequential encoding for type vsync_state
@N:CD233 : tft_timing_ctrl.vhd(163) | Using sequential encoding for type vsync_to_hsync_state
@N:CD233 : tft_timing_ctrl.vhd(168) | Using sequential encoding for type hsync_state
@N:CD233 : tft_timing_ctrl.vhd(173) | Using sequential encoding for type hdata_state
@W:CD604 : tft_timing_ctrl.vhd(312) | OTHERS clause is not synthesized 
@W:CD604 : tft_timing_ctrl.vhd(341) | OTHERS clause is not synthesized 
@W:CD604 : tft_timing_ctrl.vhd(370) | OTHERS clause is not synthesized 
@W:CD604 : tft_timing_ctrl.vhd(401) | OTHERS clause is not synthesized 
@W:CD604 : tft_timing_ctrl.vhd(429) | OTHERS clause is not synthesized 
Post processing for work.tft_timing_ctrl.rtl_tft_timing_ctrl
@W:CL169 : tft_timing_ctrl.vhd(550) | Pruning Register tft_test_reg1  
@W:CL169 : tft_timing_ctrl.vhd(550) | Pruning Register tft_test_reg0  
@W:CL169 : tft_timing_ctrl.vhd(447) | Pruning Register row_cnt(9 downto 0)  
@W:CL169 : tft_timing_ctrl.vhd(447) | Pruning Register column_cnt(9 downto 0)  
@W:CL169 : tft_timing_ctrl.vhd(386) | Pruning Register debug_hsync_reg  
@W:CL169 : tft_timing_ctrl.vhd(386) | Pruning Register debug_hsync_st(hsync_st0)  
@W:CL265 : tft_timing_ctrl.vhd(717) | Pruning bit 15 of hdata_final_sr(15 downto 0) - not in use ... 
@W:CL265 : tft_timing_ctrl.vhd(717) | Pruning bit 14 of hdata_final_sr(15 downto 0) - not in use ... 
@W:CL265 : tft_timing_ctrl.vhd(717) | Pruning bit 13 of hdata_final_sr(15 downto 0) - not in use ... 
@W:CL265 : tft_timing_ctrl.vhd(717) | Pruning bit 12 of hdata_final_sr(15 downto 0) - not in use ... 
@W:CL265 : tft_timing_ctrl.vhd(717) | Pruning bit 11 of hdata_final_sr(15 downto 0) - not in use ... 
@W:CL265 : tft_timing_ctrl.vhd(717) | Pruning bit 15 of hsync_final_sr(15 downto 0) - not in use ... 
@W:CL265 : tft_timing_ctrl.vhd(717) | Pruning bit 14 of hsync_final_sr(15 downto 0) - not in use ... 
@W:CL265 : tft_timing_ctrl.vhd(717) | Pruning bit 13 of hsync_final_sr(15 downto 0) - not in use ... 
@W:CL265 : tft_timing_ctrl.vhd(717) | Pruning bit 12 of hsync_final_sr(15 downto 0) - not in use ... 
@W:CL265 : tft_timing_ctrl.vhd(717) | Pruning bit 11 of hsync_final_sr(15 downto 0) - not in use ... 
@W:CL265 : tft_timing_ctrl.vhd(717) | Pruning bit 15 of vsync_final_sr(15 downto 0) - not in use ... 
@W:CL265 : tft_timing_ctrl.vhd(717) | Pruning bit 14 of vsync_final_sr(15 downto 0) - not in use ... 
@W:CL265 : tft_timing_ctrl.vhd(717) | Pruning bit 13 of vsync_final_sr(15 downto 0) - not in use ... 
@W:CL265 : tft_timing_ctrl.vhd(717) | Pruning bit 12 of vsync_final_sr(15 downto 0) - not in use ... 
@W:CL265 : tft_timing_ctrl.vhd(717) | Pruning bit 11 of vsync_final_sr(15 downto 0) - not in use ... 
@W:CL265 : tft_timing_ctrl.vhd(570) | Pruning bit 2 of tft_sect_reg(2 downto 0) - not in use ... 
@W:CL265 : tft_timing_ctrl.vhd(570) | Pruning bit 1 of tft_sect_reg(2 downto 0) - not in use ... 
@W:CL265 : tft_timing_ctrl.vhd(523) | Pruning bit 2 of tft_pixel_reg(18 downto 0) - not in use ... 
@W:CL265 : tft_timing_ctrl.vhd(523) | Pruning bit 1 of tft_pixel_reg(18 downto 0) - not in use ... 
@W:CL265 : tft_timing_ctrl.vhd(523) | Pruning bit 0 of tft_pixel_reg(18 downto 0) - not in use ... 
@N:CD630 : tft_pixel_rgb_pipeliner.vhd(44) | Synthesizing work.tft_pixel_rgb_pipeliner.rtl_tft_pixel_rgb_pipeliner 
@N:CD233 : tft_pixel_rgb_pipeliner.vhd(82) | Using sequential encoding for type read_enable_state
@W:CD604 : tft_pixel_rgb_pipeliner.vhd(125) | OTHERS clause is not synthesized 
@N:CD630 : pixel_rgb_fifo.vhd(14) | Synthesizing work.pixel_rgb_fifo.structure 
@N:CD630 : machxo2.vhd(364) | Synthesizing work.fd1s3dx.syn_black_box 
Post processing for work.fd1s3dx.syn_black_box
@N:CD630 : machxo2.vhd(353) | Synthesizing work.fd1s3bx.syn_black_box 
Post processing for work.fd1s3bx.syn_black_box
@N:CD630 : machxo2.vhd(1662) | Synthesizing work.dpr16x4c.syn_black_box 
Post processing for work.dpr16x4c.syn_black_box
@N:CD630 : machxo2.vhd(176) | Synthesizing work.fadd2b.syn_black_box 
Post processing for work.fadd2b.syn_black_box
@N:CD630 : machxo2.vhd(33) | Synthesizing work.ageb2.syn_black_box 
Post processing for work.ageb2.syn_black_box
@N:CD630 : machxo2.vhd(166) | Synthesizing work.cu2.syn_black_box 
Post processing for work.cu2.syn_black_box
@N:CD630 : machxo2.vhd(1495) | Synthesizing work.xor2.syn_black_box 
Post processing for work.xor2.syn_black_box
@N:CD630 : machxo2.vhd(1275) | Synthesizing work.or2.syn_black_box 
Post processing for work.or2.syn_black_box
@N:CD630 : machxo2.vhd(680) | Synthesizing work.inv.syn_black_box 
Post processing for work.inv.syn_black_box
@N:CD630 : machxo2.vhd(63) | Synthesizing work.and2.syn_black_box 
Post processing for work.and2.syn_black_box
Post processing for work.pixel_rgb_fifo.structure
Post processing for work.tft_pixel_rgb_pipeliner.rtl_tft_pixel_rgb_pipeliner
@N:CD630 : sdram_ctrl.vhd(24) | Synthesizing work.sdram_ctrl.rtl_sdram_ctrl 
@N:CD232 : sdram_ctrl.vhd(64) | Using gray code encoding for type sdram_fsm_state
@W:CD604 : sdram_ctrl.vhd(507) | OTHERS clause is not synthesized 
Post processing for work.sdram_ctrl.rtl_sdram_ctrl
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 19 of sys_addr_reg2(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 18 of sys_addr_reg2(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 17 of sys_addr_reg2(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 16 of sys_addr_reg2(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 15 of sys_addr_reg2(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 14 of sys_addr_reg2(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 13 of sys_addr_reg2(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 12 of sys_addr_reg2(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 11 of sys_addr_reg2(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 10 of sys_addr_reg2(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 9 of sys_addr_reg2(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 8 of sys_addr_reg2(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 19 of sys_addr_reg1(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 18 of sys_addr_reg1(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 17 of sys_addr_reg1(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 16 of sys_addr_reg1(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 15 of sys_addr_reg1(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 14 of sys_addr_reg1(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 13 of sys_addr_reg1(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 12 of sys_addr_reg1(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 11 of sys_addr_reg1(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 10 of sys_addr_reg1(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 9 of sys_addr_reg1(21 downto 0) - not in use ... 
@W:CL265 : sdram_ctrl.vhd(151) | Pruning bit 8 of sys_addr_reg1(21 downto 0) - not in use ... 
@N:CD630 : monster_manager.vhd(48) | Synthesizing work.monster_manager.rtl_monster_manager 
@N:CD231 : monster_manager.vhd(96) | Using onehot encoding for type fsm_state (idle="1000000000000000000000000000000")
@W:CD604 : monster_manager.vhd(388) | OTHERS clause is not synthesized 
@W:CD638 : monster_manager.vhd(111) | Signal tft_sdram_addr_reg is undriven 
@W:CD638 : monster_manager.vhd(117) | Signal dummy_reg is undriven 
@W:CD638 : monster_manager.vhd(118) | Signal red_reg is undriven 
@W:CD638 : monster_manager.vhd(119) | Signal green_reg is undriven 
@W:CD638 : monster_manager.vhd(120) | Signal blue_reg is undriven 
@W:CD638 : monster_manager.vhd(124) | Signal sys_data_val_reg1 is undriven 
@W:CD638 : monster_manager.vhd(125) | Signal sys_data_val_reg2 is undriven 
@W:CD638 : monster_manager.vhd(127) | Signal tft_red_reg is undriven 
@W:CD638 : monster_manager.vhd(128) | Signal tft_green_reg is undriven 
@W:CD638 : monster_manager.vhd(129) | Signal tft_blue_reg is undriven 
Post processing for work.monster_manager.rtl_monster_manager
@W:CL111 : monster_manager.vhd(186) | All reachable assignments to sys_be(0) assign '0', register removed by optimization
@W:CL111 : monster_manager.vhd(186) | All reachable assignments to sys_be(1) assign '0', register removed by optimization
@N:CD630 : pixel_addr_data_fifo.vhd(44) | Synthesizing work.pixel_addr_data_fifo.rtl_pixel_addr_data_fifo 
@N:CD630 : pixel_data_fifo.vhd(14) | Synthesizing work.pixel_data_fifo.structure 
@N:CD630 : machxo2.vhd(579) | Synthesizing work.fsub2b.syn_black_box 
Post processing for work.fsub2b.syn_black_box
Post processing for work.pixel_data_fifo.structure
@W:CL168 : pixel_data_fifo.vhd(856) | Pruning instance rfilld - not in use ... 
@N:CD630 : pixel_addr_fifo.vhd(14) | Synthesizing work.pixel_addr_fifo.structure 
Post processing for work.pixel_addr_fifo.structure
Post processing for work.pixel_addr_data_fifo.rtl_pixel_addr_data_fifo
@N:CD630 : sdram_test_generator.vhd(48) | Synthesizing work.sdram_test_generator.rtl_sdram_test_generator 
@N:CD233 : sdram_test_generator.vhd(69) | Using sequential encoding for type fsm_state
@W:CD604 : sdram_test_generator.vhd(123) | OTHERS clause is not synthesized 
Post processing for work.sdram_test_generator.rtl_sdram_test_generator
@W:CL265 : sdram_test_generator.vhd(137) | Pruning bit 2 of scaler_cnt(2 downto 0) - not in use ... 
@W:CL265 : sdram_test_generator.vhd(137) | Pruning bit 1 of scaler_cnt(2 downto 0) - not in use ... 
@N:CD630 : power_manager.vhd(52) | Synthesizing work.power_manager.rtl_power_manager 
@N:CD231 : power_manager.vhd(104) | Using onehot encoding for type delay_fsm_state (idle="1000000")
@N:CD231 : power_manager.vhd(114) | Using onehot encoding for type tft_on_off_state (idle="100000000")
@W:CD604 : power_manager.vhd(196) | OTHERS clause is not synthesized 
@W:CD604 : power_manager.vhd(414) | OTHERS clause is not synthesized 
Post processing for work.power_manager.rtl_power_manager
@N:CD630 : tft_on_off_button_ctrl.vhd(45) | Synthesizing work.tft_on_off_button_ctrl.rtl_tft_on_off_button_ctrl 
@N:CD233 : tft_on_off_button_ctrl.vhd(67) | Using sequential encoding for type button_state
@W:CD604 : tft_on_off_button_ctrl.vhd(149) | OTHERS clause is not synthesized 
Post processing for work.tft_on_off_button_ctrl.rtl_tft_on_off_button_ctrl
@N:CD630 : pll_block.vhd(14) | Synthesizing work.pll_block.structure 
@N:CD630 : machxo2.vhd(2219) | Synthesizing work.ehxpllj.syn_black_box 
Post processing for work.ehxpllj.syn_black_box
Post processing for work.pll_block.structure
Post processing for work.tftsurfer_top.rtl_tftsurfer_top
@W:CL252 : tftsurfer_top.vhd(405) | Bit 0 of signal tft_sect_sig is floating - a simulation mismatch is possible
@W:CL252 : tftsurfer_top.vhd(405) | Bit 1 of signal tft_sect_sig is floating - a simulation mismatch is possible
@W:CL252 : tftsurfer_top.vhd(405) | Bit 2 of signal tft_sect_sig is floating - a simulation mismatch is possible
@W:CL252 : tftsurfer_top.vhd(404) | Bit 0 of signal tft_bank_sig is floating - a simulation mismatch is possible
@W:CL252 : tftsurfer_top.vhd(404) | Bit 1 of signal tft_bank_sig is floating - a simulation mismatch is possible
@W:CL240 : tftsurfer_top.vhd(59) | test_pt5 is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : tftsurfer_top.vhd(58) | test_pt4 is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : tftsurfer_top.vhd(57) | test_pt3 is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : tftsurfer_top.vhd(56) | test_pt2 is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL240 : tftsurfer_top.vhd(55) | test_pt1 is not assigned a value (floating) - a simulation mismatch is possible 
@W:CL245 : tftsurfer_top.vhd(639) | Bit 0 of input tft_bank of instance TFT_TIMING_CTRL_INST is floating
@W:CL245 : tftsurfer_top.vhd(639) | Bit 1 of input tft_bank of instance TFT_TIMING_CTRL_INST is floating
@W:CL245 : tftsurfer_top.vhd(639) | Bit 0 of input tft_sect of instance TFT_TIMING_CTRL_INST is floating
@W:CL245 : tftsurfer_top.vhd(639) | Bit 1 of input tft_sect of instance TFT_TIMING_CTRL_INST is floating
@W:CL245 : tftsurfer_top.vhd(639) | Bit 2 of input tft_sect of instance TFT_TIMING_CTRL_INST is floating
@N:CL201 : tft_on_off_button_ctrl.vhd(125) | Trying to extract state machine for register button_st
Extracted state machine for register button_st
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@N:CL201 : power_manager.vhd(337) | Trying to extract state machine for register tft_on_off_st
Extracted state machine for register tft_on_off_st
State machine has 9 reachable states with original encodings of:
   000000001
   000000010
   000000100
   000001000
   000010000
   000100000
   001000000
   010000000
   100000000
@N:CL201 : power_manager.vhd(156) | Trying to extract state machine for register delay_st
Extracted state machine for register delay_st
State machine has 7 reachable states with original encodings of:
   0000001
   0000010
   0000100
   0001000
   0010000
   0100000
   1000000
@W:CL260 : sdram_test_generator.vhd(198) | Pruning Register bit 15 of sdram_fifo_wr_rgb(15 downto 0)  
@W:CL260 : sdram_test_generator.vhd(198) | Pruning Register bit 14 of sdram_fifo_wr_rgb(15 downto 0)  
@W:CL260 : sdram_test_generator.vhd(198) | Pruning Register bit 13 of sdram_fifo_wr_rgb(15 downto 0)  
@W:CL260 : sdram_test_generator.vhd(198) | Pruning Register bit 12 of sdram_fifo_wr_rgb(15 downto 0)  
@W:CL260 : sdram_test_generator.vhd(198) | Pruning Register bit 10 of sdram_fifo_wr_rgb(15 downto 0)  
@W:CL260 : sdram_test_generator.vhd(198) | Pruning Register bit 9 of sdram_fifo_wr_rgb(15 downto 0)  
@W:CL260 : sdram_test_generator.vhd(198) | Pruning Register bit 8 of sdram_fifo_wr_rgb(15 downto 0)  
@W:CL260 : sdram_test_generator.vhd(198) | Pruning Register bit 7 of sdram_fifo_wr_rgb(15 downto 0)  
@W:CL260 : sdram_test_generator.vhd(198) | Pruning Register bit 6 of sdram_fifo_wr_rgb(15 downto 0)  
@W:CL260 : sdram_test_generator.vhd(198) | Pruning Register bit 4 of sdram_fifo_wr_rgb(15 downto 0)  
@W:CL260 : sdram_test_generator.vhd(198) | Pruning Register bit 3 of sdram_fifo_wr_rgb(15 downto 0)  
@W:CL260 : sdram_test_generator.vhd(198) | Pruning Register bit 2 of sdram_fifo_wr_rgb(15 downto 0)  
@W:CL260 : sdram_test_generator.vhd(198) | Pruning Register bit 1 of sdram_fifo_wr_rgb(15 downto 0)  
@N:CL201 : sdram_test_generator.vhd(105) | Trying to extract state machine for register fsm_st
Extracted state machine for register fsm_st
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@N:CL201 : monster_manager.vhd(186) | Trying to extract state machine for register fsm_st
Extracted state machine for register fsm_st
State machine has 31 reachable states with original encodings of:
   0000000000000000000000000000001
   0000000000000000000000000000010
   0000000000000000000000000000100
   0000000000000000000000000001000
   0000000000000000000000000010000
   0000000000000000000000000100000
   0000000000000000000000001000000
   0000000000000000000000010000000
   0000000000000000000000100000000
   0000000000000000000001000000000
   0000000000000000000010000000000
   0000000000000000000100000000000
   0000000000000000001000000000000
   0000000000000000010000000000000
   0000000000000000100000000000000
   0000000000000001000000000000000
   0000000000000010000000000000000
   0000000000000100000000000000000
   0000000000001000000000000000000
   0000000000010000000000000000000
   0000000000100000000000000000000
   0000000001000000000000000000000
   0000000010000000000000000000000
   0000000100000000000000000000000
   0000001000000000000000000000000
   0000010000000000000000000000000
   0000100000000000000000000000000
   0001000000000000000000000000000
   0010000000000000000000000000000
   0100000000000000000000000000000
   1000000000000000000000000000000
@W:CL159 : monster_manager.vhd(72) | Input sys_cycle_end is unused
@W:CL159 : monster_manager.vhd(75) | Input sys_ref_ack is unused
@N:CL135 : sdram_ctrl.vhd(151) | Found seqShift sys_be_reg2, depth=3, width=2
@N:CL177 : sdram_ctrl.vhd(185) | Sharing sequential element sdram_cke_reg.
@N:CL201 : sdram_ctrl.vhd(185) | Trying to extract state machine for register sdram_fsm_st
Extracted state machine for register sdram_fsm_st
State machine has 49 reachable states with original encodings of:
   000000
   000001
   000010
   000011
   000100
   000101
   000110
   000111
   001000
   001001
   001010
   001011
   001100
   001101
   001110
   001111
   010000
   010001
   010010
   010011
   010100
   010101
   010110
   010111
   011000
   011001
   011010
   011011
   011100
   011101
   011110
   011111
   101000
   110000
   110001
   110010
   110011
   110100
   110101
   110110
   110111
   111000
   111001
   111010
   111011
   111100
   111101
   111110
   111111
@W:CL260 : tft_timing_ctrl.vhd(658) | Pruning Register bit 2 of tft_test_red(7 downto 0)  
@W:CL260 : tft_timing_ctrl.vhd(658) | Pruning Register bit 1 of tft_test_red(7 downto 0)  
@W:CL260 : tft_timing_ctrl.vhd(658) | Pruning Register bit 1 of tft_test_green(7 downto 0)  
@W:CL260 : tft_timing_ctrl.vhd(658) | Pruning Register bit 2 of tft_test_blue(7 downto 0)  
@W:CL260 : tft_timing_ctrl.vhd(658) | Pruning Register bit 1 of tft_test_blue(7 downto 0)  
@W:CL169 : tft_timing_ctrl.vhd(658) | Pruning Register tft_test_green(0)  
@W:CL169 : tft_timing_ctrl.vhd(658) | Pruning Register tft_test_red(0)  
@W:CL246 : tft_timing_ctrl.vhd(85) | Input port bits 2 to 1 of tft_sect(2 downto 0) are unused 
@W:CL159 : tft_timing_ctrl.vhd(83) | Input tft_test is unused
@W:CL159 : tft_timing_ctrl.vhd(87) | Input tft_sig_en is unused
@W:CL159 : tft_timing_ctrl.vhd(88) | Input tft_rgb_en is unused
@END
Process took 0h:00m:01s realtime, 0h:00m:01s cputime
# Sun Sep 18 00:45:37 2011

###########################################################]

Synopsys Lattice Technology Constraint Extraction, Version maplat, Build 064R, Built Feb 17 2011 10:52:05 Copyright (C) 1994-2011, Synopsys Inc. All Rights Reserved Product Version E-2010.09L-SP2 @N:MF249 : | Running in 32-bit mode. @N:MF257 : | Gated clock conversion enabled @W:BN132 : power_manager.vhd(337) | Removing sequential instance tft_disp_en, because it is equivalent to instance tft_led_en @W:BN132 : power_manager.vhd(337) | Removing sequential instance tft_sig_en, because it is equivalent to instance tft_rgb_en Finished Timing Extraction Phase. (Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 79MB) Timing Extraction successful! Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Sun Sep 18 00:45:37 2011 ###########################################################] Synopsys Lattice Technology Mapper, Version maplat, Build 064R, Built Feb 17 2011 10:52:05 Copyright (C) 1994-2011, Synopsys Inc. All Rights Reserved Product Version E-2010.09L-SP2 @N:MF249 : | Running in 32-bit mode. @N:MF257 : | Gated clock conversion enabled @N:BN116 : tft_timing_ctrl.vhd(550) | Removing sequential instance sdram_test_reg1 of view:PrimLib.dffre(prim) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(550) | Removing sequential instance sdram_test_reg0 of view:PrimLib.dffre(prim) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(537) | Removing sequential instance v_tick_reg_sr[3:0] of view:PrimLib.dffr(prim) because there are no references to its outputs Available hyper_sources - for debug and ip models None Found @N:MT206 : | Autoconstrain Mode is ON Finished RTL optimizations (Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 79MB) Encoding state machine work.tft_on_off_button_ctrl(rtl_tft_on_off_button_ctrl)-button_st[0:2] original code -> new code 00 -> 00 01 -> 01 10 -> 10 Encoding state machine work.power_manager(rtl_power_manager)-delay_st[0:6] original code -> new code 0000001 -> 0000001 0000010 -> 0000010 0000100 -> 0000100 0001000 -> 0001000 0010000 -> 0010000 0100000 -> 0100000 1000000 -> 1000000 Encoding state machine work.power_manager(rtl_power_manager)-tft_on_off_st[0:8] original code -> new code 000000001 -> 000000001 000000010 -> 000000010 000000100 -> 000000100 000001000 -> 000001000 000010000 -> 000010000 000100000 -> 000100000 001000000 -> 001000000 010000000 -> 010000000 100000000 -> 100000000 @N: : power_manager.vhd(209) | Found counter in view:work.power_manager(rtl_power_manager) inst timer_cnt[14:0] @N: : power_manager.vhd(284) | Found counter in view:work.power_manager(rtl_power_manager) inst frame_cnt[3:0] Encoding state machine work.sdram_test_generator(rtl_sdram_test_generator)-fsm_st[0:3] original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 Encoding state machine work.monster_manager(rtl_monster_manager)-fsm_st[0:30] original code -> new code 0000000000000000000000000000001 -> 00000 0000000000000000000000000000010 -> 00001 0000000000000000000000000000100 -> 00010 0000000000000000000000000001000 -> 00011 0000000000000000000000000010000 -> 00100 0000000000000000000000000100000 -> 00101 0000000000000000000000001000000 -> 00110 0000000000000000000000010000000 -> 00111 0000000000000000000000100000000 -> 01000 0000000000000000000001000000000 -> 01001 0000000000000000000010000000000 -> 01010 0000000000000000000100000000000 -> 01011 0000000000000000001000000000000 -> 01100 0000000000000000010000000000000 -> 01101 0000000000000000100000000000000 -> 01110 0000000000000001000000000000000 -> 01111 0000000000000010000000000000000 -> 10000 0000000000000100000000000000000 -> 10001 0000000000001000000000000000000 -> 10010 0000000000010000000000000000000 -> 10011 0000000000100000000000000000000 -> 10100 0000000001000000000000000000000 -> 10101 0000000010000000000000000000000 -> 10110 0000000100000000000000000000000 -> 10111 0000001000000000000000000000000 -> 11000 0000010000000000000000000000000 -> 11001 0000100000000000000000000000000 -> 11010 0001000000000000000000000000000 -> 11011 0010000000000000000000000000000 -> 11100 0100000000000000000000000000000 -> 11101 1000000000000000000000000000000 -> 11110 Encoding state machine work.sdram_ctrl(rtl_sdram_ctrl)-sdram_fsm_st[0:48] original code -> new code 000000 -> 000000 000001 -> 000001 000010 -> 000011 000011 -> 000010 000100 -> 000110 000101 -> 000111 000110 -> 000101 000111 -> 000100 001000 -> 001100 001001 -> 001101 001010 -> 001111 001011 -> 001110 001100 -> 001010 001101 -> 001011 001110 -> 001001 001111 -> 001000 010000 -> 011000 010001 -> 011001 010010 -> 011011 010011 -> 011010 010100 -> 011110 010101 -> 011111 010110 -> 011101 010111 -> 011100 011000 -> 010100 011001 -> 010101 011010 -> 010111 011011 -> 010110 011100 -> 010010 011101 -> 010011 011110 -> 010001 011111 -> 010000 101000 -> 110000 110000 -> 110001 110001 -> 110011 110010 -> 110010 110011 -> 110110 110100 -> 110111 110101 -> 110101 110110 -> 110100 110111 -> 111100 111000 -> 111101 111001 -> 111111 111010 -> 111110 111011 -> 111010 111100 -> 111011 111101 -> 111001 111110 -> 111000 111111 -> 101000 @W:BN132 : tft_on_off_button_ctrl.vhd(125) | Removing instance TFT_ON_OFF_BUTTON_CTRL_INST.tft_off, because it is equivalent to instance TFT_ON_OFF_BUTTON_CTRL_INST.button_st[1] @N:BN116 : sdram_ctrl.vhd(185) | Removing sequential instance SDRAM_CTRL_INST.cycle_end_reg of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : sdram_ctrl.vhd(185) | Removing sequential instance SDRAM_CTRL_INST.ref_ack_reg of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(354) | Removing sequential instance TFT_TIMING_CTRL_INST.hsync_st[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.vsync_final_sr[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.vsync_final_sr[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.hsync_final_sr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.hsync_final_sr[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.hsync_final_sr[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.hsync_final_sr[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.hsync_final_sr[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.hsync_final_sr[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.hsync_final_sr[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.hsync_final_sr[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.hsync_final_sr[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.hsync_final_sr[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.hsync_final_sr[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.vsync_final_sr[10] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.vsync_final_sr[9] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.vsync_final_sr[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.vsync_final_sr[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.vsync_final_sr[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.vsync_final_sr[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.vsync_final_sr[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.vsync_final_sr[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(717) | Removing sequential instance TFT_TIMING_CTRL_INST.vsync_final_sr[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(354) | Removing sequential instance TFT_TIMING_CTRL_INST.hsync_reg of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(296) | Removing sequential instance TFT_TIMING_CTRL_INST.vsync_reg of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_timing_ctrl.vhd(296) | Removing sequential instance TFT_TIMING_CTRL_INST.vsync_st[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : pixel_data_fifo.vhd(783) | Removing sequential instance PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.FF_6 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs @N:BN116 : pixel_data_fifo.vhd(786) | Removing sequential instance PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.FF_5 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs @N:BN116 : pixel_data_fifo.vhd(789) | Removing sequential instance PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.FF_4 of view:LUCENT.FD1S3DX(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(321) | Removing sequential instance POWER_MANAGER_INST.frame_cnt_7_reg of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(321) | Removing sequential instance POWER_MANAGER_INST.frame_cnt_3_reg of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(321) | Removing sequential instance POWER_MANAGER_INST.frame_cnt_15_reg of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(264) | Removing sequential instance POWER_MANAGER_INST.tft_on_reg2 of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(264) | Removing sequential instance POWER_MANAGER_INST.tft_off_reg2 of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(264) | Removing sequential instance POWER_MANAGER_INST.tft_on_reg1 of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @A:BN291 : power_manager.vhd(264) | Boundary register POWER_MANAGER_INST.tft_on_reg1 has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : power_manager.vhd(264) | Removing sequential instance POWER_MANAGER_INST.tft_off_reg1 of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @A:BN291 : power_manager.vhd(264) | Boundary register POWER_MANAGER_INST.tft_off_reg1 has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : power_manager.vhd(406) | Removing sequential instance POWER_MANAGER_INST.tft_on_off_st[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(399) | Removing sequential instance POWER_MANAGER_INST.tft_on_off_st[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(395) | Removing sequential instance POWER_MANAGER_INST.tft_on_off_st[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(387) | Removing sequential instance POWER_MANAGER_INST.tft_on_off_st[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(379) | Removing sequential instance POWER_MANAGER_INST.tft_on_off_st[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(371) | Removing sequential instance POWER_MANAGER_INST.tft_on_off_st[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(363) | Removing sequential instance POWER_MANAGER_INST.tft_on_off_st[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(359) | Removing sequential instance POWER_MANAGER_INST.tft_on_off_st[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(347) | Removing sequential instance POWER_MANAGER_INST.tft_on_off_st[8] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(284) | Removing sequential instance POWER_MANAGER_INST.frame_cnt[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(284) | Removing sequential instance POWER_MANAGER_INST.frame_cnt[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(284) | Removing sequential instance POWER_MANAGER_INST.frame_cnt[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(284) | Removing sequential instance POWER_MANAGER_INST.frame_cnt[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(337) | Removing sequential instance POWER_MANAGER_INST.tft_avdd_en of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(337) | Removing sequential instance POWER_MANAGER_INST.tft_vdd_en of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(337) | Removing sequential instance POWER_MANAGER_INST.tft_led_en of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : power_manager.vhd(337) | Removing sequential instance POWER_MANAGER_INST.tft_rgb_en of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_on_off_button_ctrl.vhd(95) | Removing sequential instance TFT_ON_OFF_BUTTON_CTRL_INST.button_imp_reg0 of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_on_off_button_ctrl.vhd(113) | Removing sequential instance TFT_ON_OFF_BUTTON_CTRL_INST.button_pre_reg of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_on_off_button_ctrl.vhd(125) | Removing sequential instance TFT_ON_OFF_BUTTON_CTRL_INST.tft_on of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @A:BN291 : tft_on_off_button_ctrl.vhd(125) | Boundary register TFT_ON_OFF_BUTTON_CTRL_INST.tft_on has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @N:BN116 : tft_on_off_button_ctrl.vhd(95) | Removing sequential instance TFT_ON_OFF_BUTTON_CTRL_INST.button_imp_reg1 of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_on_off_button_ctrl.vhd(78) | Removing sequential instance TFT_ON_OFF_BUTTON_CTRL_INST.button_reg[2] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_on_off_button_ctrl.vhd(78) | Removing sequential instance TFT_ON_OFF_BUTTON_CTRL_INST.button_reg[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_on_off_button_ctrl.vhd(78) | Removing sequential instance TFT_ON_OFF_BUTTON_CTRL_INST.button_reg[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_on_off_button_ctrl.vhd(125) | Removing sequential instance TFT_ON_OFF_BUTTON_CTRL_INST.button_st[1] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_on_off_button_ctrl.vhd(125) | Removing sequential instance TFT_ON_OFF_BUTTON_CTRL_INST.button_st[0] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_on_off_button_ctrl.vhd(78) | Removing sequential instance TFT_ON_OFF_BUTTON_CTRL_INST.button_reg[7] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_on_off_button_ctrl.vhd(78) | Removing sequential instance TFT_ON_OFF_BUTTON_CTRL_INST.button_reg[6] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_on_off_button_ctrl.vhd(78) | Removing sequential instance TFT_ON_OFF_BUTTON_CTRL_INST.button_reg[5] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_on_off_button_ctrl.vhd(78) | Removing sequential instance TFT_ON_OFF_BUTTON_CTRL_INST.button_reg[4] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_on_off_button_ctrl.vhd(78) | Removing sequential instance TFT_ON_OFF_BUTTON_CTRL_INST.button_reg[3] of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs @N:BN116 : tft_on_off_button_ctrl.vhd(125) | Removing sequential instance TFT_ON_OFF_BUTTON_CTRL_INST.test_button of view:UNILIB.FDCPE(PRIM) because there are no references to its outputs Finished factoring (Time elapsed 0h:00m:00s; Memory used current: 80MB peak: 81MB) #################### START OF GENERATED CLOCK OPTIMIZATION REPORT ####################[ ====================================================================================== Instance:Pin Generated Clock Optimization Status ====================================================================================== TFT_PIXEL_RGB_PIPELINER_INST.read_enable_st[0]:C Not Done SDRAM_CTRL_INST.sys_r_wn_reg2:C Not Done POWER_MANAGER_INST.timer_cnt_100us_reg:C Not Done ##################### END OF GENERATED CLOCK OPTIMIZATION REPORT #####################] Finished gated-clock and generated-clock conversion (Time elapsed 0h:00m:00s; Memory used current: 80MB peak: 81MB) Finished generic timing optimizations - Pass 1 (Time elapsed 0h:00m:00s; Memory used current: 80MB peak: 81MB) Starting Early Timing Optimization (Time elapsed 0h:00m:00s; Memory used current: 80MB peak: 81MB) Finished Early Timing Optimization (Time elapsed 0h:00m:01s; Memory used current: 80MB peak: 81MB) Finished generic timing optimizations - Pass 2 (Time elapsed 0h:00m:01s; Memory used current: 80MB peak: 81MB) Finished preparing to map (Time elapsed 0h:00m:01s; Memory used current: 80MB peak: 81MB) Finished technology mapping (Time elapsed 0h:00m:01s; Memory used current: 87MB peak: 88MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:02s -2.47ns 292 / 485 2 0h:00m:02s -2.47ns 288 / 485 ------------------------------------------------------------ @N:FX271 : sdram_ctrl.vhd(185) | Instance "SDRAM_CTRL_INST.sdram_fsm_st[4]" with 36 loads has been replicated 3 time(s) to improve timing @N:FX271 : sdram_ctrl.vhd(185) | Instance "SDRAM_CTRL_INST.sdram_fsm_st[5]" with 29 loads has been replicated 2 time(s) to improve timing Timing driven replication report Added 5 Registers via timing driven replication Added 5 LUTs via timing driven replication @N:FX271 : sdram_test_generator.vhd(137) | Instance "SDRAM_TEST_GENERATOR_INST.scaler_cnt[0]" with 39 loads has been replicated 1 time(s) to improve timing Added 1 Registers via timing driven replication Added 1 LUTs via timing driven replication Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:03s -1.94ns 298 / 473 2 0h:00m:03s -1.94ns 298 / 473 3 0h:00m:03s -1.94ns 298 / 473 4 0h:00m:03s -1.94ns 298 / 473 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:03s -1.94ns 298 / 473 2 0h:00m:03s -1.94ns 298 / 473 3 0h:00m:03s -1.94ns 298 / 473 4 0h:00m:03s -1.94ns 298 / 473 ------------------------------------------------------------ Finished technology timing optimizations and critical path resynthesis (Time elapsed 0h:00m:03s; Memory used current: 87MB peak: 88MB) @N:FX164 : | The option to pack flops in the IOB has not been specified @A:BN291 : power_manager.vhd(156) | Boundary register POWER_MANAGER_INST.delay_100_us.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(523) | Boundary register TFT_TIMING_CTRL_INST.tft_pixel_reg_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(523) | Boundary register TFT_TIMING_CTRL_INST.tft_pixel_reg_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(523) | Boundary register TFT_TIMING_CTRL_INST.tft_pixel_reg_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(523) | Boundary register TFT_TIMING_CTRL_INST.tft_pixel_reg_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(523) | Boundary register TFT_TIMING_CTRL_INST.tft_pixel_reg_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(523) | Boundary register TFT_TIMING_CTRL_INST.tft_pixel_reg_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(523) | Boundary register TFT_TIMING_CTRL_INST.tft_pixel_reg_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(523) | Boundary register TFT_TIMING_CTRL_INST.tft_pixel_reg_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(523) | Boundary register TFT_TIMING_CTRL_INST.tft_pixel_reg_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(523) | Boundary register TFT_TIMING_CTRL_INST.tft_pixel_reg_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(523) | Boundary register TFT_TIMING_CTRL_INST.tft_pixel_reg_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(523) | Boundary register TFT_TIMING_CTRL_INST.tft_pixel_reg_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(523) | Boundary register TFT_TIMING_CTRL_INST.tft_pixel_reg_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(523) | Boundary register TFT_TIMING_CTRL_INST.tft_pixel_reg_16_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(523) | Boundary register TFT_TIMING_CTRL_INST.tft_pixel_reg_17_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(523) | Boundary register TFT_TIMING_CTRL_INST.tft_pixel_reg_18_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(447) | Boundary register TFT_TIMING_CTRL_INST.pixel_cnt_9_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(447) | Boundary register TFT_TIMING_CTRL_INST.pixel_cnt_10_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(447) | Boundary register TFT_TIMING_CTRL_INST.pixel_cnt_11_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(447) | Boundary register TFT_TIMING_CTRL_INST.pixel_cnt_12_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(447) | Boundary register TFT_TIMING_CTRL_INST.pixel_cnt_13_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(447) | Boundary register TFT_TIMING_CTRL_INST.pixel_cnt_14_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(447) | Boundary register TFT_TIMING_CTRL_INST.pixel_cnt_15_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(447) | Boundary register TFT_TIMING_CTRL_INST.pixel_cnt_16_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(447) | Boundary register TFT_TIMING_CTRL_INST.pixel_cnt_17_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(447) | Boundary register TFT_TIMING_CTRL_INST.pixel_cnt_18_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(447) | Boundary register TFT_TIMING_CTRL_INST.pixel_cnt_1_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(447) | Boundary register TFT_TIMING_CTRL_INST.pixel_cnt_2_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(447) | Boundary register TFT_TIMING_CTRL_INST.pixel_cnt_3_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(447) | Boundary register TFT_TIMING_CTRL_INST.pixel_cnt_4_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(447) | Boundary register TFT_TIMING_CTRL_INST.pixel_cnt_5_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(447) | Boundary register TFT_TIMING_CTRL_INST.pixel_cnt_6_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(447) | Boundary register TFT_TIMING_CTRL_INST.pixel_cnt_7_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. @A:BN291 : tft_timing_ctrl.vhd(447) | Boundary register TFT_TIMING_CTRL_INST.pixel_cnt_8_.fb has been packed into a complex cell. To disable this register packing, set syn_keep=1 on the net between the register and the complex cell. --------------------------------------- Resource Usage Report Part: lcmxo2_1200hc-6 Register bits: 761 of 1280 (59%) PIC Latch: 0 I/O cells: 55 Details: AND2: 6 BB: 16 CCU2D: 58 CU2: 18 DPR16X4C: 14 FADD2B: 18 FD1P3BX: 8 FD1P3DX: 330 FD1S3AX: 47 FD1S3BX: 73 FD1S3DX: 251 FSUB2B: 3 GSR: 1 IB: 2 IFS1P3BX: 16 INV: 12 OB: 37 OFS1P3BX: 18 OFS1P3DX: 18 OR2: 3 ORCALUT4: 291 PUR: 1 ROM16X1A: 41 VHI: 1 VLO: 1 XOR2: 25 Finished restoring hierarchy (Time elapsed 0h:00m:04s; Memory used current: 87MB peak: 88MB) Writing Analyst data base C:\work\LSCC\TFTSurfer\VHDL\tftsurfer_demo_v0\par_d12\tftsurfer\tftsurfer.srm Finished Writing Netlist Databases (Time elapsed 0h:00m:05s; Memory used current: 87MB peak: 88MB) Writing EDIF Netlist and constraint files E-2010.09L-SP2 @N:BW106 : | Synplicity Constraint File capacitance units will use default value of 1pF Finished Writing EDIF Netlist and constraint files (Time elapsed 0h:00m:05s; Memory used current: 91MB peak: 92MB) Starting Writing Gated Clock Conversion Report (Time elapsed 0h:00m:05s; Memory used current: 90MB peak: 92MB) @N:MF276 : | Gated clock conversion enabled, but no gated clocks found in design Finished Writing Gated Clock Conversion Report (Time elapsed 0h:00m:05s; Memory used current: 90MB peak: 92MB) Starting Writing Generated Clock Conversion Report (Time elapsed 0h:00m:05s; Memory used current: 90MB peak: 92MB) @N:MF333 : | Generated clock conversion enabled, but no generated clocks found in design Finished Writing Generated Clock Conversion Report (Time elapsed 0h:00m:05s; Memory used current: 90MB peak: 92MB) @W:MT246 : tftsurfer_top.vhd(464) | Blackbox ODDRXE is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : tftsurfer_top.vhd(435) | Blackbox OSCH is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : tx_lvds_71.vhd(197) | Blackbox ECLKSYNCA is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : tx_lvds_71.vhd(192) | Blackbox CLKDIVC is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : tx_lvds_71.vhd(184) | Blackbox ODDRX71A is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : pixel_rgb_fifo.vhd(835) | Blackbox AGEB2 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : pll_block.vhd(120) | Blackbox EHXPLLJ is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock tftsurfer_top|osch_clk_sig_inferred_clock with period 4.57ns. A user-defined clock should be declared on object "n:osch_clk_sig" @W:MT420 : | Found inferred clock pll_block|CLKOS3_inferred_clock with period 6.51ns. A user-defined clock should be declared on object "n:PLL_BLOCK_INST.CLKOS3" @W:MT420 : | Found inferred clock pll_block|CLKOP_inferred_clock with period 5.66ns. A user-defined clock should be declared on object "n:PLL_BLOCK_INST.CLKOP" ##### START OF TIMING REPORT #####[ # Timing Report written on Sun Sep 18 00:45:43 2011 # Top view: tftsurfer_top Requested Frequency: 153.5 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | This timing report estimates place and route data. Please look at the place and route timing report for final timing.. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock.. Performance Summary ******************* Worst slack in design: -1.149 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group --------------------------------------------------------------------------------------------------------------------------------------------------- pll_block|CLKOP_inferred_clock 176.5 MHz 150.1 MHz 5.664 6.664 -1.000 inferred Autoconstr_clkgroup_0 pll_block|CLKOS3_inferred_clock 153.5 MHz 130.5 MHz 6.513 7.663 -1.149 inferred Autoconstr_clkgroup_1 tftsurfer_top|osch_clk_sig_inferred_clock 219.0 MHz 186.2 MHz 4.566 5.372 -0.806 inferred Autoconstr_clkgroup_2 System 779.7 MHz 662.8 MHz 1.283 1.509 -0.226 system system_clkgroup =================================================================================================================================================== Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack ----------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 1.283 -0.226 | No paths - | No paths - | No paths - System pll_block|CLKOP_inferred_clock | 5.664 4.045 | No paths - | No paths - | No paths - System pll_block|CLKOS3_inferred_clock | 6.513 5.280 | No paths - | No paths - | No paths - System tftsurfer_top|osch_clk_sig_inferred_clock | 4.566 4.460 | No paths - | No paths - | No paths - pll_block|CLKOP_inferred_clock System | 5.664 2.235 | No paths - | No paths - | No paths - pll_block|CLKOP_inferred_clock pll_block|CLKOP_inferred_clock | 5.664 -1.000 | No paths - | No paths - | No paths - pll_block|CLKOP_inferred_clock pll_block|CLKOS3_inferred_clock | Diff grp - | No paths - | No paths - | No paths - pll_block|CLKOS3_inferred_clock System | 6.513 3.228 | No paths - | No paths - | No paths - pll_block|CLKOS3_inferred_clock pll_block|CLKOP_inferred_clock | Diff grp - | No paths - | No paths - | No paths - pll_block|CLKOS3_inferred_clock pll_block|CLKOS3_inferred_clock | 6.513 -1.149 | No paths - | No paths - | No paths - tftsurfer_top|osch_clk_sig_inferred_clock pll_block|CLKOP_inferred_clock | Diff grp - | No paths - | No paths - | No paths - tftsurfer_top|osch_clk_sig_inferred_clock tftsurfer_top|osch_clk_sig_inferred_clock | 4.566 -0.806 | No paths - | No paths - | No paths - ============================================================================================================================================================================= Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: pll_block|CLKOP_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------------------- SDRAM_CTRL_INST.sys_ref_req_reg pll_block|CLKOP_inferred_clock FD1S3DX Q sys_ref_req_reg 1.220 -1.000 SDRAM_CTRL_INST.sdram_fsm_st_fast[4] pll_block|CLKOP_inferred_clock FD1S3DX Q sdram_fsm_st_fast[4] 1.044 -0.824 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.FF_12 pll_block|CLKOP_inferred_clock FD1S3DX Q w_gcount_r24 1.188 -0.587 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.FF_13 pll_block|CLKOP_inferred_clock FD1S3DX Q w_gcount_r23 1.108 -0.507 SDRAM_CTRL_INST.sdram_fsm_st[1] pll_block|CLKOP_inferred_clock FD1S3DX Q sdram_fsm_st[1] 1.336 -0.331 SDRAM_CTRL_INST.sdram_fsm_st[2] pll_block|CLKOP_inferred_clock FD1S3DX Q sdram_fsm_st[2] 1.336 -0.331 SDRAM_CTRL_INST.sdram_fsm_st[3] pll_block|CLKOP_inferred_clock FD1S3DX Q sdram_fsm_st[3] 1.326 -0.321 SDRAM_CTRL_INST.sdram_fsm_st[0] pll_block|CLKOP_inferred_clock FD1S3DX Q sdram_fsm_st[0] 1.337 -0.236 SDRAM_CTRL_INST.sdram_fsm_st_4_rep1 pll_block|CLKOP_inferred_clock FD1S3DX Q sdram_fsm_st_4_rep1 1.188 -0.087 SDRAM_CTRL_INST.sdram_fsm_st_fast[5] pll_block|CLKOP_inferred_clock FD1S3DX Q sdram_fsm_st_fast[5] 1.108 -0.007 =========================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------- SDRAM_CTRL_INST.sdram_fsm_st[0] pll_block|CLKOP_inferred_clock FD1S3DX D N_24_i 5.921 -1.000 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.FF_2 pll_block|CLKOP_inferred_clock FD1S3DX D rfill_sub_4 5.559 -0.587 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.FF_3 pll_block|CLKOP_inferred_clock FD1S3DX D rfill_sub_3 5.559 -0.587 SDRAM_CTRL_INST.sdram_fsm_st[3] pll_block|CLKOP_inferred_clock FD1S3DX D m65_i 5.921 -0.331 SDRAM_CTRL_INST.sdram_fsm_st[1] pll_block|CLKOP_inferred_clock FD1S3DX D N_181_i 5.921 -0.172 SDRAM_CTRL_INST.sdram_fsm_st[2] pll_block|CLKOP_inferred_clock FD1S3DX D N_46_i 5.921 0.005 MONSTER_MANAGER_INST.sys_addr[0] pll_block|CLKOP_inferred_clock FD1P3DX SP N_37 5.193 0.390 MONSTER_MANAGER_INST.sys_addr[1] pll_block|CLKOP_inferred_clock FD1P3DX SP N_37 5.193 0.390 MONSTER_MANAGER_INST.sys_addr[2] pll_block|CLKOP_inferred_clock FD1P3DX SP N_37 5.193 0.390 MONSTER_MANAGER_INST.sys_addr[3] pll_block|CLKOP_inferred_clock FD1P3DX SP N_37 5.193 0.390 ================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 5.664 - Setup time: -0.257 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.921 - Propagation time: 6.921 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.000 Number of logic level(s): 6 Starting point: SDRAM_CTRL_INST.sys_ref_req_reg / Q Ending point: SDRAM_CTRL_INST.sdram_fsm_st[0] / D The start point is clocked by pll_block|CLKOP_inferred_clock [rising] on pin CK The end point is clocked by pll_block|CLKOP_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------- SDRAM_CTRL_INST.sys_ref_req_reg FD1S3DX Q Out 1.220 1.220 - sys_ref_req_reg Net - - - - 8 SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.m23_0_a5_5_0 ORCALUT4 B In 0.000 1.220 - SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.m23_0_a5_5_0 ORCALUT4 Z Out 1.017 2.237 - m23_0_a5_5_0 Net - - - - 1 SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.m23_0_a5_5 ORCALUT4 D In 0.000 2.237 - SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.m23_0_a5_5 ORCALUT4 Z Out 1.017 3.253 - N_230 Net - - - - 1 SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.m23_0_3 ORCALUT4 A In 0.000 3.253 - SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.m23_0_3 ORCALUT4 Z Out 1.017 4.270 - m23_0_3 Net - - - - 1 SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.m23_0_5 ORCALUT4 D In 0.000 4.270 - SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.m23_0_5 ORCALUT4 Z Out 1.017 5.287 - m23_0_5 Net - - - - 1 SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.m23_0_6 ORCALUT4 D In 0.000 5.287 - SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.m23_0_6 ORCALUT4 Z Out 1.017 6.304 - m23_0_6 Net - - - - 1 SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.N_24_i ORCALUT4 B In 0.000 6.304 - SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.N_24_i ORCALUT4 Z Out 0.617 6.921 - N_24_i Net - - - - 1 SDRAM_CTRL_INST.sdram_fsm_st[0] FD1S3DX D In 0.000 6.921 - ==================================================================================================================== Path information for path number 2: Requested Period: 5.664 - Setup time: -0.257 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.921 - Propagation time: 6.745 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.824 Number of logic level(s): 6 Starting point: SDRAM_CTRL_INST.sdram_fsm_st_fast[4] / Q Ending point: SDRAM_CTRL_INST.sdram_fsm_st[0] / D The start point is clocked by pll_block|CLKOP_inferred_clock [rising] on pin CK The end point is clocked by pll_block|CLKOP_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------- SDRAM_CTRL_INST.sdram_fsm_st_fast[4] FD1S3DX Q Out 1.044 1.044 - sdram_fsm_st_fast[4] Net - - - - 2 SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.m23_0_a5_5_0 ORCALUT4 A In 0.000 1.044 - SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.m23_0_a5_5_0 ORCALUT4 Z Out 1.017 2.061 - m23_0_a5_5_0 Net - - - - 1 SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.m23_0_a5_5 ORCALUT4 D In 0.000 2.061 - SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.m23_0_a5_5 ORCALUT4 Z Out 1.017 3.077 - N_230 Net - - - - 1 SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.m23_0_3 ORCALUT4 A In 0.000 3.077 - SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.m23_0_3 ORCALUT4 Z Out 1.017 4.094 - m23_0_3 Net - - - - 1 SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.m23_0_5 ORCALUT4 D In 0.000 4.094 - SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.m23_0_5 ORCALUT4 Z Out 1.017 5.111 - m23_0_5 Net - - - - 1 SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.m23_0_6 ORCALUT4 D In 0.000 5.111 - SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.m23_0_6 ORCALUT4 Z Out 1.017 6.128 - m23_0_6 Net - - - - 1 SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.N_24_i ORCALUT4 B In 0.000 6.128 - SDRAM_CTRL_INST.sdram_fsm_st_ns_5_0_.N_24_i ORCALUT4 Z Out 0.617 6.745 - N_24_i Net - - - - 1 SDRAM_CTRL_INST.sdram_fsm_st[0] FD1S3DX D In 0.000 6.745 - ==================================================================================================================== Path information for path number 3: Requested Period: 5.664 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.559 - Propagation time: 6.146 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.587 Number of logic level(s): 5 Starting point: PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.FF_12 / Q Ending point: PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.FF_2 / D The start point is clocked by pll_block|CLKOP_inferred_clock [rising] on pin CK The end point is clocked by pll_block|CLKOP_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------- PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.FF_12 FD1S3DX Q Out 1.188 1.188 - w_gcount_r24 Net - - - - 6 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.LUT4_10 ROM16X1A AD2 In 0.000 1.188 - PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.LUT4_10 ROM16X1A DO0 Out 1.153 2.341 - wcount_r3 Net - - - - 3 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.LUT4_8 ROM16X1A AD0 In 0.000 2.341 - PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.LUT4_8 ROM16X1A DO0 Out 1.089 3.429 - wcount_r0 Net - - - - 2 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.rfill_0 FSUB2B A1 In 0.000 3.429 - PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.rfill_0 FSUB2B BOUT Out 1.509 4.938 - co0_2 Net - - - - 1 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.rfill_1 FSUB2B BI In 0.000 4.938 - PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.rfill_1 FSUB2B BOUT Out 0.143 5.081 - co1_2 Net - - - - 1 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.rfill_2 FSUB2B BI In 0.000 5.081 - PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.rfill_2 FSUB2B S1 Out 1.065 6.146 - rfill_sub_4 Net - - - - 1 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.FF_2 FD1S3DX D In 0.000 6.146 - ========================================================================================================================= Path information for path number 4: Requested Period: 5.664 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.559 - Propagation time: 6.146 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.587 Number of logic level(s): 5 Starting point: PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.FF_12 / Q Ending point: PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.FF_3 / D The start point is clocked by pll_block|CLKOP_inferred_clock [rising] on pin CK The end point is clocked by pll_block|CLKOP_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------- PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.FF_12 FD1S3DX Q Out 1.188 1.188 - w_gcount_r24 Net - - - - 6 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.LUT4_10 ROM16X1A AD2 In 0.000 1.188 - PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.LUT4_10 ROM16X1A DO0 Out 1.153 2.341 - wcount_r3 Net - - - - 3 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.LUT4_8 ROM16X1A AD0 In 0.000 2.341 - PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.LUT4_8 ROM16X1A DO0 Out 1.089 3.429 - wcount_r0 Net - - - - 2 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.rfill_0 FSUB2B A1 In 0.000 3.429 - PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.rfill_0 FSUB2B BOUT Out 1.509 4.938 - co0_2 Net - - - - 1 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.rfill_1 FSUB2B BI In 0.000 4.938 - PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.rfill_1 FSUB2B BOUT Out 0.143 5.081 - co1_2 Net - - - - 1 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.rfill_2 FSUB2B BI In 0.000 5.081 - PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.rfill_2 FSUB2B S0 Out 1.065 6.146 - rfill_sub_3 Net - - - - 1 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.FF_3 FD1S3DX D In 0.000 6.146 - ========================================================================================================================= Path information for path number 5: Requested Period: 5.664 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 5.559 - Propagation time: 6.066 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.507 Number of logic level(s): 5 Starting point: PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.FF_13 / Q Ending point: PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.FF_2 / D The start point is clocked by pll_block|CLKOP_inferred_clock [rising] on pin CK The end point is clocked by pll_block|CLKOP_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------- PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.FF_13 FD1S3DX Q Out 1.108 1.108 - w_gcount_r23 Net - - - - 3 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.LUT4_10 ROM16X1A AD3 In 0.000 1.108 - PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.LUT4_10 ROM16X1A DO0 Out 1.153 2.261 - wcount_r3 Net - - - - 3 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.LUT4_8 ROM16X1A AD0 In 0.000 2.261 - PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.LUT4_8 ROM16X1A DO0 Out 1.089 3.349 - wcount_r0 Net - - - - 2 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.rfill_0 FSUB2B A1 In 0.000 3.349 - PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.rfill_0 FSUB2B BOUT Out 1.509 4.858 - co0_2 Net - - - - 1 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.rfill_1 FSUB2B BI In 0.000 4.858 - PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.rfill_1 FSUB2B BOUT Out 0.143 5.001 - co1_2 Net - - - - 1 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.rfill_2 FSUB2B BI In 0.000 5.001 - PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.rfill_2 FSUB2B S1 Out 1.065 6.066 - rfill_sub_4 Net - - - - 1 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.FF_2 FD1S3DX D In 0.000 6.066 - ========================================================================================================================= ==================================== Detailed Report for Clock: pll_block|CLKOS3_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------------------- SDRAM_TEST_GENERATOR_INST.column_cnt[3] pll_block|CLKOS3_inferred_clock FD1P3DX Q column_cnt[3] 1.108 -1.149 SDRAM_TEST_GENERATOR_INST.column_cnt[4] pll_block|CLKOS3_inferred_clock FD1P3DX Q column_cnt[4] 1.108 -1.149 SDRAM_TEST_GENERATOR_INST.column_cnt[8] pll_block|CLKOS3_inferred_clock FD1P3DX Q column_cnt[8] 1.108 -1.149 SDRAM_TEST_GENERATOR_INST.column_cnt[9] pll_block|CLKOS3_inferred_clock FD1P3DX Q column_cnt[9] 1.108 -1.149 SDRAM_TEST_GENERATOR_INST.row_cnt[3] pll_block|CLKOS3_inferred_clock FD1S3DX Q row_cnt[3] 1.108 -1.149 SDRAM_TEST_GENERATOR_INST.row_cnt[4] pll_block|CLKOS3_inferred_clock FD1S3DX Q row_cnt[4] 1.108 -1.149 SDRAM_TEST_GENERATOR_INST.row_cnt[5] pll_block|CLKOS3_inferred_clock FD1S3DX Q row_cnt[5] 1.108 -1.149 SDRAM_TEST_GENERATOR_INST.column_cnt[0] pll_block|CLKOS3_inferred_clock FD1S3DX Q column_cnt[0] 1.188 -0.213 SDRAM_TEST_GENERATOR_INST.row_cnt[0] pll_block|CLKOS3_inferred_clock FD1S3DX Q row_cnt[0] 1.180 -0.205 SDRAM_TEST_GENERATOR_INST.scaler_cnt_fast[0] pll_block|CLKOS3_inferred_clock FD1S3DX Q scaler_cnt_fast[0] 1.148 -0.173 ================================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------- SDRAM_TEST_GENERATOR_INST.row_cnt[9] pll_block|CLKOS3_inferred_clock FD1S3DX D row_cnt_4[9] 6.770 -1.149 SDRAM_TEST_GENERATOR_INST.row_cnt[6] pll_block|CLKOS3_inferred_clock FD1S3DX D row_cnt_4[6] 6.770 -0.864 SDRAM_TEST_GENERATOR_INST.row_cnt[7] pll_block|CLKOS3_inferred_clock FD1S3DX D un1_row_cnt[8] 6.408 -0.752 SDRAM_TEST_GENERATOR_INST.row_cnt[8] pll_block|CLKOS3_inferred_clock FD1S3DX D un1_row_cnt[9] 6.408 -0.752 SDRAM_TEST_GENERATOR_INST.row_cnt[4] pll_block|CLKOS3_inferred_clock FD1S3DX D row_cnt_4[4] 6.770 -0.721 SDRAM_TEST_GENERATOR_INST.row_cnt[5] pll_block|CLKOS3_inferred_clock FD1S3DX D un1_row_cnt[6] 6.408 -0.609 SDRAM_TEST_GENERATOR_INST.row_cnt[1] pll_block|CLKOS3_inferred_clock FD1S3DX D row_cnt_4[1] 6.770 -0.578 SDRAM_TEST_GENERATOR_INST.row_cnt[2] pll_block|CLKOS3_inferred_clock FD1S3DX D row_cnt_4[2] 6.770 -0.578 SDRAM_TEST_GENERATOR_INST.row_cnt[3] pll_block|CLKOS3_inferred_clock FD1S3DX D un1_row_cnt[4] 6.408 -0.467 SDRAM_TEST_GENERATOR_INST.row_cnt[0] pll_block|CLKOS3_inferred_clock FD1S3DX D row_cnt_4[0] 6.770 0.482 ======================================================================================================================================= Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 6.513 - Setup time: -0.257 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.770 - Propagation time: 7.920 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.149 Number of logic level(s): 10 Starting point: SDRAM_TEST_GENERATOR_INST.column_cnt[3] / Q Ending point: SDRAM_TEST_GENERATOR_INST.row_cnt[9] / D The start point is clocked by pll_block|CLKOS3_inferred_clock [rising] on pin CK The end point is clocked by pll_block|CLKOS3_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- SDRAM_TEST_GENERATOR_INST.column_cnt[3] FD1P3DX Q Out 1.108 1.108 - column_cnt[3] Net - - - - 3 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO_3 ORCALUT4 A In 0.000 1.108 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO_3 ORCALUT4 Z Out 1.017 2.125 - g0_sx_sx Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO_1 ORCALUT4 C In 0.000 2.125 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO_1 ORCALUT4 Z Out 1.017 3.141 - g0_sx Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO ORCALUT4 D In 0.000 3.141 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO ORCALUT4 Z Out 1.017 4.158 - row_cnt_1_sqmuxa Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0 CCU2D B0 In 0.000 4.158 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0 CCU2D COUT Out 1.509 5.667 - un1_row_cnt_cry_0 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_1_0 CCU2D CIN In 0.000 5.667 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_1_0 CCU2D COUT Out 0.143 5.810 - un1_row_cnt_cry_2 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_3_0 CCU2D CIN In 0.000 5.810 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_3_0 CCU2D COUT Out 0.143 5.953 - un1_row_cnt_cry_4 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_5_0 CCU2D CIN In 0.000 5.953 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_5_0 CCU2D COUT Out 0.143 6.095 - un1_row_cnt_cry_6 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_7_0 CCU2D CIN In 0.000 6.095 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_7_0 CCU2D COUT Out 0.143 6.238 - un1_row_cnt_cry_8 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_s_9_0 CCU2D CIN In 0.000 6.238 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_s_9_0 CCU2D S0 Out 1.065 7.303 - un1_row_cnt_s_9_0_S0 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.row_cnt_4[9] ORCALUT4 A In 0.000 7.303 - SDRAM_TEST_GENERATOR_INST.row_cnt_4[9] ORCALUT4 Z Out 0.617 7.920 - row_cnt_4[9] Net - - - - 1 SDRAM_TEST_GENERATOR_INST.row_cnt[9] FD1S3DX D In 0.000 7.920 - ====================================================================================================================== Path information for path number 2: Requested Period: 6.513 - Setup time: -0.257 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.770 - Propagation time: 7.920 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.149 Number of logic level(s): 10 Starting point: SDRAM_TEST_GENERATOR_INST.column_cnt[4] / Q Ending point: SDRAM_TEST_GENERATOR_INST.row_cnt[9] / D The start point is clocked by pll_block|CLKOS3_inferred_clock [rising] on pin CK The end point is clocked by pll_block|CLKOS3_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- SDRAM_TEST_GENERATOR_INST.column_cnt[4] FD1P3DX Q Out 1.108 1.108 - column_cnt[4] Net - - - - 3 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO_3 ORCALUT4 B In 0.000 1.108 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO_3 ORCALUT4 Z Out 1.017 2.125 - g0_sx_sx Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO_1 ORCALUT4 C In 0.000 2.125 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO_1 ORCALUT4 Z Out 1.017 3.141 - g0_sx Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO ORCALUT4 D In 0.000 3.141 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO ORCALUT4 Z Out 1.017 4.158 - row_cnt_1_sqmuxa Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0 CCU2D B0 In 0.000 4.158 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0 CCU2D COUT Out 1.509 5.667 - un1_row_cnt_cry_0 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_1_0 CCU2D CIN In 0.000 5.667 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_1_0 CCU2D COUT Out 0.143 5.810 - un1_row_cnt_cry_2 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_3_0 CCU2D CIN In 0.000 5.810 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_3_0 CCU2D COUT Out 0.143 5.953 - un1_row_cnt_cry_4 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_5_0 CCU2D CIN In 0.000 5.953 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_5_0 CCU2D COUT Out 0.143 6.095 - un1_row_cnt_cry_6 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_7_0 CCU2D CIN In 0.000 6.095 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_7_0 CCU2D COUT Out 0.143 6.238 - un1_row_cnt_cry_8 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_s_9_0 CCU2D CIN In 0.000 6.238 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_s_9_0 CCU2D S0 Out 1.065 7.303 - un1_row_cnt_s_9_0_S0 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.row_cnt_4[9] ORCALUT4 A In 0.000 7.303 - SDRAM_TEST_GENERATOR_INST.row_cnt_4[9] ORCALUT4 Z Out 0.617 7.920 - row_cnt_4[9] Net - - - - 1 SDRAM_TEST_GENERATOR_INST.row_cnt[9] FD1S3DX D In 0.000 7.920 - ====================================================================================================================== Path information for path number 3: Requested Period: 6.513 - Setup time: -0.257 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.770 - Propagation time: 7.920 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.149 Number of logic level(s): 10 Starting point: SDRAM_TEST_GENERATOR_INST.column_cnt[8] / Q Ending point: SDRAM_TEST_GENERATOR_INST.row_cnt[9] / D The start point is clocked by pll_block|CLKOS3_inferred_clock [rising] on pin CK The end point is clocked by pll_block|CLKOS3_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- SDRAM_TEST_GENERATOR_INST.column_cnt[8] FD1P3DX Q Out 1.108 1.108 - column_cnt[8] Net - - - - 3 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO_3 ORCALUT4 C In 0.000 1.108 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO_3 ORCALUT4 Z Out 1.017 2.125 - g0_sx_sx Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO_1 ORCALUT4 C In 0.000 2.125 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO_1 ORCALUT4 Z Out 1.017 3.141 - g0_sx Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO ORCALUT4 D In 0.000 3.141 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO ORCALUT4 Z Out 1.017 4.158 - row_cnt_1_sqmuxa Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0 CCU2D B0 In 0.000 4.158 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0 CCU2D COUT Out 1.509 5.667 - un1_row_cnt_cry_0 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_1_0 CCU2D CIN In 0.000 5.667 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_1_0 CCU2D COUT Out 0.143 5.810 - un1_row_cnt_cry_2 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_3_0 CCU2D CIN In 0.000 5.810 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_3_0 CCU2D COUT Out 0.143 5.953 - un1_row_cnt_cry_4 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_5_0 CCU2D CIN In 0.000 5.953 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_5_0 CCU2D COUT Out 0.143 6.095 - un1_row_cnt_cry_6 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_7_0 CCU2D CIN In 0.000 6.095 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_7_0 CCU2D COUT Out 0.143 6.238 - un1_row_cnt_cry_8 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_s_9_0 CCU2D CIN In 0.000 6.238 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_s_9_0 CCU2D S0 Out 1.065 7.303 - un1_row_cnt_s_9_0_S0 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.row_cnt_4[9] ORCALUT4 A In 0.000 7.303 - SDRAM_TEST_GENERATOR_INST.row_cnt_4[9] ORCALUT4 Z Out 0.617 7.920 - row_cnt_4[9] Net - - - - 1 SDRAM_TEST_GENERATOR_INST.row_cnt[9] FD1S3DX D In 0.000 7.920 - ====================================================================================================================== Path information for path number 4: Requested Period: 6.513 - Setup time: -0.257 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.770 - Propagation time: 7.920 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.149 Number of logic level(s): 10 Starting point: SDRAM_TEST_GENERATOR_INST.column_cnt[9] / Q Ending point: SDRAM_TEST_GENERATOR_INST.row_cnt[9] / D The start point is clocked by pll_block|CLKOS3_inferred_clock [rising] on pin CK The end point is clocked by pll_block|CLKOS3_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- SDRAM_TEST_GENERATOR_INST.column_cnt[9] FD1P3DX Q Out 1.108 1.108 - column_cnt[9] Net - - - - 3 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO_3 ORCALUT4 D In 0.000 1.108 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO_3 ORCALUT4 Z Out 1.017 2.125 - g0_sx_sx Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO_1 ORCALUT4 C In 0.000 2.125 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO_1 ORCALUT4 Z Out 1.017 3.141 - g0_sx Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO ORCALUT4 D In 0.000 3.141 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO ORCALUT4 Z Out 1.017 4.158 - row_cnt_1_sqmuxa Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0 CCU2D B0 In 0.000 4.158 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0 CCU2D COUT Out 1.509 5.667 - un1_row_cnt_cry_0 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_1_0 CCU2D CIN In 0.000 5.667 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_1_0 CCU2D COUT Out 0.143 5.810 - un1_row_cnt_cry_2 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_3_0 CCU2D CIN In 0.000 5.810 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_3_0 CCU2D COUT Out 0.143 5.953 - un1_row_cnt_cry_4 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_5_0 CCU2D CIN In 0.000 5.953 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_5_0 CCU2D COUT Out 0.143 6.095 - un1_row_cnt_cry_6 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_7_0 CCU2D CIN In 0.000 6.095 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_7_0 CCU2D COUT Out 0.143 6.238 - un1_row_cnt_cry_8 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_s_9_0 CCU2D CIN In 0.000 6.238 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_s_9_0 CCU2D S0 Out 1.065 7.303 - un1_row_cnt_s_9_0_S0 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.row_cnt_4[9] ORCALUT4 A In 0.000 7.303 - SDRAM_TEST_GENERATOR_INST.row_cnt_4[9] ORCALUT4 Z Out 0.617 7.920 - row_cnt_4[9] Net - - - - 1 SDRAM_TEST_GENERATOR_INST.row_cnt[9] FD1S3DX D In 0.000 7.920 - ====================================================================================================================== Path information for path number 5: Requested Period: 6.513 - Setup time: -0.257 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.770 - Propagation time: 7.920 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.149 Number of logic level(s): 10 Starting point: SDRAM_TEST_GENERATOR_INST.row_cnt[3] / Q Ending point: SDRAM_TEST_GENERATOR_INST.row_cnt[9] / D The start point is clocked by pll_block|CLKOS3_inferred_clock [rising] on pin CK The end point is clocked by pll_block|CLKOS3_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- SDRAM_TEST_GENERATOR_INST.row_cnt[3] FD1S3DX Q Out 1.108 1.108 - row_cnt[3] Net - - - - 3 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO_2 ORCALUT4 A In 0.000 1.108 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO_2 ORCALUT4 Z Out 1.017 2.125 - un1_row_cnt_cry_0_0_RNO_2 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO_0 ORCALUT4 A In 0.000 2.125 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO_0 ORCALUT4 Z Out 1.017 3.141 - un1_row_cnt_cry_0_0_RNO_0 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO ORCALUT4 A In 0.000 3.141 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0_RNO ORCALUT4 Z Out 1.017 4.158 - row_cnt_1_sqmuxa Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0 CCU2D B0 In 0.000 4.158 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_0_0 CCU2D COUT Out 1.509 5.667 - un1_row_cnt_cry_0 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_1_0 CCU2D CIN In 0.000 5.667 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_1_0 CCU2D COUT Out 0.143 5.810 - un1_row_cnt_cry_2 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_3_0 CCU2D CIN In 0.000 5.810 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_3_0 CCU2D COUT Out 0.143 5.953 - un1_row_cnt_cry_4 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_5_0 CCU2D CIN In 0.000 5.953 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_5_0 CCU2D COUT Out 0.143 6.095 - un1_row_cnt_cry_6 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_7_0 CCU2D CIN In 0.000 6.095 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_cry_7_0 CCU2D COUT Out 0.143 6.238 - un1_row_cnt_cry_8 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.un1_row_cnt_s_9_0 CCU2D CIN In 0.000 6.238 - SDRAM_TEST_GENERATOR_INST.un1_row_cnt_s_9_0 CCU2D S0 Out 1.065 7.303 - un1_row_cnt_s_9_0_S0 Net - - - - 1 SDRAM_TEST_GENERATOR_INST.row_cnt_4[9] ORCALUT4 A In 0.000 7.303 - SDRAM_TEST_GENERATOR_INST.row_cnt_4[9] ORCALUT4 Z Out 0.617 7.920 - row_cnt_4[9] Net - - - - 1 SDRAM_TEST_GENERATOR_INST.row_cnt[9] FD1S3DX D In 0.000 7.920 - ====================================================================================================================== ==================================== Detailed Report for Clock: tftsurfer_top|osch_clk_sig_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------------- POWER_MANAGER_INST.timer_cnt_rst tftsurfer_top|osch_clk_sig_inferred_clock FD1P3BX Q timer_cnt_rst 0.972 -0.806 POWER_MANAGER_INST.timer_cnt[0] tftsurfer_top|osch_clk_sig_inferred_clock FD1S3AX Q timer_cnt[0] 1.044 -0.014 POWER_MANAGER_INST.timer_cnt[1] tftsurfer_top|osch_clk_sig_inferred_clock FD1S3AX Q timer_cnt[1] 1.044 0.129 POWER_MANAGER_INST.timer_cnt[2] tftsurfer_top|osch_clk_sig_inferred_clock FD1S3AX Q timer_cnt[2] 1.044 0.129 POWER_MANAGER_INST.timer_cnt[3] tftsurfer_top|osch_clk_sig_inferred_clock FD1S3AX Q timer_cnt[3] 1.044 0.272 POWER_MANAGER_INST.timer_cnt[4] tftsurfer_top|osch_clk_sig_inferred_clock FD1S3AX Q timer_cnt[4] 1.044 0.272 POWER_MANAGER_INST.timer_cnt[5] tftsurfer_top|osch_clk_sig_inferred_clock FD1S3AX Q timer_cnt[5] 1.044 0.415 POWER_MANAGER_INST.timer_cnt[6] tftsurfer_top|osch_clk_sig_inferred_clock FD1S3AX Q timer_cnt[6] 1.044 0.415 POWER_MANAGER_INST.timer_cnt[8] tftsurfer_top|osch_clk_sig_inferred_clock FD1S3AX Q timer_cnt[8] 1.108 0.493 POWER_MANAGER_INST.timer_cnt[7] tftsurfer_top|osch_clk_sig_inferred_clock FD1S3AX Q timer_cnt[7] 1.044 0.558 =========================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------------------------- POWER_MANAGER_INST.timer_cnt[13] tftsurfer_top|osch_clk_sig_inferred_clock FD1S3AX D timer_cnt_s[13] 4.460 -0.806 POWER_MANAGER_INST.timer_cnt[14] tftsurfer_top|osch_clk_sig_inferred_clock FD1S3AX D timer_cnt_s[14] 4.460 -0.806 POWER_MANAGER_INST.timer_cnt[11] tftsurfer_top|osch_clk_sig_inferred_clock FD1S3AX D timer_cnt_s[11] 4.460 -0.663 POWER_MANAGER_INST.timer_cnt[12] tftsurfer_top|osch_clk_sig_inferred_clock FD1S3AX D timer_cnt_s[12] 4.460 -0.663 POWER_MANAGER_INST.timer_cnt[9] tftsurfer_top|osch_clk_sig_inferred_clock FD1S3AX D timer_cnt_s[9] 4.460 -0.520 POWER_MANAGER_INST.timer_cnt[10] tftsurfer_top|osch_clk_sig_inferred_clock FD1S3AX D timer_cnt_s[10] 4.460 -0.520 POWER_MANAGER_INST.timer_cnt[7] tftsurfer_top|osch_clk_sig_inferred_clock FD1S3AX D timer_cnt_s[7] 4.460 -0.377 POWER_MANAGER_INST.timer_cnt[8] tftsurfer_top|osch_clk_sig_inferred_clock FD1S3AX D timer_cnt_s[8] 4.460 -0.377 POWER_MANAGER_INST.timer_cnt[5] tftsurfer_top|osch_clk_sig_inferred_clock FD1S3AX D timer_cnt_s[5] 4.460 -0.234 POWER_MANAGER_INST.timer_cnt[6] tftsurfer_top|osch_clk_sig_inferred_clock FD1S3AX D timer_cnt_s[6] 4.460 -0.234 ============================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 4.566 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.460 - Propagation time: 5.266 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.806 Number of logic level(s): 9 Starting point: POWER_MANAGER_INST.timer_cnt_rst / Q Ending point: POWER_MANAGER_INST.timer_cnt[14] / D The start point is clocked by tftsurfer_top|osch_clk_sig_inferred_clock [rising] on pin CK The end point is clocked by tftsurfer_top|osch_clk_sig_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------- POWER_MANAGER_INST.timer_cnt_rst FD1P3BX Q Out 0.972 0.972 - timer_cnt_rst Net - - - - 1 POWER_MANAGER_INST.timer_cnt_rst_RNI74JF INV A In 0.000 0.972 - POWER_MANAGER_INST.timer_cnt_rst_RNI74JF INV Z Out 0.864 1.836 - timer_cnt_rst_i Net - - - - 16 POWER_MANAGER_INST.timer_cnt_cry_0[0] CCU2D A1 In 0.000 1.836 - POWER_MANAGER_INST.timer_cnt_cry_0[0] CCU2D COUT Out 1.509 3.345 - timer_cnt_cry[0] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[1] CCU2D CIN In 0.000 3.345 - POWER_MANAGER_INST.timer_cnt_cry_0[1] CCU2D COUT Out 0.143 3.487 - timer_cnt_cry[2] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[3] CCU2D CIN In 0.000 3.487 - POWER_MANAGER_INST.timer_cnt_cry_0[3] CCU2D COUT Out 0.143 3.630 - timer_cnt_cry[4] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[5] CCU2D CIN In 0.000 3.630 - POWER_MANAGER_INST.timer_cnt_cry_0[5] CCU2D COUT Out 0.143 3.773 - timer_cnt_cry[6] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[7] CCU2D CIN In 0.000 3.773 - POWER_MANAGER_INST.timer_cnt_cry_0[7] CCU2D COUT Out 0.143 3.916 - timer_cnt_cry[8] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[9] CCU2D CIN In 0.000 3.916 - POWER_MANAGER_INST.timer_cnt_cry_0[9] CCU2D COUT Out 0.143 4.059 - timer_cnt_cry[10] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[11] CCU2D CIN In 0.000 4.059 - POWER_MANAGER_INST.timer_cnt_cry_0[11] CCU2D COUT Out 0.143 4.201 - timer_cnt_cry[12] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[13] CCU2D CIN In 0.000 4.201 - POWER_MANAGER_INST.timer_cnt_cry_0[13] CCU2D S1 Out 1.065 5.266 - timer_cnt_s[14] Net - - - - 1 POWER_MANAGER_INST.timer_cnt[14] FD1S3AX D In 0.000 5.266 - ========================================================================================================== Path information for path number 2: Requested Period: 4.566 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.460 - Propagation time: 5.266 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.806 Number of logic level(s): 9 Starting point: POWER_MANAGER_INST.timer_cnt_rst / Q Ending point: POWER_MANAGER_INST.timer_cnt[14] / D The start point is clocked by tftsurfer_top|osch_clk_sig_inferred_clock [rising] on pin CK The end point is clocked by tftsurfer_top|osch_clk_sig_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------- POWER_MANAGER_INST.timer_cnt_rst FD1P3BX Q Out 0.972 0.972 - timer_cnt_rst Net - - - - 1 POWER_MANAGER_INST.timer_cnt_rst_RNI74JF INV A In 0.000 0.972 - POWER_MANAGER_INST.timer_cnt_rst_RNI74JF INV Z Out 0.864 1.836 - timer_cnt_rst_i Net - - - - 16 POWER_MANAGER_INST.timer_cnt_cry_0[0] CCU2D B0 In 0.000 1.836 - POWER_MANAGER_INST.timer_cnt_cry_0[0] CCU2D COUT Out 1.509 3.345 - timer_cnt_cry[0] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[1] CCU2D CIN In 0.000 3.345 - POWER_MANAGER_INST.timer_cnt_cry_0[1] CCU2D COUT Out 0.143 3.487 - timer_cnt_cry[2] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[3] CCU2D CIN In 0.000 3.487 - POWER_MANAGER_INST.timer_cnt_cry_0[3] CCU2D COUT Out 0.143 3.630 - timer_cnt_cry[4] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[5] CCU2D CIN In 0.000 3.630 - POWER_MANAGER_INST.timer_cnt_cry_0[5] CCU2D COUT Out 0.143 3.773 - timer_cnt_cry[6] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[7] CCU2D CIN In 0.000 3.773 - POWER_MANAGER_INST.timer_cnt_cry_0[7] CCU2D COUT Out 0.143 3.916 - timer_cnt_cry[8] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[9] CCU2D CIN In 0.000 3.916 - POWER_MANAGER_INST.timer_cnt_cry_0[9] CCU2D COUT Out 0.143 4.059 - timer_cnt_cry[10] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[11] CCU2D CIN In 0.000 4.059 - POWER_MANAGER_INST.timer_cnt_cry_0[11] CCU2D COUT Out 0.143 4.201 - timer_cnt_cry[12] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[13] CCU2D CIN In 0.000 4.201 - POWER_MANAGER_INST.timer_cnt_cry_0[13] CCU2D S1 Out 1.065 5.266 - timer_cnt_s[14] Net - - - - 1 POWER_MANAGER_INST.timer_cnt[14] FD1S3AX D In 0.000 5.266 - ========================================================================================================== Path information for path number 3: Requested Period: 4.566 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.460 - Propagation time: 5.266 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.806 Number of logic level(s): 9 Starting point: POWER_MANAGER_INST.timer_cnt_rst / Q Ending point: POWER_MANAGER_INST.timer_cnt[13] / D The start point is clocked by tftsurfer_top|osch_clk_sig_inferred_clock [rising] on pin CK The end point is clocked by tftsurfer_top|osch_clk_sig_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------- POWER_MANAGER_INST.timer_cnt_rst FD1P3BX Q Out 0.972 0.972 - timer_cnt_rst Net - - - - 1 POWER_MANAGER_INST.timer_cnt_rst_RNI74JF INV A In 0.000 0.972 - POWER_MANAGER_INST.timer_cnt_rst_RNI74JF INV Z Out 0.864 1.836 - timer_cnt_rst_i Net - - - - 16 POWER_MANAGER_INST.timer_cnt_cry_0[0] CCU2D A1 In 0.000 1.836 - POWER_MANAGER_INST.timer_cnt_cry_0[0] CCU2D COUT Out 1.509 3.345 - timer_cnt_cry[0] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[1] CCU2D CIN In 0.000 3.345 - POWER_MANAGER_INST.timer_cnt_cry_0[1] CCU2D COUT Out 0.143 3.487 - timer_cnt_cry[2] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[3] CCU2D CIN In 0.000 3.487 - POWER_MANAGER_INST.timer_cnt_cry_0[3] CCU2D COUT Out 0.143 3.630 - timer_cnt_cry[4] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[5] CCU2D CIN In 0.000 3.630 - POWER_MANAGER_INST.timer_cnt_cry_0[5] CCU2D COUT Out 0.143 3.773 - timer_cnt_cry[6] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[7] CCU2D CIN In 0.000 3.773 - POWER_MANAGER_INST.timer_cnt_cry_0[7] CCU2D COUT Out 0.143 3.916 - timer_cnt_cry[8] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[9] CCU2D CIN In 0.000 3.916 - POWER_MANAGER_INST.timer_cnt_cry_0[9] CCU2D COUT Out 0.143 4.059 - timer_cnt_cry[10] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[11] CCU2D CIN In 0.000 4.059 - POWER_MANAGER_INST.timer_cnt_cry_0[11] CCU2D COUT Out 0.143 4.201 - timer_cnt_cry[12] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[13] CCU2D CIN In 0.000 4.201 - POWER_MANAGER_INST.timer_cnt_cry_0[13] CCU2D S0 Out 1.065 5.266 - timer_cnt_s[13] Net - - - - 1 POWER_MANAGER_INST.timer_cnt[13] FD1S3AX D In 0.000 5.266 - ========================================================================================================== Path information for path number 4: Requested Period: 4.566 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.460 - Propagation time: 5.266 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.806 Number of logic level(s): 9 Starting point: POWER_MANAGER_INST.timer_cnt_rst / Q Ending point: POWER_MANAGER_INST.timer_cnt[13] / D The start point is clocked by tftsurfer_top|osch_clk_sig_inferred_clock [rising] on pin CK The end point is clocked by tftsurfer_top|osch_clk_sig_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------- POWER_MANAGER_INST.timer_cnt_rst FD1P3BX Q Out 0.972 0.972 - timer_cnt_rst Net - - - - 1 POWER_MANAGER_INST.timer_cnt_rst_RNI74JF INV A In 0.000 0.972 - POWER_MANAGER_INST.timer_cnt_rst_RNI74JF INV Z Out 0.864 1.836 - timer_cnt_rst_i Net - - - - 16 POWER_MANAGER_INST.timer_cnt_cry_0[0] CCU2D B0 In 0.000 1.836 - POWER_MANAGER_INST.timer_cnt_cry_0[0] CCU2D COUT Out 1.509 3.345 - timer_cnt_cry[0] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[1] CCU2D CIN In 0.000 3.345 - POWER_MANAGER_INST.timer_cnt_cry_0[1] CCU2D COUT Out 0.143 3.487 - timer_cnt_cry[2] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[3] CCU2D CIN In 0.000 3.487 - POWER_MANAGER_INST.timer_cnt_cry_0[3] CCU2D COUT Out 0.143 3.630 - timer_cnt_cry[4] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[5] CCU2D CIN In 0.000 3.630 - POWER_MANAGER_INST.timer_cnt_cry_0[5] CCU2D COUT Out 0.143 3.773 - timer_cnt_cry[6] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[7] CCU2D CIN In 0.000 3.773 - POWER_MANAGER_INST.timer_cnt_cry_0[7] CCU2D COUT Out 0.143 3.916 - timer_cnt_cry[8] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[9] CCU2D CIN In 0.000 3.916 - POWER_MANAGER_INST.timer_cnt_cry_0[9] CCU2D COUT Out 0.143 4.059 - timer_cnt_cry[10] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[11] CCU2D CIN In 0.000 4.059 - POWER_MANAGER_INST.timer_cnt_cry_0[11] CCU2D COUT Out 0.143 4.201 - timer_cnt_cry[12] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[13] CCU2D CIN In 0.000 4.201 - POWER_MANAGER_INST.timer_cnt_cry_0[13] CCU2D S0 Out 1.065 5.266 - timer_cnt_s[13] Net - - - - 1 POWER_MANAGER_INST.timer_cnt[13] FD1S3AX D In 0.000 5.266 - ========================================================================================================== Path information for path number 5: Requested Period: 4.566 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 4.460 - Propagation time: 5.123 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.663 Number of logic level(s): 8 Starting point: POWER_MANAGER_INST.timer_cnt_rst / Q Ending point: POWER_MANAGER_INST.timer_cnt[14] / D The start point is clocked by tftsurfer_top|osch_clk_sig_inferred_clock [rising] on pin CK The end point is clocked by tftsurfer_top|osch_clk_sig_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------- POWER_MANAGER_INST.timer_cnt_rst FD1P3BX Q Out 0.972 0.972 - timer_cnt_rst Net - - - - 1 POWER_MANAGER_INST.timer_cnt_rst_RNI74JF INV A In 0.000 0.972 - POWER_MANAGER_INST.timer_cnt_rst_RNI74JF INV Z Out 0.864 1.836 - timer_cnt_rst_i Net - - - - 16 POWER_MANAGER_INST.timer_cnt_cry_0[1] CCU2D A1 In 0.000 1.836 - POWER_MANAGER_INST.timer_cnt_cry_0[1] CCU2D COUT Out 1.509 3.345 - timer_cnt_cry[2] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[3] CCU2D CIN In 0.000 3.345 - POWER_MANAGER_INST.timer_cnt_cry_0[3] CCU2D COUT Out 0.143 3.487 - timer_cnt_cry[4] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[5] CCU2D CIN In 0.000 3.487 - POWER_MANAGER_INST.timer_cnt_cry_0[5] CCU2D COUT Out 0.143 3.630 - timer_cnt_cry[6] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[7] CCU2D CIN In 0.000 3.630 - POWER_MANAGER_INST.timer_cnt_cry_0[7] CCU2D COUT Out 0.143 3.773 - timer_cnt_cry[8] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[9] CCU2D CIN In 0.000 3.773 - POWER_MANAGER_INST.timer_cnt_cry_0[9] CCU2D COUT Out 0.143 3.916 - timer_cnt_cry[10] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[11] CCU2D CIN In 0.000 3.916 - POWER_MANAGER_INST.timer_cnt_cry_0[11] CCU2D COUT Out 0.143 4.059 - timer_cnt_cry[12] Net - - - - 1 POWER_MANAGER_INST.timer_cnt_cry_0[13] CCU2D CIN In 0.000 4.059 - POWER_MANAGER_INST.timer_cnt_cry_0[13] CCU2D S1 Out 1.065 5.123 - timer_cnt_s[14] Net - - - - 1 POWER_MANAGER_INST.timer_cnt[14] FD1S3AX D In 0.000 5.123 - ========================================================================================================== ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------------- PIXEL_ADDR_DATA_FIFO_INST.PIXEL_ADDR_FIFO_INST.AND2_t9 System AND2 Z rden_i 0.000 -0.226 TFT_PIXEL_RGB_PIPELINER_INST.PIXEL_RGB_FIFO_INST.AND2_t9 System AND2 Z rden_i 0.000 -0.226 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_ADDR_FIFO_INST.AND2_t10 System AND2 Z wren_i 0.000 -0.226 TFT_PIXEL_RGB_PIPELINER_INST.PIXEL_RGB_FIFO_INST.AND2_t10 System AND2 Z wren_i 0.000 -0.226 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.AND2_t10 System AND2 Z rden_i 0.000 -0.226 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.AND2_t11 System AND2 Z wren_i 0.000 -0.226 TX_LVDS_71_INST.Inst2_ECLKSYNCA System ECLKSYNCA ECLKO eclko 0.000 1.283 TX_LVDS_71_INST.Inst3_CLKDIVC System CLKDIVC CDIVX sclk_sig 0.000 1.283 TFT_PIXEL_RGB_PIPELINER_INST.PIXEL_RGB_FIFO_INST.empty_cmp_0 System AGEB2 GE co0_2 0.000 1.283 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_ADDR_FIFO_INST.empty_cmp_0 System AGEB2 GE co0_2 0.000 1.283 ====================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------------------------- PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.empty_cmp_0 System AGEB2 CI cmp_ci 1.283 -0.226 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_ADDR_FIFO_INST.empty_cmp_0 System AGEB2 CI cmp_ci 1.283 -0.226 TFT_PIXEL_RGB_PIPELINER_INST.PIXEL_RGB_FIFO_INST.empty_cmp_0 System AGEB2 CI cmp_ci 1.283 -0.226 TFT_PIXEL_RGB_PIPELINER_INST.PIXEL_RGB_FIFO_INST.full_cmp_0 System AGEB2 CI cmp_ci_1 1.283 -0.226 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_ADDR_FIFO_INST.full_cmp_0 System AGEB2 CI cmp_ci_1 1.283 -0.226 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.full_cmp_0 System AGEB2 CI cmp_ci_1 1.283 -0.226 TX_LVDS_71_INST.Inst3_CLKDIVC System CLKDIVC CLKI eclko 1.283 1.283 TX_LVDS_71_INST.Inst4_ODDRX71A0 System ODDRX71A ECLK eclko 1.283 1.283 TX_LVDS_71_INST.Inst4_ODDRX71A0 System ODDRX71A SCLK sclk_sig 1.283 1.283 TX_LVDS_71_INST.Inst4_ODDRX71A1 System ODDRX71A ECLK eclko 1.283 1.283 ===================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1.283 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 1.283 - Propagation time: 1.509 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.226 Number of logic level(s): 1 Starting point: PIXEL_ADDR_DATA_FIFO_INST.PIXEL_ADDR_FIFO_INST.AND2_t9 / Z Ending point: PIXEL_ADDR_DATA_FIFO_INST.PIXEL_ADDR_FIFO_INST.empty_cmp_0 / CI The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------ PIXEL_ADDR_DATA_FIFO_INST.PIXEL_ADDR_FIFO_INST.AND2_t9 AND2 Z Out 0.000 0.000 - rden_i Net - - - - 39 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_ADDR_FIFO_INST.empty_cmp_ci_a FADD2B A1 In 0.000 0.000 - PIXEL_ADDR_DATA_FIFO_INST.PIXEL_ADDR_FIFO_INST.empty_cmp_ci_a FADD2B COUT Out 1.509 1.509 - cmp_ci Net - - - - 1 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_ADDR_FIFO_INST.empty_cmp_0 AGEB2 CI In 0.000 1.509 - ============================================================================================================================== Path information for path number 2: Requested Period: 1.283 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 1.283 - Propagation time: 1.509 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.226 Number of logic level(s): 1 Starting point: TFT_PIXEL_RGB_PIPELINER_INST.PIXEL_RGB_FIFO_INST.AND2_t9 / Z Ending point: TFT_PIXEL_RGB_PIPELINER_INST.PIXEL_RGB_FIFO_INST.empty_cmp_0 / CI The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) -------------------------------------------------------------------------------------------------------------------------------- TFT_PIXEL_RGB_PIPELINER_INST.PIXEL_RGB_FIFO_INST.AND2_t9 AND2 Z Out 0.000 0.000 - rden_i Net - - - - 33 TFT_PIXEL_RGB_PIPELINER_INST.PIXEL_RGB_FIFO_INST.empty_cmp_ci_a FADD2B A1 In 0.000 0.000 - TFT_PIXEL_RGB_PIPELINER_INST.PIXEL_RGB_FIFO_INST.empty_cmp_ci_a FADD2B COUT Out 1.509 1.509 - cmp_ci Net - - - - 1 TFT_PIXEL_RGB_PIPELINER_INST.PIXEL_RGB_FIFO_INST.empty_cmp_0 AGEB2 CI In 0.000 1.509 - ================================================================================================================================ Path information for path number 3: Requested Period: 1.283 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 1.283 - Propagation time: 1.509 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.226 Number of logic level(s): 1 Starting point: PIXEL_ADDR_DATA_FIFO_INST.PIXEL_ADDR_FIFO_INST.AND2_t10 / Z Ending point: PIXEL_ADDR_DATA_FIFO_INST.PIXEL_ADDR_FIFO_INST.full_cmp_0 / CI The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ----------------------------------------------------------------------------------------------------------------------------- PIXEL_ADDR_DATA_FIFO_INST.PIXEL_ADDR_FIFO_INST.AND2_t10 AND2 Z Out 0.000 0.000 - wren_i Net - - - - 18 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_ADDR_FIFO_INST.full_cmp_ci_a FADD2B A1 In 0.000 0.000 - PIXEL_ADDR_DATA_FIFO_INST.PIXEL_ADDR_FIFO_INST.full_cmp_ci_a FADD2B COUT Out 1.509 1.509 - cmp_ci_1 Net - - - - 1 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_ADDR_FIFO_INST.full_cmp_0 AGEB2 CI In 0.000 1.509 - ============================================================================================================================= Path information for path number 4: Requested Period: 1.283 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 1.283 - Propagation time: 1.509 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.226 Number of logic level(s): 1 Starting point: TFT_PIXEL_RGB_PIPELINER_INST.PIXEL_RGB_FIFO_INST.AND2_t10 / Z Ending point: TFT_PIXEL_RGB_PIPELINER_INST.PIXEL_RGB_FIFO_INST.full_cmp_0 / CI The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------- TFT_PIXEL_RGB_PIPELINER_INST.PIXEL_RGB_FIFO_INST.AND2_t10 AND2 Z Out 0.000 0.000 - wren_i Net - - - - 18 TFT_PIXEL_RGB_PIPELINER_INST.PIXEL_RGB_FIFO_INST.full_cmp_ci_a FADD2B A1 In 0.000 0.000 - TFT_PIXEL_RGB_PIPELINER_INST.PIXEL_RGB_FIFO_INST.full_cmp_ci_a FADD2B COUT Out 1.509 1.509 - cmp_ci_1 Net - - - - 1 TFT_PIXEL_RGB_PIPELINER_INST.PIXEL_RGB_FIFO_INST.full_cmp_0 AGEB2 CI In 0.000 1.509 - =============================================================================================================================== Path information for path number 5: Requested Period: 1.283 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 1.283 - Propagation time: 1.509 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : -0.226 Number of logic level(s): 1 Starting point: PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.AND2_t10 / Z Ending point: PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.empty_cmp_0 / CI The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------ PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.AND2_t10 AND2 Z Out 0.000 0.000 - rden_i Net - - - - 33 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.empty_cmp_ci_a FADD2B A1 In 0.000 0.000 - PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.empty_cmp_ci_a FADD2B COUT Out 1.509 1.509 - cmp_ci Net - - - - 1 PIXEL_ADDR_DATA_FIFO_INST.PIXEL_DATA_FIFO_INST.empty_cmp_0 AGEB2 CI In 0.000 1.509 - ============================================================================================================================== ##### END OF TIMING REPORT #####] Mapper successful! Process took 0h:00m:05s realtime, 0h:00m:05s cputime # Sun Sep 18 00:45:43 2011 ###########################################################]