Lattice Mapping Report File for Design Module 'tftsurfer_demo' Design Information Command line: map -a MachXO2 -p LCMXO2-1200HC -t TQFP144 -s 6 -oc Commercial image_image.ngd -o image_image_map.ncd -pr image_image.prf -mp image_image.mrp C:/work/LSCC/TFTSurfer/VHDL/tftsurfer_demo_v001/par_imager/image.lpf -c 0 Target Vendor: LATTICE Target Device: LCMXO2-1200HCTQFP144 Target Speed: 6 Mapper: xo2c00, version: Diamond_1.2_Production (92) Mapped on: 09/18/11 14:48:42 Design Summary Number of registers: 196 PFU registers: 153 PIO registers: 43 Number of SLICEs: 83 out of 640 (13%) SLICEs(logic/ROM): 83 out of 160 (52%) SLICEs(logic/ROM/RAM): 0 out of 480 (0%) As RAM: 0 out of 480 (0%) As Logic/ROM: 0 out of 480 (0%) Number of logic LUT4s: 84 Number of distributed RAM: 0 (0 LUT4s) Number of ripple logic: 26 (52 LUT4s) Number of shift registers: 0 Total number of LUT4s: 136 Number of PIO sites used: 52 out of 108 (48%) Number of block RAMs: 0 out of 7 (0%) Number of GSRs: 1 out of 1 (100%) EFB used : No JTAG used : No Readback used : No Oscillator used : No Startup used : No POR : On Bandgap : On Number of Power Controller: 0 out of 1 (0%) Number of Dynamic Bank Controller (BCINRD): 0 out of 4 (0%) Number of Dynamic Bank Controller (BCLVDSO): 0 out of 1 (0%) Number of DCCA: 0 out of 8 (0%) Number of DCMA: 0 out of 2 (0%) Number of PLLs: 0 out of 1 (0%) Number of DQSDLLs: 0 out of 2 (0%) Number of CLKDIVC: 0 out of 4 (0%) Number of ECLKSYNCA: 0 out of 4 (0%) Number of ECLKBRIDGECS: 0 out of 2 (0%) Notes:- 1. Total number of LUT4s = (Number of logic LUT4s) + 2*(Number of distributed RAMs) + 2*(Number of ripple logic) 2. Number of logic LUT4s does not include count of distributed RAM and ripple logic. Number of clocks: 3 Net tft_clk_c: 126 loads, 90 rising, 36 falling (Driver: PIO tft_clk ) Net demo_start_c: 1 loads, 1 rising, 0 falling (Driver: PIO demo_start ) Net spi_q_c: 1 loads, 1 rising, 0 falling (Driver: PIO spi_q ) Number of Clock Enables: 15 Net SPI_FLASH_READER_INST_un1_rst_d_cnt_0_sqmuxa_0_i: 1 loads, 0 LSLICEs Net SPI_FLASH_READER_INST/spi_byte_cnte_0_i: 11 loads, 11 LSLICEs Net SPI_FLASH_READER_INST/rgb_byte_0_sqmuxa: 3 loads, 3 LSLICEs Net SPI_FLASH_READER_INST/N_120_0_i: 1 loads, 1 LSLICEs Net SPI_FLASH_READER_INST_spi_q_sr_en: 5 loads, 4 LSLICEs Net SPI_FLASH_READER_INST/un1_spi_rd_st_4_0_i: 1 loads, 1 LSLICEs Net SPI_FLASH_READER_INST/un6_spi_clk_in_0_i: 8 loads, 8 LSLICEs Net SPI_FLASH_READER_INST/un1_spi_rd_st_3_0_i: 1 loads, 1 LSLICEs Net img_start_move_sig: 4 loads, 4 LSLICEs Net IMG_MOVER_VIEWER_INST/move_view_st_RNILUSR_7: 3 loads, 3 LSLICEs Net IMG_MOVER_VIEWER_INST/move_view_st_RNIJUSR_5: 3 loads, 3 LSLICEs Net IMG_MOVER_VIEWER_INST/move_view_st_RNIHUSR_3: 3 loads, 3 LSLICEs Net IMG_MOVER_VIEWER_INST/pixel_addre_0_i: 12 loads, 12 LSLICEs Net IMG_MOVER_VIEWER_INST_move_view_st_ns_3: 2 loads, 0 LSLICEs Net MICRO_EMULATOR_INST/img_nr_cnte_0_i: 2 loads, 2 LSLICEs Number of local set/reset loads for net sys_rst_c merged into GSR: 167 Number of LSRs: 1 Net SPI_FLASH_READER_INST/rst_q_cnt: 2 loads, 2 LSLICEs Number of nets driven by tri-state buffers: 0 Top 10 highest fanout non-clock nets: Net GND: 44 loads Net spi_start_rd_sig_i: 44 loads Net spi_start_rd_sig: 24 loads Net IMG_MOVER_VIEWER_INST/pixel_addre_0_i: 12 loads Net SPI_FLASH_READER_INST/spi_byte_cnte_0_i: 11 loads Net spi_end_rd_sig: 10 loads Net spi_byte_en_sig: 9 loads Net img_start_move_sig: 8 loads Net SPI_FLASH_READER_INST/un6_spi_clk_in_0_i: 8 loads Net img_nr_sig_0: 7 loads Number of warnings: 1 Number of errors: 0 Design Errors/Warnings WARNING: Using local reset signal 'sys_rst_c' to infer global GSR net. IO (PIO) Attributes +---------------------+-----------+-----------+------------+ | IO Name | Direction | Levelmode | IO | | | | IO_TYPE | Register | +---------------------+-----------+-----------+------------+ | test_pt | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | sys_rst | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | spi_q | INPUT | LVCMOS25 | IN | +---------------------+-----------+-----------+------------+ | spi_d | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | spi_clk | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | spi_csn | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_rgb_15 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_rgb_14 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_rgb_13 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_rgb_12 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_rgb_11 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_rgb_10 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_rgb_9 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_rgb_8 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_rgb_7 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_rgb_6 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_rgb_5 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_rgb_4 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_rgb_3 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_rgb_2 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_rgb_1 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_rgb_0 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_21 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_20 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_19 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_18 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_17 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_16 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_15 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_14 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_13 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_12 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_11 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_10 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_9 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_8 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_7 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_6 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_5 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_4 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_3 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_2 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_1 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_add_0 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | fifo_wr_req | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | tft_sect_2 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | tft_sect_1 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | tft_sect_0 | OUTPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ | tft_bank_1 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | tft_bank_0 | OUTPUT | LVCMOS25 | OUT | +---------------------+-----------+-----------+------------+ | demo_start | INPUT | LVCMOS25 | IN | +---------------------+-----------+-----------+------------+ | tft_clk | INPUT | LVCMOS25 | | +---------------------+-----------+-----------+------------+ Removed logic Signal IMG_MOVER_VIEWER_INST/IMG_SPI_SECTOR_ROM_INST/qdataout5_ffin was merged into signal img_nr_sig_0 Signal IMG_MOVER_VIEWER_INST/IMG_SPI_SECTOR_ROM_INST/qdataout6_ffin was merged into signal img_nr_sig_1 Signal SPI_FLASH_READER_INST_spi_csn_CN was merged into signal tft_clk_c Signal IMG_MOVER_VIEWER_INST/pixel_addr_s_0_S1_21 undriven or does not drive anything - clipped. Signal IMG_MOVER_VIEWER_INST/pixel_addr_s_0_COUT_21 undriven or does not drive anything - clipped. Signal IMG_MOVER_VIEWER_INST/pixel_addr_cry_0_S0_0 undriven or does not drive anything - clipped. Signal SPI_FLASH_READER_INST/d_cnt_cry_0_S0_0 undriven or does not drive anything - clipped. Signal SPI_FLASH_READER_INST/d_cnt_cry_0_COUT_3 undriven or does not drive anything - clipped. Signal SPI_FLASH_READER_INST/spi_byte_cnt_cry_0_S0_0 undriven or does not drive anything - clipped. Signal SPI_FLASH_READER_INST/spi_byte_cnt_cry_0_COUT_19 undriven or does not drive anything - clipped. Block IMG_MOVER_VIEWER_INST/IMG_SPI_SECTOR_ROM_INST/mem_0_5 was optimized away. Block IMG_MOVER_VIEWER_INST/IMG_SPI_SECTOR_ROM_INST/mem_0_6 was optimized away. Block SPI_FLASH_READER_INST/spi_d_sr_en_CN was optimized away. Memory Usage GSR Usage --------- GSR Component: The local reset signal 'sys_rst_c' of the design has been inferred as Global Set Reset (GSR). The reset signal used for GSR control is 'sys_rst_c'. GSR Property: The design components with GSR property set to ENABLED will respond to global set reset while the components with GSR property set to DISABLED will not. Run Time and Memory Usage ------------------------- Total CPU Time: 0 secs Total REAL Time: 0 secs Peak Memory Usage: 29 MB Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved.