-------------------------------------------------------------------------------- Lattice TRACE Report - Hold Sat Sep 17 22:58:27 2011 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design file: tftsurfer_top Device,speed: LCMXO2-1200HC,M Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "sys_clk_sig_c" 130.000000 MHz ; 30 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.134ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MONSTER_MANAGER_INST/sys_data_in_11 (from sys_clk_sig_c +) Destination: FF Data in SDRAM_CTRL_INST/sdram_dq_reg_CR15_ram_1/RAM1 (to sys_clk_sig_c +) FF SDRAM_CTRL_INST/sdram_dq_reg_CR15_ram_1/RAM1 Delay: 0.263ns (49.8% logic, 50.2% route), 2 logic levels. Constraint Details: 0.263ns physical path delay SLICE_73 to SLICE_113 meets 0.129ns WD_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.129ns) by 0.134ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R9C11D.CLK to R9C11D.Q1 SLICE_73 (from sys_clk_sig_c) ROUTE 1 0.132 R9C11D.Q1 to R7C11C.D1 sys_data_in_sig_11 ZERO_DEL --- 0.000 R7C11C.D1 to R7C11C.WDO3 SDRAM_CTRL_INST/sdram_dq_reg_CR15_ram_1/SLICE_111 ROUTE 1 0.000 R7C11C.WDO3 to R7C11B.WD1 SDRAM_CTRL_INST/sdram_dq_reg_CR15_ram_1/WD3_INT (to sys_clk_sig_c) -------- 0.263 (49.8% logic, 50.2% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 0.582ns LPLL.CLKOP to R9C11D.CLK Destination Clock: Delay Connection 0.582ns LPLL.CLKOP to R7C11B.WCK Passed: The following path meets requirements by 0.208ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MONSTER_MANAGER_INST/sys_data_in_12 (from sys_clk_sig_c +) Destination: FF Data in SDRAM_CTRL_INST/sdram_dq_reg_CR15_ram_2/RAM0 (to sys_clk_sig_c +) FF SDRAM_CTRL_INST/sdram_dq_reg_CR15_ram_2/RAM0 Delay: 0.337ns (38.9% logic, 61.1% route), 2 logic levels. Constraint Details: 0.337ns physical path delay SLICE_71 to SLICE_109 meets 0.129ns WD_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.129ns) by 0.208ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R9C11A.CLK to R9C11A.Q0 SLICE_71 (from sys_clk_sig_c) ROUTE 1 0.206 R9C11A.Q0 to R8C11C.A1 sys_data_in_sig_12 ZERO_DEL --- 0.000 R8C11C.A1 to R8C11C.WDO0 SDRAM_CTRL_INST/sdram_dq_reg_CR15_ram_2/SLICE_108 ROUTE 1 0.000 R8C11C.WDO0 to R8C11A.WD0 SDRAM_CTRL_INST/sdram_dq_reg_CR15_ram_2/WD0_INT (to sys_clk_sig_c) -------- 0.337 (38.9% logic, 61.1% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 0.582ns LPLL.CLKOP to R9C11A.CLK Destination Clock: Delay Connection 0.582ns LPLL.CLKOP to R8C11A.WCK Passed: The following path meets requirements by 0.210ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/FF_73 (from sys_clk_sig_c +) Destination: FF Data in TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_2/RAM0 (to sys_clk_sig_c +) FF TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_2/RAM0 Delay: 0.339ns (38.6% logic, 61.4% route), 2 logic levels. Constraint Details: 0.339ns physical path delay SLICE_610 to TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_2.23 meets 0.129ns WAD_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.129ns) by 0.210ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R8C16D.CLK to R8C16D.Q1 SLICE_610 (from sys_clk_sig_c) ROUTE 4 0.208 R8C16D.Q1 to R8C16C.A0 TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/wptr_0 ZERO_DEL --- 0.000 R8C16C.A0 to R8C16C.WADO0 TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_2.24 ROUTE 2 0.000 R8C16C.WADO0 to R8C16A.WAD0 TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_2/WAD0_INT (to sys_clk_sig_c) -------- 0.339 (38.6% logic, 61.4% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 0.582ns LPLL.CLKOP to R8C16D.CLK Destination Clock: Delay Connection 0.582ns LPLL.CLKOP to R8C16A.WCK Passed: The following path meets requirements by 0.210ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/FF_73 (from sys_clk_sig_c +) Destination: FF Data in TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_2/RAM1 (to sys_clk_sig_c +) FF TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_2/RAM1 Delay: 0.339ns (38.6% logic, 61.4% route), 2 logic levels. Constraint Details: 0.339ns physical path delay SLICE_610 to TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_2 meets 0.129ns WAD_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.129ns) by 0.210ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R8C16D.CLK to R8C16D.Q1 SLICE_610 (from sys_clk_sig_c) ROUTE 4 0.208 R8C16D.Q1 to R8C16C.A0 TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/wptr_0 ZERO_DEL --- 0.000 R8C16C.A0 to R8C16C.WADO0 TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_2.24 ROUTE 2 0.000 R8C16C.WADO0 to R8C16B.WAD0 TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_2/WAD0_INT (to sys_clk_sig_c) -------- 0.339 (38.6% logic, 61.4% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 0.582ns LPLL.CLKOP to R8C16D.CLK Destination Clock: Delay Connection 0.582ns LPLL.CLKOP to R8C16B.WCK Passed: The following path meets requirements by 0.244ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q MONSTER_MANAGER_INST/tft_sdram_red_1 (from sys_clk_sig_c +) Destination: FF Data in TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_0/RAM0 (to sys_clk_sig_c +) FF TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_0/RAM0 Delay: 0.373ns (35.1% logic, 64.9% route), 2 logic levels. Constraint Details: 0.373ns physical path delay SLICE_106 to TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_0 meets 0.129ns WD_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.129ns) by 0.244ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R8C14A.CLK to R8C14A.Q0 SLICE_106 (from sys_clk_sig_c) ROUTE 1 0.242 R8C14A.Q0 to R7C14C.A1 tft_sdram_red_in_sig_1 ZERO_DEL --- 0.000 R7C14C.A1 to R7C14C.WDO0 TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_0.19 ROUTE 1 0.000 R7C14C.WDO0 to R7C14A.WD0 TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_0/WD0_INT (to sys_clk_sig_c) -------- 0.373 (35.1% logic, 64.9% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 0.582ns LPLL.CLKOP to R8C14A.CLK Destination Clock: Delay Connection 0.582ns LPLL.CLKOP to R7C14A.WCK Passed: The following path meets requirements by 0.252ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MONSTER_MANAGER_INST/tft_sdram_green_5 (from sys_clk_sig_c +) Destination: FF Data in TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_1/RAM1 (to sys_clk_sig_c +) FF TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_1/RAM1 Delay: 0.381ns (34.4% logic, 65.6% route), 2 logic levels. Constraint Details: 0.381ns physical path delay SLICE_47 to TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_1.22 meets 0.129ns WD_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.129ns) by 0.252ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R7C19A.CLK to R7C19A.Q0 SLICE_47 (from sys_clk_sig_c) ROUTE 1 0.250 R7C19A.Q0 to R7C16C.C1 tft_sdram_green_in_sig_5 ZERO_DEL --- 0.000 R7C16C.C1 to R7C16C.WDO2 TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_1.21 ROUTE 1 0.000 R7C16C.WDO2 to R7C16B.WD0 TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_1/WD2_INT (to sys_clk_sig_c) -------- 0.381 (34.4% logic, 65.6% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 0.582ns LPLL.CLKOP to R7C19A.CLK Destination Clock: Delay Connection 0.582ns LPLL.CLKOP to R7C16B.WCK Passed: The following path meets requirements by 0.263ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3/RAM1 (from tft_clk_sig_c +) Destination: FF Data in PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/FF_42 (to sys_clk_sig_c +) Delay: 0.248ns (100.0% logic, 0.0% route), 1 logic levels. Constraint Details: 0.248ns physical path delay PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3 to PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3 meets -0.015ns DIN_HLD and (delay constraint based on source clock period of 26.923ns and destination clock period of 7.692ns) 0.000ns delay constraint less 0.000ns skew less 0.000ns feedback compensation requirement (totaling -0.015ns) by 0.263ns Physical Path Details: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 0.248 R8C12B.WCK to R8C12B.F1 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3 (from tft_clk_sig_c) ROUTE 1 0.000 R8C12B.F1 to R8C12B.DI1 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/rdataout11 (to sys_clk_sig_c) -------- 0.248 (100.0% logic, 0.0% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 0.582 LPLL.CLKOS3 to R8C12B.WCK tft_clk_sig_c -------- 1.224 (33.4% logic, 66.6% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.582 LPLL.CLKOP to R8C12B.CLK sys_clk_sig_c -------- 1.224 (33.4% logic, 66.6% route), 2 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 0.263ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_4/RAM0 (from tft_clk_sig_c +) Destination: FF Data in PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/FF_54 (to sys_clk_sig_c +) Delay: 0.248ns (100.0% logic, 0.0% route), 1 logic levels. Constraint Details: 0.248ns physical path delay PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_4 to PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_4 meets -0.015ns DIN_HLD and (delay constraint based on source clock period of 26.923ns and destination clock period of 7.692ns) 0.000ns delay constraint less 0.000ns skew less 0.000ns feedback compensation requirement (totaling -0.015ns) by 0.263ns Physical Path Details: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 0.248 R10C11A.WCK to R10C11A.F1 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_4 (from tft_clk_sig_c) ROUTE 1 0.000 R10C11A.F1 to R10C11A.DI1 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/rdataout5 (to sys_clk_sig_c) -------- 0.248 (100.0% logic, 0.0% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 0.582 LPLL.CLKOS3 to R10C11A.WCK tft_clk_sig_c -------- 1.224 (33.4% logic, 66.6% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.582 LPLL.CLKOP to R10C11A.CLK sys_clk_sig_c -------- 1.224 (33.4% logic, 66.6% route), 2 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 0.263ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_4/RAM1 (from tft_clk_sig_c +) Destination: FF Data in PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/FF_52 (to sys_clk_sig_c +) Delay: 0.248ns (100.0% logic, 0.0% route), 1 logic levels. Constraint Details: 0.248ns physical path delay PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_4.8 to PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_4.8 meets -0.015ns DIN_HLD and (delay constraint based on source clock period of 26.923ns and destination clock period of 7.692ns) 0.000ns delay constraint less 0.000ns skew less 0.000ns feedback compensation requirement (totaling -0.015ns) by 0.263ns Physical Path Details: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 0.248 R10C11B.WCK to R10C11B.F0 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_4.8 (from tft_clk_sig_c) ROUTE 1 0.000 R10C11B.F0 to R10C11B.DI0 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/rdataout6 (to sys_clk_sig_c) -------- 0.248 (100.0% logic, 0.0% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 0.582 LPLL.CLKOS3 to R10C11B.WCK tft_clk_sig_c -------- 1.224 (33.4% logic, 66.6% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.582 LPLL.CLKOP to R10C11B.CLK sys_clk_sig_c -------- 1.224 (33.4% logic, 66.6% route), 2 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 0.263ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: Sync_RAM Q PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_0/RAM0 (from tft_clk_sig_c +) Destination: FF Data in PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/FF_24 (to sys_clk_sig_c +) Delay: 0.248ns (100.0% logic, 0.0% route), 1 logic levels. Constraint Details: 0.248ns physical path delay PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_0.0 to PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_0.0 meets -0.015ns DIN_HLD and (delay constraint based on source clock period of 26.923ns and destination clock period of 7.692ns) 0.000ns delay constraint less 0.000ns skew less 0.000ns feedback compensation requirement (totaling -0.015ns) by 0.263ns Physical Path Details: Name Fanout Delay (ns) Site Resource CLKTOF_DEL --- 0.248 R10C10A.WCK to R10C10A.F0 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_0.0 (from tft_clk_sig_c) ROUTE 1 0.000 R10C10A.F0 to R10C10A.DI0 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/rdataout20 (to sys_clk_sig_c) -------- 0.248 (100.0% logic, 0.0% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 0.582 LPLL.CLKOS3 to R10C10A.WCK tft_clk_sig_c -------- 1.224 (33.4% logic, 66.6% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.582 LPLL.CLKOP to R10C10A.CLK sys_clk_sig_c -------- 1.224 (33.4% logic, 66.6% route), 2 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. ================================================================================ Preference: FREQUENCY NET "TX_LVDS_71_INST/eclko" 130.000000 MHz ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "TX_LVDS_71_INST/sclk_sig" 38.000000 MHz ; 19 items scored, 8 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 0.095ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_TIMING_CTRL_INST/tft_test_red_4 (from tft_clk_sig_c +) Destination: FF Data in TX_LVDS_71_INST/Inst4_ODDRX71A0 (to TX_LVDS_71_INST/sclk_sig +) Delay: 0.298ns (44.0% logic, 56.0% route), 1 logic levels. Constraint Details: 0.298ns physical path delay TFT_TIMING_CTRL_INST/SLICE_714 to tft_data0_MGIOL exceeds -0.023ns DO_HLD and (delay constraint based on source clock period of 26.923ns and destination clock period of 26.315ns) 0.000ns delay constraint less -0.416ns skew less 0.000ns feedback compensation requirement (totaling 0.393ns) by 0.095ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R2C17C.CLK to R2C17C.Q1 TFT_TIMING_CTRL_INST/SLICE_714 (from tft_clk_sig_c) ROUTE 1 0.167 R2C17C.Q1 to IOL_T17A.TXD4 tft_red_sig_4 (to TX_LVDS_71_INST/sclk_sig) -------- 0.298 (44.0% logic, 56.0% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Source Clock path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 0.582 LPLL.CLKOS3 to R2C17C.CLK tft_clk_sig_c -------- 1.224 (33.4% logic, 66.6% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.187 LPLL.CLKOP to *LKSYNC0.ECLKI sys_clk_sig_c C2OUT_DEL --- 0.000 *LKSYNC0.ECLKI to *LKSYNC0.ECLKO TX_LVDS_71_INST/Inst2_ECLKSYNCA ROUTE 6 0.000 *LKSYNC0.ECLKO to TCLKDIV0.CLKI TX_LVDS_71_INST/eclko CLKOUT_DEL --- 0.128 TCLKDIV0.CLKI to TCLKDIV0.CDIVX TX_LVDS_71_INST/Inst3_CLKDIVC ROUTE 5 0.683 TCLKDIV0.CDIVX to IOL_T17A.CLK TX_LVDS_71_INST/sclk_sig -------- 1.640 (32.7% logic, 67.3% route), 4 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Error: The following path exceeds requirements by 0.095ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_TIMING_CTRL_INST/tft_test_blue_5 (from tft_clk_sig_c +) Destination: FF Data in TX_LVDS_71_INST/Inst4_ODDRX71A2 (to TX_LVDS_71_INST/sclk_sig +) Delay: 0.298ns (44.0% logic, 56.0% route), 1 logic levels. Constraint Details: 0.298ns physical path delay TFT_TIMING_CTRL_INST/SLICE_764 to tft_data2_MGIOL exceeds -0.023ns DO_HLD and (delay constraint based on source clock period of 26.923ns and destination clock period of 26.315ns) 0.000ns delay constraint less -0.416ns skew less 0.000ns feedback compensation requirement (totaling 0.393ns) by 0.095ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R2C15D.CLK to R2C15D.Q0 TFT_TIMING_CTRL_INST/SLICE_764 (from tft_clk_sig_c) ROUTE 1 0.167 R2C15D.Q0 to IOL_T15A.TXD5 tft_blue_sig_5 (to TX_LVDS_71_INST/sclk_sig) -------- 0.298 (44.0% logic, 56.0% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Source Clock path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 0.582 LPLL.CLKOS3 to R2C15D.CLK tft_clk_sig_c -------- 1.224 (33.4% logic, 66.6% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.187 LPLL.CLKOP to *LKSYNC0.ECLKI sys_clk_sig_c C2OUT_DEL --- 0.000 *LKSYNC0.ECLKI to *LKSYNC0.ECLKO TX_LVDS_71_INST/Inst2_ECLKSYNCA ROUTE 6 0.000 *LKSYNC0.ECLKO to TCLKDIV0.CLKI TX_LVDS_71_INST/eclko CLKOUT_DEL --- 0.128 TCLKDIV0.CLKI to TCLKDIV0.CDIVX TX_LVDS_71_INST/Inst3_CLKDIVC ROUTE 5 0.683 TCLKDIV0.CDIVX to IOL_T15A.CLK TX_LVDS_71_INST/sclk_sig -------- 1.640 (32.7% logic, 67.3% route), 4 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Error: The following path exceeds requirements by 0.094ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_TIMING_CTRL_INST/tft_test_blue_6 (from tft_clk_sig_c +) Destination: FF Data in TX_LVDS_71_INST/Inst4_ODDRX71A2 (to TX_LVDS_71_INST/sclk_sig +) Delay: 0.299ns (43.8% logic, 56.2% route), 1 logic levels. Constraint Details: 0.299ns physical path delay TFT_TIMING_CTRL_INST/SLICE_710 to tft_data2_MGIOL exceeds -0.023ns DO_HLD and (delay constraint based on source clock period of 26.923ns and destination clock period of 26.315ns) 0.000ns delay constraint less -0.416ns skew less 0.000ns feedback compensation requirement (totaling 0.393ns) by 0.094ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R2C15B.CLK to R2C15B.Q1 TFT_TIMING_CTRL_INST/SLICE_710 (from tft_clk_sig_c) ROUTE 1 0.168 R2C15B.Q1 to IOL_T15A.TXD4 tft_blue_sig_6 (to TX_LVDS_71_INST/sclk_sig) -------- 0.299 (43.8% logic, 56.2% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Source Clock path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 0.582 LPLL.CLKOS3 to R2C15B.CLK tft_clk_sig_c -------- 1.224 (33.4% logic, 66.6% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.187 LPLL.CLKOP to *LKSYNC0.ECLKI sys_clk_sig_c C2OUT_DEL --- 0.000 *LKSYNC0.ECLKI to *LKSYNC0.ECLKO TX_LVDS_71_INST/Inst2_ECLKSYNCA ROUTE 6 0.000 *LKSYNC0.ECLKO to TCLKDIV0.CLKI TX_LVDS_71_INST/eclko CLKOUT_DEL --- 0.128 TCLKDIV0.CLKI to TCLKDIV0.CDIVX TX_LVDS_71_INST/Inst3_CLKDIVC ROUTE 5 0.683 TCLKDIV0.CDIVX to IOL_T15A.CLK TX_LVDS_71_INST/sclk_sig -------- 1.640 (32.7% logic, 67.3% route), 4 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Error: The following path exceeds requirements by 0.013ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_TIMING_CTRL_INST/tft_test_blue_4 (from tft_clk_sig_c +) Destination: FF Data in TX_LVDS_71_INST/Inst4_ODDRX71A2 (to TX_LVDS_71_INST/sclk_sig +) Delay: 0.380ns (34.5% logic, 65.5% route), 1 logic levels. Constraint Details: 0.380ns physical path delay TFT_TIMING_CTRL_INST/SLICE_764 to tft_data2_MGIOL exceeds -0.023ns DO_HLD and (delay constraint based on source clock period of 26.923ns and destination clock period of 26.315ns) 0.000ns delay constraint less -0.416ns skew less 0.000ns feedback compensation requirement (totaling 0.393ns) by 0.013ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R2C15D.CLK to R2C15D.Q1 TFT_TIMING_CTRL_INST/SLICE_764 (from tft_clk_sig_c) ROUTE 1 0.249 R2C15D.Q1 to IOL_T15A.TXD6 tft_blue_sig_4 (to TX_LVDS_71_INST/sclk_sig) -------- 0.380 (34.5% logic, 65.5% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Source Clock path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 0.582 LPLL.CLKOS3 to R2C15D.CLK tft_clk_sig_c -------- 1.224 (33.4% logic, 66.6% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.187 LPLL.CLKOP to *LKSYNC0.ECLKI sys_clk_sig_c C2OUT_DEL --- 0.000 *LKSYNC0.ECLKI to *LKSYNC0.ECLKO TX_LVDS_71_INST/Inst2_ECLKSYNCA ROUTE 6 0.000 *LKSYNC0.ECLKO to TCLKDIV0.CLKI TX_LVDS_71_INST/eclko CLKOUT_DEL --- 0.128 TCLKDIV0.CLKI to TCLKDIV0.CDIVX TX_LVDS_71_INST/Inst3_CLKDIVC ROUTE 5 0.683 TCLKDIV0.CDIVX to IOL_T15A.CLK TX_LVDS_71_INST/sclk_sig -------- 1.640 (32.7% logic, 67.3% route), 4 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Error: The following path exceeds requirements by 0.013ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_TIMING_CTRL_INST/tft_test_red_6 (from tft_clk_sig_c +) Destination: FF Data in TX_LVDS_71_INST/Inst4_ODDRX71A0 (to TX_LVDS_71_INST/sclk_sig +) Delay: 0.380ns (34.5% logic, 65.5% route), 1 logic levels. Constraint Details: 0.380ns physical path delay TFT_TIMING_CTRL_INST/SLICE_397 to tft_data0_MGIOL exceeds -0.023ns DO_HLD and (delay constraint based on source clock period of 26.923ns and destination clock period of 26.315ns) 0.000ns delay constraint less -0.416ns skew less 0.000ns feedback compensation requirement (totaling 0.393ns) by 0.013ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C17B.CLK to R3C17B.Q0 TFT_TIMING_CTRL_INST/SLICE_397 (from tft_clk_sig_c) ROUTE 1 0.249 R3C17B.Q0 to IOL_T17A.TXD2 tft_red_sig_6 (to TX_LVDS_71_INST/sclk_sig) -------- 0.380 (34.5% logic, 65.5% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Source Clock path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 0.582 LPLL.CLKOS3 to R3C17B.CLK tft_clk_sig_c -------- 1.224 (33.4% logic, 66.6% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.187 LPLL.CLKOP to *LKSYNC0.ECLKI sys_clk_sig_c C2OUT_DEL --- 0.000 *LKSYNC0.ECLKI to *LKSYNC0.ECLKO TX_LVDS_71_INST/Inst2_ECLKSYNCA ROUTE 6 0.000 *LKSYNC0.ECLKO to TCLKDIV0.CLKI TX_LVDS_71_INST/eclko CLKOUT_DEL --- 0.128 TCLKDIV0.CLKI to TCLKDIV0.CDIVX TX_LVDS_71_INST/Inst3_CLKDIVC ROUTE 5 0.683 TCLKDIV0.CDIVX to IOL_T17A.CLK TX_LVDS_71_INST/sclk_sig -------- 1.640 (32.7% logic, 67.3% route), 4 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Error: The following path exceeds requirements by 0.013ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_TIMING_CTRL_INST/tft_test_red_5 (from tft_clk_sig_c +) Destination: FF Data in TX_LVDS_71_INST/Inst4_ODDRX71A0 (to TX_LVDS_71_INST/sclk_sig +) Delay: 0.380ns (34.5% logic, 65.5% route), 1 logic levels. Constraint Details: 0.380ns physical path delay TFT_TIMING_CTRL_INST/SLICE_714 to tft_data0_MGIOL exceeds -0.023ns DO_HLD and (delay constraint based on source clock period of 26.923ns and destination clock period of 26.315ns) 0.000ns delay constraint less -0.416ns skew less 0.000ns feedback compensation requirement (totaling 0.393ns) by 0.013ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R2C17C.CLK to R2C17C.Q0 TFT_TIMING_CTRL_INST/SLICE_714 (from tft_clk_sig_c) ROUTE 1 0.249 R2C17C.Q0 to IOL_T17A.TXD3 tft_red_sig_5 (to TX_LVDS_71_INST/sclk_sig) -------- 0.380 (34.5% logic, 65.5% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Source Clock path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 0.582 LPLL.CLKOS3 to R2C17C.CLK tft_clk_sig_c -------- 1.224 (33.4% logic, 66.6% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.187 LPLL.CLKOP to *LKSYNC0.ECLKI sys_clk_sig_c C2OUT_DEL --- 0.000 *LKSYNC0.ECLKI to *LKSYNC0.ECLKO TX_LVDS_71_INST/Inst2_ECLKSYNCA ROUTE 6 0.000 *LKSYNC0.ECLKO to TCLKDIV0.CLKI TX_LVDS_71_INST/eclko CLKOUT_DEL --- 0.128 TCLKDIV0.CLKI to TCLKDIV0.CDIVX TX_LVDS_71_INST/Inst3_CLKDIVC ROUTE 5 0.683 TCLKDIV0.CDIVX to IOL_T17A.CLK TX_LVDS_71_INST/sclk_sig -------- 1.640 (32.7% logic, 67.3% route), 4 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Error: The following path exceeds requirements by 0.013ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_TIMING_CTRL_INST/tft_test_blue_3 (from tft_clk_sig_c +) Destination: FF Data in TX_LVDS_71_INST/Inst4_ODDRX71A1 (to TX_LVDS_71_INST/sclk_sig +) Delay: 0.380ns (34.5% logic, 65.5% route), 1 logic levels. Constraint Details: 0.380ns physical path delay TFT_TIMING_CTRL_INST/SLICE_763 to tft_data1_MGIOL exceeds -0.023ns DO_HLD and (delay constraint based on source clock period of 26.923ns and destination clock period of 26.315ns) 0.000ns delay constraint less -0.416ns skew less 0.000ns feedback compensation requirement (totaling 0.393ns) by 0.013ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C16C.CLK to R3C16C.Q0 TFT_TIMING_CTRL_INST/SLICE_763 (from tft_clk_sig_c) ROUTE 1 0.249 R3C16C.Q0 to IOL_T16A.TXD0 tft_blue_sig_3 (to TX_LVDS_71_INST/sclk_sig) -------- 0.380 (34.5% logic, 65.5% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Source Clock path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 0.582 LPLL.CLKOS3 to R3C16C.CLK tft_clk_sig_c -------- 1.224 (33.4% logic, 66.6% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.187 LPLL.CLKOP to *LKSYNC0.ECLKI sys_clk_sig_c C2OUT_DEL --- 0.000 *LKSYNC0.ECLKI to *LKSYNC0.ECLKO TX_LVDS_71_INST/Inst2_ECLKSYNCA ROUTE 6 0.000 *LKSYNC0.ECLKO to TCLKDIV0.CLKI TX_LVDS_71_INST/eclko CLKOUT_DEL --- 0.128 TCLKDIV0.CLKI to TCLKDIV0.CDIVX TX_LVDS_71_INST/Inst3_CLKDIVC ROUTE 5 0.683 TCLKDIV0.CDIVX to IOL_T16A.CLK TX_LVDS_71_INST/sclk_sig -------- 1.640 (32.7% logic, 67.3% route), 4 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Error: The following path exceeds requirements by 0.011ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_TIMING_CTRL_INST/hdata_final_sr_0_10 (from tft_clk_sig_c +) Destination: FF Data in TX_LVDS_71_INST/Inst4_ODDRX71A2 (to TX_LVDS_71_INST/sclk_sig +) Delay: 0.382ns (34.3% logic, 65.7% route), 1 logic levels. Constraint Details: 0.382ns physical path delay TFT_TIMING_CTRL_INST/SLICE_747 to tft_data2_MGIOL exceeds -0.023ns DO_HLD and (delay constraint based on source clock period of 26.923ns and destination clock period of 26.315ns) 0.000ns delay constraint less -0.416ns skew less 0.000ns feedback compensation requirement (totaling 0.393ns) by 0.011ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R3C15D.CLK to R3C15D.Q0 TFT_TIMING_CTRL_INST/SLICE_747 (from tft_clk_sig_c) ROUTE 3 0.251 R3C15D.Q0 to IOL_T15A.TXD0 tft_dtmg_sig (to TX_LVDS_71_INST/sclk_sig) -------- 0.382 (34.3% logic, 65.7% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Source Clock path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 0.582 LPLL.CLKOS3 to R3C15D.CLK tft_clk_sig_c -------- 1.224 (33.4% logic, 66.6% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.187 LPLL.CLKOP to *LKSYNC0.ECLKI sys_clk_sig_c C2OUT_DEL --- 0.000 *LKSYNC0.ECLKI to *LKSYNC0.ECLKO TX_LVDS_71_INST/Inst2_ECLKSYNCA ROUTE 6 0.000 *LKSYNC0.ECLKO to TCLKDIV0.CLKI TX_LVDS_71_INST/eclko CLKOUT_DEL --- 0.128 TCLKDIV0.CLKI to TCLKDIV0.CDIVX TX_LVDS_71_INST/Inst3_CLKDIVC ROUTE 5 0.683 TCLKDIV0.CDIVX to IOL_T15A.CLK TX_LVDS_71_INST/sclk_sig -------- 1.640 (32.7% logic, 67.3% route), 4 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 0.015ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_TIMING_CTRL_INST/tft_test_red_3 (from tft_clk_sig_c +) Destination: FF Data in TX_LVDS_71_INST/Inst4_ODDRX71A0 (to TX_LVDS_71_INST/sclk_sig +) Delay: 0.408ns (32.1% logic, 67.9% route), 1 logic levels. Constraint Details: 0.408ns physical path delay TFT_TIMING_CTRL_INST/SLICE_395 to tft_data0_MGIOL meets -0.023ns DO_HLD and (delay constraint based on source clock period of 26.923ns and destination clock period of 26.315ns) 0.000ns delay constraint less -0.416ns skew less 0.000ns feedback compensation requirement (totaling 0.393ns) by 0.015ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R2C17A.CLK to R2C17A.Q1 TFT_TIMING_CTRL_INST/SLICE_395 (from tft_clk_sig_c) ROUTE 1 0.277 R2C17A.Q1 to IOL_T17A.TXD5 tft_red_sig_3 (to TX_LVDS_71_INST/sclk_sig) -------- 0.408 (32.1% logic, 67.9% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 0.582 LPLL.CLKOS3 to R2C17A.CLK tft_clk_sig_c -------- 1.224 (33.4% logic, 66.6% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.187 LPLL.CLKOP to *LKSYNC0.ECLKI sys_clk_sig_c C2OUT_DEL --- 0.000 *LKSYNC0.ECLKI to *LKSYNC0.ECLKO TX_LVDS_71_INST/Inst2_ECLKSYNCA ROUTE 6 0.000 *LKSYNC0.ECLKO to TCLKDIV0.CLKI TX_LVDS_71_INST/eclko CLKOUT_DEL --- 0.128 TCLKDIV0.CLKI to TCLKDIV0.CDIVX TX_LVDS_71_INST/Inst3_CLKDIVC ROUTE 5 0.683 TCLKDIV0.CDIVX to IOL_T17A.CLK TX_LVDS_71_INST/sclk_sig -------- 1.640 (32.7% logic, 67.3% route), 4 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 0.015ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_TIMING_CTRL_INST/tft_test_blue_7 (from tft_clk_sig_c +) Destination: FF Data in TX_LVDS_71_INST/Inst4_ODDRX71A2 (to TX_LVDS_71_INST/sclk_sig +) Delay: 0.408ns (32.1% logic, 67.9% route), 1 logic levels. Constraint Details: 0.408ns physical path delay TFT_TIMING_CTRL_INST/SLICE_710 to tft_data2_MGIOL meets -0.023ns DO_HLD and (delay constraint based on source clock period of 26.923ns and destination clock period of 26.315ns) 0.000ns delay constraint less -0.416ns skew less 0.000ns feedback compensation requirement (totaling 0.393ns) by 0.015ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R2C15B.CLK to R2C15B.Q0 TFT_TIMING_CTRL_INST/SLICE_710 (from tft_clk_sig_c) ROUTE 1 0.277 R2C15B.Q0 to IOL_T15A.TXD3 tft_blue_sig_7 (to TX_LVDS_71_INST/sclk_sig) -------- 0.408 (32.1% logic, 67.9% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 0.582 LPLL.CLKOS3 to R2C15B.CLK tft_clk_sig_c -------- 1.224 (33.4% logic, 66.6% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 0.409 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.233 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.187 LPLL.CLKOP to *LKSYNC0.ECLKI sys_clk_sig_c C2OUT_DEL --- 0.000 *LKSYNC0.ECLKI to *LKSYNC0.ECLKO TX_LVDS_71_INST/Inst2_ECLKSYNCA ROUTE 6 0.000 *LKSYNC0.ECLKO to TCLKDIV0.CLKI TX_LVDS_71_INST/eclko CLKOUT_DEL --- 0.128 TCLKDIV0.CLKI to TCLKDIV0.CDIVX TX_LVDS_71_INST/Inst3_CLKDIVC ROUTE 5 0.683 TCLKDIV0.CDIVX to IOL_T15A.CLK TX_LVDS_71_INST/sclk_sig -------- 1.640 (32.7% logic, 67.3% route), 4 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.635 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 0.635 (0.0% logic, 100.0% route), 1 logic levels. ================================================================================ Preference: FREQUENCY NET "tft_clk_sig_c" 37.142857 MHz ; 30 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.135ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/FF_75 (from tft_clk_sig_c +) Destination: FF Data in PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_0/RAM0 (to tft_clk_sig_c +) FF PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_0/RAM0 Delay: 0.264ns (49.6% logic, 50.4% route), 2 logic levels. Constraint Details: 0.264ns physical path delay SLICE_597 to PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_0.11 meets 0.129ns WAD_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.129ns) by 0.135ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R7C18A.CLK to R7C18A.Q1 SLICE_597 (from tft_clk_sig_c) ROUTE 4 0.133 R7C18A.Q1 to R8C18C.D0 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/wptr_3 ZERO_DEL --- 0.000 R8C18C.D0 to R8C18C.WADO3 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_0.12 ROUTE 2 0.000 R8C18C.WADO3 to R8C18A.WAD3 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_0/WAD3_INT (to tft_clk_sig_c) -------- 0.264 (49.6% logic, 50.4% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 0.582ns LPLL.CLKOS3 to R7C18A.CLK Destination Clock: Delay Connection 0.582ns LPLL.CLKOS3 to R8C18A.WCK Passed: The following path meets requirements by 0.135ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/FF_75 (from tft_clk_sig_c +) Destination: FF Data in PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_0/RAM1 (to tft_clk_sig_c +) FF PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_0/RAM1 Delay: 0.264ns (49.6% logic, 50.4% route), 2 logic levels. Constraint Details: 0.264ns physical path delay SLICE_597 to PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_0 meets 0.129ns WAD_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.129ns) by 0.135ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R7C18A.CLK to R7C18A.Q1 SLICE_597 (from tft_clk_sig_c) ROUTE 4 0.133 R7C18A.Q1 to R8C18C.D0 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/wptr_3 ZERO_DEL --- 0.000 R8C18C.D0 to R8C18C.WADO3 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_0.12 ROUTE 2 0.000 R8C18C.WADO3 to R8C18B.WAD3 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_0/WAD3_INT (to tft_clk_sig_c) -------- 0.264 (49.6% logic, 50.4% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 0.582ns LPLL.CLKOS3 to R7C18A.CLK Destination Clock: Delay Connection 0.582ns LPLL.CLKOS3 to R8C18B.WCK Passed: The following path meets requirements by 0.207ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SDRAM_TEST_GENERATOR_INST/sdram_fifo_wr_add_8 (from tft_clk_sig_c +) Destination: FF Data in PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3/RAM0 (to tft_clk_sig_c +) FF PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3/RAM0 Delay: 0.336ns (39.0% logic, 61.0% route), 2 logic levels. Constraint Details: 0.336ns physical path delay SLICE_659 to PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3.6 meets 0.129ns WD_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.129ns) by 0.207ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R8C12D.CLK to R8C12D.Q1 SLICE_659 (from tft_clk_sig_c) ROUTE 1 0.205 R8C12D.Q1 to R8C12C.A1 fifo_wr_add_sig_8 ZERO_DEL --- 0.000 R8C12C.A1 to R8C12C.WDO0 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3.5 ROUTE 1 0.000 R8C12C.WDO0 to R8C12A.WD0 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3/WD0_INT (to tft_clk_sig_c) -------- 0.336 (39.0% logic, 61.0% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 0.582ns LPLL.CLKOS3 to R8C12D.CLK Destination Clock: Delay Connection 0.582ns LPLL.CLKOS3 to R8C12A.WCK Passed: The following path meets requirements by 0.209ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SDRAM_TEST_GENERATOR_INST/sdram_fifo_wr_add_0 (from tft_clk_sig_c +) Destination: FF Data in PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_5/RAM0 (to tft_clk_sig_c +) FF PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_5/RAM0 Delay: 0.338ns (38.8% logic, 61.2% route), 2 logic levels. Constraint Details: 0.338ns physical path delay SDRAM_TEST_GENERATOR_INST/SLICE_362 to PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_5.9 meets 0.129ns WD_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.129ns) by 0.209ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R7C9A.CLK to R7C9A.Q1 SDRAM_TEST_GENERATOR_INST/SLICE_362 (from tft_clk_sig_c) ROUTE 1 0.207 R7C9A.Q1 to R8C9C.A1 fifo_wr_add_sig_0 ZERO_DEL --- 0.000 R8C9C.A1 to R8C9C.WDO0 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_5 ROUTE 1 0.000 R8C9C.WDO0 to R8C9A.WD0 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_5/WD0_INT (to tft_clk_sig_c) -------- 0.338 (38.8% logic, 61.2% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 0.582ns LPLL.CLKOS3 to R7C9A.CLK Destination Clock: Delay Connection 0.582ns LPLL.CLKOS3 to R8C9A.WCK Passed: The following path meets requirements by 0.215ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SDRAM_TEST_GENERATOR_INST/sdram_fifo_wr_add_7 (from tft_clk_sig_c +) Destination: FF Data in PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_4/RAM1 (to tft_clk_sig_c +) FF PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_4/RAM1 Delay: 0.344ns (38.1% logic, 61.9% route), 2 logic levels. Constraint Details: 0.344ns physical path delay SLICE_659 to PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_4.8 meets 0.129ns WD_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.129ns) by 0.215ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R8C12D.CLK to R8C12D.Q0 SLICE_659 (from tft_clk_sig_c) ROUTE 1 0.213 R8C12D.Q0 to R10C11C.D1 fifo_wr_add_sig_7 ZERO_DEL --- 0.000 R10C11C.D1 to R10C11C.WDO3 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_4.7 ROUTE 1 0.000 R10C11C.WDO3 to R10C11B.WD1 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_4/WD3_INT (to tft_clk_sig_c) -------- 0.344 (38.1% logic, 61.9% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 0.582ns LPLL.CLKOS3 to R8C12D.CLK Destination Clock: Delay Connection 0.582ns LPLL.CLKOS3 to R10C11B.WCK Passed: The following path meets requirements by 0.218ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SDRAM_TEST_GENERATOR_INST/sdram_fifo_wr_add_2 (from tft_clk_sig_c +) Destination: FF Data in PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_5/RAM1 (to tft_clk_sig_c +) FF PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_5/RAM1 Delay: 0.347ns (37.8% logic, 62.2% route), 2 logic levels. Constraint Details: 0.347ns physical path delay SLICE_629 to PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_5.10 meets 0.129ns WD_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.129ns) by 0.218ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R9C8A.CLK to R9C8A.Q1 SLICE_629 (from tft_clk_sig_c) ROUTE 1 0.216 R9C8A.Q1 to R8C9C.C1 fifo_wr_add_sig_2 ZERO_DEL --- 0.000 R8C9C.C1 to R8C9C.WDO2 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_5 ROUTE 1 0.000 R8C9C.WDO2 to R8C9B.WD0 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_5/WD2_INT (to tft_clk_sig_c) -------- 0.347 (37.8% logic, 62.2% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 0.582ns LPLL.CLKOS3 to R9C8A.CLK Destination Clock: Delay Connection 0.582ns LPLL.CLKOS3 to R8C9B.WCK Passed: The following path meets requirements by 0.220ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SDRAM_TEST_GENERATOR_INST/sdram_fifo_wr_add_1 (from tft_clk_sig_c +) Destination: FF Data in PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_5/RAM0 (to tft_clk_sig_c +) FF PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_5/RAM0 Delay: 0.349ns (37.5% logic, 62.5% route), 2 logic levels. Constraint Details: 0.349ns physical path delay SDRAM_TEST_GENERATOR_INST/SLICE_240 to PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_5.9 meets 0.129ns WD_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.129ns) by 0.220ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R8C8B.CLK to R8C8B.Q1 SDRAM_TEST_GENERATOR_INST/SLICE_240 (from tft_clk_sig_c) ROUTE 1 0.218 R8C8B.Q1 to R8C9C.B1 fifo_wr_add_sig_1 ZERO_DEL --- 0.000 R8C9C.B1 to R8C9C.WDO1 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_5 ROUTE 1 0.000 R8C9C.WDO1 to R8C9A.WD1 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_5/WD1_INT (to tft_clk_sig_c) -------- 0.349 (37.5% logic, 62.5% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 0.582ns LPLL.CLKOS3 to R8C8B.CLK Destination Clock: Delay Connection 0.582ns LPLL.CLKOS3 to R8C9A.WCK Passed: The following path meets requirements by 0.220ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SDRAM_TEST_GENERATOR_INST/sdram_fifo_wr_add_9 (from tft_clk_sig_c +) Destination: FF Data in PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3/RAM0 (to tft_clk_sig_c +) FF PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3/RAM0 Delay: 0.349ns (37.5% logic, 62.5% route), 2 logic levels. Constraint Details: 0.349ns physical path delay SLICE_660 to PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3.6 meets 0.129ns WD_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.129ns) by 0.220ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R8C13D.CLK to R8C13D.Q0 SLICE_660 (from tft_clk_sig_c) ROUTE 1 0.218 R8C13D.Q0 to R8C12C.B1 fifo_wr_add_sig_9 ZERO_DEL --- 0.000 R8C12C.B1 to R8C12C.WDO1 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3.5 ROUTE 1 0.000 R8C12C.WDO1 to R8C12A.WD1 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3/WD1_INT (to tft_clk_sig_c) -------- 0.349 (37.5% logic, 62.5% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 0.582ns LPLL.CLKOS3 to R8C13D.CLK Destination Clock: Delay Connection 0.582ns LPLL.CLKOS3 to R8C12A.WCK Passed: The following path meets requirements by 0.221ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SDRAM_TEST_GENERATOR_INST/sdram_fifo_wr_add_21 (from tft_clk_sig_c +) Destination: FF Data in PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_0/RAM0 (to tft_clk_sig_c +) FF PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_0/RAM0 Delay: 0.350ns (37.4% logic, 62.6% route), 2 logic levels. Constraint Details: 0.350ns physical path delay SLICE_652 to PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_0.0 meets 0.129ns WD_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.129ns) by 0.221ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R10C8B.CLK to R10C8B.Q1 SLICE_652 (from tft_clk_sig_c) ROUTE 1 0.219 R10C8B.Q1 to R10C10C.B1 fifo_wr_add_sig_21 ZERO_DEL --- 0.000 R10C10C.B1 to R10C10C.WDO1 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_0 ROUTE 1 0.000 R10C10C.WDO1 to R10C10A.WD1 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_0/WD1_INT (to tft_clk_sig_c) -------- 0.350 (37.4% logic, 62.6% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 0.582ns LPLL.CLKOS3 to R10C8B.CLK Destination Clock: Delay Connection 0.582ns LPLL.CLKOS3 to R10C10A.WCK Passed: The following path meets requirements by 0.243ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SDRAM_TEST_GENERATOR_INST/sdram_fifo_wr_add_19 (from tft_clk_sig_c +) Destination: FF Data in PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_1/RAM1 (to tft_clk_sig_c +) FF PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_1/RAM1 Delay: 0.372ns (35.2% logic, 64.8% route), 2 logic levels. Constraint Details: 0.372ns physical path delay SLICE_629 to PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_1.1 meets 0.129ns WD_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling 0.129ns) by 0.243ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R9C8A.CLK to R9C8A.Q0 SLICE_629 (from tft_clk_sig_c) ROUTE 1 0.241 R9C8A.Q0 to R9C10C.D1 fifo_wr_add_sig_19 ZERO_DEL --- 0.000 R9C10C.D1 to R9C10C.WDO3 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_1.2 ROUTE 1 0.000 R9C10C.WDO3 to R9C10B.WD1 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_1/WD3_INT (to tft_clk_sig_c) -------- 0.372 (35.2% logic, 64.8% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 0.582ns LPLL.CLKOS3 to R9C8A.CLK Destination Clock: Delay Connection 0.582ns LPLL.CLKOS3 to R9C10B.WCK ================================================================================ Preference: FREQUENCY NET "osch_clk_sig_inferred_clock" 2.080000 MHz ; 30 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.301ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q POWER_MANAGER_INST/pll_lock_reg0 (from osch_clk_sig_inferred_clock +) Destination: FF Data in POWER_MANAGER_INST/pll_lock_reg1 (to osch_clk_sig_inferred_clock +) Delay: 0.280ns (46.8% logic, 53.2% route), 1 logic levels. Constraint Details: 0.280ns physical path delay POWER_MANAGER_INST/SLICE_199 to POWER_MANAGER_INST/SLICE_200 meets -0.021ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.021ns) by 0.301ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R8C4D.CLK to R8C4D.Q1 POWER_MANAGER_INST/SLICE_199 (from osch_clk_sig_inferred_clock) ROUTE 1 0.149 R8C4D.Q1 to R8C4C.M1 POWER_MANAGER_INST/pll_lock_reg0 (to osch_clk_sig_inferred_clock) -------- 0.280 (46.8% logic, 53.2% route), 1 logic levels. Clock Skew Details: Source Clock: Delay Connection 1.663ns OSC.OSC to R8C4D.CLK Destination Clock: Delay Connection 1.663ns OSC.OSC to R8C4C.CLK Passed: The following path meets requirements by 0.305ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q POWER_MANAGER_INST/delay_st_6 (from osch_clk_sig_inferred_clock +) Destination: FF Data in POWER_MANAGER_INST/delay_st_5 (to osch_clk_sig_inferred_clock +) Delay: 0.284ns (46.1% logic, 53.9% route), 1 logic levels. Constraint Details: 0.284ns physical path delay POWER_MANAGER_INST/SLICE_197 to POWER_MANAGER_INST/SLICE_196 meets -0.021ns M_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.021ns) by 0.305ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R8C5B.CLK to R8C5B.Q0 POWER_MANAGER_INST/SLICE_197 (from osch_clk_sig_inferred_clock) ROUTE 2 0.153 R8C5B.Q0 to R8C4B.M1 POWER_MANAGER_INST/delay_st_6 (to osch_clk_sig_inferred_clock) -------- 0.284 (46.1% logic, 53.9% route), 1 logic levels. Clock Skew Details: Source Clock: Delay Connection 1.663ns OSC.OSC to R8C5B.CLK Destination Clock: Delay Connection 1.663ns OSC.OSC to R8C4B.CLK Passed: The following path meets requirements by 0.374ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q POWER_MANAGER_INST/delay_st_4 (from osch_clk_sig_inferred_clock +) Destination: FF Data in POWER_MANAGER_INST/delay_st_4 (to osch_clk_sig_inferred_clock +) Delay: 0.359ns (64.1% logic, 35.9% route), 2 logic levels. Constraint Details: 0.359ns physical path delay POWER_MANAGER_INST/SLICE_196 to POWER_MANAGER_INST/SLICE_196 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.374ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R8C4B.CLK to R8C4B.Q0 POWER_MANAGER_INST/SLICE_196 (from osch_clk_sig_inferred_clock) ROUTE 2 0.129 R8C4B.Q0 to R8C4B.A0 POWER_MANAGER_INST/delay_st_4 CTOF_DEL --- 0.099 R8C4B.A0 to R8C4B.F0 POWER_MANAGER_INST/SLICE_196 ROUTE 1 0.000 R8C4B.F0 to R8C4B.DI0 POWER_MANAGER_INST/delay_st_ns_0_i_2 (to osch_clk_sig_inferred_clock) -------- 0.359 (64.1% logic, 35.9% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 1.663ns OSC.OSC to R8C4B.CLK Destination Clock: Delay Connection 1.663ns OSC.OSC to R8C4B.CLK Passed: The following path meets requirements by 0.374ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q POWER_MANAGER_INST/delay_st_1 (from osch_clk_sig_inferred_clock +) Destination: FF Data in POWER_MANAGER_INST/delay_st_1 (to osch_clk_sig_inferred_clock +) Delay: 0.359ns (64.1% logic, 35.9% route), 2 logic levels. Constraint Details: 0.359ns physical path delay POWER_MANAGER_INST/SLICE_194 to POWER_MANAGER_INST/SLICE_194 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.374ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R8C6A.CLK to R8C6A.Q1 POWER_MANAGER_INST/SLICE_194 (from osch_clk_sig_inferred_clock) ROUTE 4 0.129 R8C6A.Q1 to R8C6A.A1 POWER_MANAGER_INST/delay_st_1 CTOF_DEL --- 0.099 R8C6A.A1 to R8C6A.F1 POWER_MANAGER_INST/SLICE_194 ROUTE 1 0.000 R8C6A.F1 to R8C6A.DI1 POWER_MANAGER_INST/delay_st_ns_0_i_5 (to osch_clk_sig_inferred_clock) -------- 0.359 (64.1% logic, 35.9% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 1.663ns OSC.OSC to R8C6A.CLK Destination Clock: Delay Connection 1.663ns OSC.OSC to R8C6A.CLK Passed: The following path meets requirements by 0.374ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q POWER_MANAGER_INST/delay_st_0 (from osch_clk_sig_inferred_clock +) Destination: FF Data in POWER_MANAGER_INST/delay_st_0 (to osch_clk_sig_inferred_clock +) Delay: 0.359ns (64.1% logic, 35.9% route), 2 logic levels. Constraint Details: 0.359ns physical path delay POWER_MANAGER_INST/SLICE_194 to POWER_MANAGER_INST/SLICE_194 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.374ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R8C6A.CLK to R8C6A.Q0 POWER_MANAGER_INST/SLICE_194 (from osch_clk_sig_inferred_clock) ROUTE 2 0.129 R8C6A.Q0 to R8C6A.A0 POWER_MANAGER_INST/delay_st_0 CTOF_DEL --- 0.099 R8C6A.A0 to R8C6A.F0 POWER_MANAGER_INST/SLICE_194 ROUTE 1 0.000 R8C6A.F0 to R8C6A.DI0 POWER_MANAGER_INST/fb_0 (to osch_clk_sig_inferred_clock) -------- 0.359 (64.1% logic, 35.9% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 1.663ns OSC.OSC to R8C6A.CLK Destination Clock: Delay Connection 1.663ns OSC.OSC to R8C6A.CLK Passed: The following path meets requirements by 0.375ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q POWER_MANAGER_INST/delay_st_3 (from osch_clk_sig_inferred_clock +) Destination: FF Data in POWER_MANAGER_INST/delay_st_3 (to osch_clk_sig_inferred_clock +) Delay: 0.360ns (63.9% logic, 36.1% route), 2 logic levels. Constraint Details: 0.360ns physical path delay POWER_MANAGER_INST/SLICE_195 to POWER_MANAGER_INST/SLICE_195 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.375ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R8C4A.CLK to R8C4A.Q1 POWER_MANAGER_INST/SLICE_195 (from osch_clk_sig_inferred_clock) ROUTE 4 0.130 R8C4A.Q1 to R8C4A.A1 POWER_MANAGER_INST/delay_st_3 CTOF_DEL --- 0.099 R8C4A.A1 to R8C4A.F1 POWER_MANAGER_INST/SLICE_195 ROUTE 1 0.000 R8C4A.F1 to R8C4A.DI1 POWER_MANAGER_INST/delay_st_ns_0_i_3 (to osch_clk_sig_inferred_clock) -------- 0.360 (63.9% logic, 36.1% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 1.663ns OSC.OSC to R8C4A.CLK Destination Clock: Delay Connection 1.663ns OSC.OSC to R8C4A.CLK Passed: The following path meets requirements by 0.378ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q POWER_MANAGER_INST/delay_st_3 (from osch_clk_sig_inferred_clock +) Destination: FF Data in POWER_MANAGER_INST/delay_st_2 (to osch_clk_sig_inferred_clock +) Delay: 0.363ns (63.4% logic, 36.6% route), 2 logic levels. Constraint Details: 0.363ns physical path delay POWER_MANAGER_INST/SLICE_195 to POWER_MANAGER_INST/SLICE_195 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.378ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R8C4A.CLK to R8C4A.Q1 POWER_MANAGER_INST/SLICE_195 (from osch_clk_sig_inferred_clock) ROUTE 4 0.133 R8C4A.Q1 to R8C4A.D0 POWER_MANAGER_INST/delay_st_3 CTOF_DEL --- 0.099 R8C4A.D0 to R8C4A.F0 POWER_MANAGER_INST/SLICE_195 ROUTE 1 0.000 R8C4A.F0 to R8C4A.DI0 POWER_MANAGER_INST/N_78_0 (to osch_clk_sig_inferred_clock) -------- 0.363 (63.4% logic, 36.6% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 1.663ns OSC.OSC to R8C4A.CLK Destination Clock: Delay Connection 1.663ns OSC.OSC to R8C4A.CLK Passed: The following path meets requirements by 0.380ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q POWER_MANAGER_INST/timer_cnt_15ms_reg (from osch_clk_sig_inferred_clock +) Destination: FF Data in POWER_MANAGER_INST/delay_st_4 (to osch_clk_sig_inferred_clock +) Delay: 0.365ns (63.0% logic, 37.0% route), 2 logic levels. Constraint Details: 0.365ns physical path delay POWER_MANAGER_INST/SLICE_200 to POWER_MANAGER_INST/SLICE_196 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.380ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R8C4C.CLK to R8C4C.Q0 POWER_MANAGER_INST/SLICE_200 (from osch_clk_sig_inferred_clock) ROUTE 2 0.135 R8C4C.Q0 to R8C4B.D0 POWER_MANAGER_INST/timer_cnt_15ms_reg CTOF_DEL --- 0.099 R8C4B.D0 to R8C4B.F0 POWER_MANAGER_INST/SLICE_196 ROUTE 1 0.000 R8C4B.F0 to R8C4B.DI0 POWER_MANAGER_INST/delay_st_ns_0_i_2 (to osch_clk_sig_inferred_clock) -------- 0.365 (63.0% logic, 37.0% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 1.663ns OSC.OSC to R8C4C.CLK Destination Clock: Delay Connection 1.663ns OSC.OSC to R8C4B.CLK Passed: The following path meets requirements by 0.380ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q POWER_MANAGER_INST/timer_cnt_15ms_reg (from osch_clk_sig_inferred_clock +) Destination: FF Data in POWER_MANAGER_INST/delay_st_3 (to osch_clk_sig_inferred_clock +) Delay: 0.365ns (63.0% logic, 37.0% route), 2 logic levels. Constraint Details: 0.365ns physical path delay POWER_MANAGER_INST/SLICE_200 to POWER_MANAGER_INST/SLICE_195 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.380ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R8C4C.CLK to R8C4C.Q0 POWER_MANAGER_INST/SLICE_200 (from osch_clk_sig_inferred_clock) ROUTE 2 0.135 R8C4C.Q0 to R8C4A.D1 POWER_MANAGER_INST/timer_cnt_15ms_reg CTOF_DEL --- 0.099 R8C4A.D1 to R8C4A.F1 POWER_MANAGER_INST/SLICE_195 ROUTE 1 0.000 R8C4A.F1 to R8C4A.DI1 POWER_MANAGER_INST/delay_st_ns_0_i_3 (to osch_clk_sig_inferred_clock) -------- 0.365 (63.0% logic, 37.0% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 1.663ns OSC.OSC to R8C4C.CLK Destination Clock: Delay Connection 1.663ns OSC.OSC to R8C4A.CLK Passed: The following path meets requirements by 0.380ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q POWER_MANAGER_INST/timer_cnt_8 (from osch_clk_sig_inferred_clock +) Destination: FF Data in POWER_MANAGER_INST/timer_cnt_8 (to osch_clk_sig_inferred_clock +) Delay: 0.365ns (63.0% logic, 37.0% route), 2 logic levels. Constraint Details: 0.365ns physical path delay POWER_MANAGER_INST/SLICE_101 to POWER_MANAGER_INST/SLICE_101 meets -0.015ns DIN_HLD and 0.000ns delay constraint less 0.000ns skew requirement (totaling -0.015ns) by 0.380ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.131 R7C5A.CLK to R7C5A.Q1 POWER_MANAGER_INST/SLICE_101 (from osch_clk_sig_inferred_clock) ROUTE 3 0.135 R7C5A.Q1 to R7C5A.C1 POWER_MANAGER_INST/timer_cnt_8 CTOF_DEL --- 0.099 R7C5A.C1 to R7C5A.F1 POWER_MANAGER_INST/SLICE_101 ROUTE 1 0.000 R7C5A.F1 to R7C5A.DI1 POWER_MANAGER_INST/timer_cnt_s_8 (to osch_clk_sig_inferred_clock) -------- 0.365 (63.0% logic, 37.0% route), 2 logic levels. Clock Skew Details: Source Clock: Delay Connection 1.663ns OSC.OSC to R7C5A.CLK Destination Clock: Delay Connection 1.663ns OSC.OSC to R7C5A.CLK ================================================================================ Preference: FREQUENCY NET "ext_osc_clk_c" 40.000000 MHz ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "ext_osc_clk" 40.000000 MHz ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Report Summary -------------- ---------------------------------------------------------------------------- Preference(MIN Delays) | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "sys_clk_sig_c" | | | 130.000000 MHz ; | -| -| 2 | | | FREQUENCY NET "TX_LVDS_71_INST/eclko" | | | 130.000000 MHz ; | -| -| 0 | | | FREQUENCY NET | | | "TX_LVDS_71_INST/sclk_sig" 38.000000 | | | MHz ; | -| -| 1 * | | | FREQUENCY NET "tft_clk_sig_c" 37.142857 | | | MHz ; | -| -| 2 | | | FREQUENCY NET | | | "osch_clk_sig_inferred_clock" 2.080000 | | | MHz ; | -| -| 1 | | | FREQUENCY NET "ext_osc_clk_c" 40.000000 | | | MHz ; | -| -| 0 | | | FREQUENCY PORT "ext_osc_clk" 40.000000 | | | MHz ; | -| -| 0 | | | ---------------------------------------------------------------------------- 1 preference(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- tft_blue_sig_4 | 1| 1| 12.50% | | | tft_blue_sig_5 | 1| 1| 12.50% | | | tft_blue_sig_6 | 1| 1| 12.50% | | | tft_dtmg_sig | 3| 1| 12.50% | | | tft_blue_sig_3 | 1| 1| 12.50% | | | tft_red_sig_4 | 1| 1| 12.50% | | | tft_red_sig_5 | 1| 1| 12.50% | | | tft_red_sig_6 | 1| 1| 12.50% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 6 clocks: Clock Domain: TX_LVDS_71_INST/sclk_sig Source: TX_LVDS_71_INST/Inst3_CLKDIVC.CDIVX Loads: 5 No transfer within this clock domain is found Data transfers from: Clock Domain: tft_clk_sig_c Source: PLL_BLOCK_INST/PLLInst_0.CLKOS3 Covered under: FREQUENCY NET "TX_LVDS_71_INST/sclk_sig" 38.000000 MHz ; Transfers: 18 Clock Domain: TX_LVDS_71_INST/eclko Source: TX_LVDS_71_INST/Inst2_ECLKSYNCA.ECLKO Loads: 6 No transfer within this clock domain is found Data transfers from: Clock Domain: TX_LVDS_71_INST/sclk_sig Source: TX_LVDS_71_INST/Inst3_CLKDIVC.CDIVX Covered under: Timing Rule Check Transfers: 4 Clock Domain: tft_clk_sig_c Source: PLL_BLOCK_INST/PLLInst_0.CLKOS3 Loads: 175 Covered under: FREQUENCY NET "tft_clk_sig_c" 37.142857 MHz ; Data transfers from: Clock Domain: sys_clk_sig_c Source: PLL_BLOCK_INST/PLLInst_0.CLKOP Covered under: FREQUENCY NET "tft_clk_sig_c" 37.142857 MHz ; Transfers: 23 Clock Domain: sys_clk_sig_c Source: PLL_BLOCK_INST/PLLInst_0.CLKOP Loads: 214 Covered under: FREQUENCY NET "sys_clk_sig_c" 130.000000 MHz ; Data transfers from: Clock Domain: tft_clk_sig_c Source: PLL_BLOCK_INST/PLLInst_0.CLKOS3 Covered under: FREQUENCY NET "sys_clk_sig_c" 130.000000 MHz ; Transfers: 71 Clock Domain: osch_clk_sig_inferred_clock Source: OSCH_INST.OSC Not reported because source and destination domains are unrelated. Clock Domain: osch_clk_sig_inferred_clock Source: OSCH_INST.OSC Loads: 16 Covered under: FREQUENCY NET "osch_clk_sig_inferred_clock" 2.080000 MHz ; Clock Domain: ext_osc_clk_c Source: ext_osc_clk.PAD Loads: 1 No transfer within this clock domain is found Timing summary (Hold): --------------- Timing errors: 8 Score: 347 Cumulative negative slack: 347 Constraints cover 4656 paths, 6 nets, and 3406 connections (96.0% coverage) Timing summary (Setup and Hold): --------------- Timing errors: 4 (setup), 8 (hold) Score: 514 (setup), 347 (hold) Cumulative negative slack: 861 (514+347)