Place & Route TRACE Report
Loading design for application trce from file tftsurfer_tftsurfer.ncd.
Design name: top_conMICO32
NCD version: 3.2
Vendor: LATTICE
Device: LCMXO2-7000HC
Package: TQFP144
Performance: 6
Loading device for application trce from file 'xo2c7000.nph' in environment: C:/lscc/diamond/2.2/ispfpga.
Package Status: Final Version 1.36
Performance Hardware Data Status: Final) Version 23.4
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond Version 2.2.0.101
Fri Aug 02 10:00:25 2013
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 6 -sphld m -o tftsurfer_tftsurfer.twr tftsurfer_tftsurfer.ncd tftsurfer_tftsurfer.prf
Design file: tftsurfer_tftsurfer.ncd
Preference file: tftsurfer_tftsurfer.prf
Device,speed: LCMXO2-7000HC,6
Report level: verbose report, limited to 10 items per preference
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Preference Summary
FREQUENCY NET "controller_marco.sys_clk_sig_c" 125.000000 MHz (0 errors) 2888 items scored, 0 timing errors detected.
Report: 150.105MHz is the maximum frequency for this preference.
FREQUENCY NET "controller_marco/osch_clk_sig_c" 10.230000 MHz (0 errors) 310 items scored, 0 timing errors detected.
Report: 171.145MHz is the maximum frequency for this preference.
FREQUENCY NET "tft_clk_c_c" 35.714286 MHz (0 errors) 3364 items scored, 0 timing errors detected.
Report: 74.019MHz is the maximum frequency for this preference.
FREQUENCY PORT "ext_osc_clk" 25.000000 MHz (0 errors) 0 items scored, 0 timing errors detected.
Report: 150.150MHz is the maximum frequency for this preference.
FREQUENCY NET "ext_osc_clk_c" 25.000000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
Report: 54.460MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
BLOCK INTERCLOCKDOMAIN PATHS
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Derating parameters
-------------------
Voltage: 1.180 V
================================================================================
Preference: FREQUENCY NET "controller_marco.sys_clk_sig_c" 125.000000 MHz ;
2888 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 1.338ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/SDRAM_CTRL_INST/sdram_fsm_st[1] (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco/SDRAM_CTRL_INST/sdram_fsm_st[1] (to controller_marco.sys_clk_sig_c +)
Delay: 6.541ns (28.0% logic, 72.0% route), 5 logic levels.
Constraint Details:
6.541ns physical path delay controller_marco/SDRAM_CTRL_INST/SLICE_875 to controller_marco/SDRAM_CTRL_INST/SLICE_875 meets
8.000ns delay constraint less
0.000ns skew and
0.121ns DIN_SET requirement (totaling 7.879ns) by 1.338ns
Physical Path Details:
Data path controller_marco/SDRAM_CTRL_INST/SLICE_875 to controller_marco/SDRAM_CTRL_INST/SLICE_875:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R8C33C.CLK to R8C33C.Q1 controller_marco/SDRAM_CTRL_INST/SLICE_875 (from controller_marco.sys_clk_sig_c)
ROUTE 36 0.781 R8C33C.Q1 to R8C34B.A1 controller_marco/SDRAM_CTRL_INST/sdram_fsm_st[1]
CTOF_DEL --- 0.374 R8C34B.A1 to R8C34B.F1 controller_marco/SDRAM_CTRL_INST/SLICE_2192
ROUTE 7 1.036 R8C34B.F1 to R8C35C.D1 controller_marco/SDRAM_CTRL_INST/cycle_end_reg_1_0_0_o2
CTOF_DEL --- 0.374 R8C35C.D1 to R8C35C.F1 controller_marco/SDRAM_CTRL_INST/SLICE_2156
ROUTE 1 1.270 R8C35C.F1 to R8C34A.B1 controller_marco/SDRAM_CTRL_INST/m33_i_1
CTOF_DEL --- 0.374 R8C34A.B1 to R8C34A.F1 controller_marco/SDRAM_CTRL_INST/SLICE_2612
ROUTE 1 1.622 R8C34A.F1 to R8C33C.D1 controller_marco/SDRAM_CTRL_INST/m33_i_2
CTOF_DEL --- 0.374 R8C33C.D1 to R8C33C.F1 controller_marco/SDRAM_CTRL_INST/SLICE_875
ROUTE 1 0.000 R8C33C.F1 to R8C33C.DI1 controller_marco/SDRAM_CTRL_INST/N_346_i (to controller_marco.sys_clk_sig_c)
--------
6.541 (28.0% logic, 72.0% route), 5 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/SDRAM_CTRL_INST/SLICE_875:
Name Fanout Delay (ns) Site Resource
ROUTE 382 1.412 LPLL.CLKOP to R8C33C.CLK controller_marco.sys_clk_sig_c
--------
1.412 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/SDRAM_CTRL_INST/SLICE_875:
Name Fanout Delay (ns) Site Resource
ROUTE 382 1.412 LPLL.CLKOP to R8C33C.CLK controller_marco.sys_clk_sig_c
--------
1.412 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.339ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/SDRAM_CTRL_INST/sdram_fsm_st[5] (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco_SDRAM_CTRL_INST_sdram_a_regio[4] (to controller_marco.sys_clk_sig_c +)
Delay: 6.670ns (27.5% logic, 72.5% route), 5 logic levels.
Constraint Details:
6.670ns physical path delay controller_marco/SDRAM_CTRL_INST/SLICE_877 to sdram_a[4]_MGIOL meets
8.000ns delay constraint less
-0.122ns skew and
0.113ns DO_SET requirement (totaling 8.009ns) by 1.339ns
Physical Path Details:
Data path controller_marco/SDRAM_CTRL_INST/SLICE_877 to sdram_a[4]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R7C32C.CLK to R7C32C.Q1 controller_marco/SDRAM_CTRL_INST/SLICE_877 (from controller_marco.sys_clk_sig_c)
ROUTE 32 1.034 R7C32C.Q1 to R8C35D.D0 controller_marco/SDRAM_CTRL_INST/sdram_fsm_st[5]
CTOF_DEL --- 0.374 R8C35D.D0 to R8C35D.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2185
ROUTE 5 0.798 R8C35D.F0 to R10C36A.C0 controller_marco/SDRAM_CTRL_INST/sdram_fsm_st_RNIOCJU1[5]
CTOF_DEL --- 0.374 R10C36A.C0 to R10C36A.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2149
ROUTE 6 0.461 R10C36A.F0 to R10C36A.D1 controller_marco/SDRAM_CTRL_INST/sdram_a_reg_9s2_i_a2_0_3_0
CTOF_DEL --- 0.374 R10C36A.D1 to R10C36A.F1 controller_marco/SDRAM_CTRL_INST/SLICE_2149
ROUTE 3 0.692 R10C36A.F1 to R12C37D.D0 controller_marco/SDRAM_CTRL_INST/N_344_tz
CTOF_DEL --- 0.374 R12C37D.D0 to R12C37D.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2613
ROUTE 1 1.853 R12C37D.F0 to IOL_R2A.OPOS controller_marco.N_343_i (to controller_marco.sys_clk_sig_c)
--------
6.670 (27.5% logic, 72.5% route), 5 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/SDRAM_CTRL_INST/SLICE_877:
Name Fanout Delay (ns) Site Resource
ROUTE 382 1.412 LPLL.CLKOP to R7C32C.CLK controller_marco.sys_clk_sig_c
--------
1.412 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to sdram_a[4]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 382 1.534 LPLL.CLKOP to IOL_R2A.CLK controller_marco.sys_clk_sig_c
--------
1.534 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.346ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/SDRAM_CTRL_INST/sdram_fsm_st[0] (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco_SDRAM_CTRL_INST_sdram_a_regio[4] (to controller_marco.sys_clk_sig_c +)
Delay: 6.663ns (27.5% logic, 72.5% route), 5 logic levels.
Constraint Details:
6.663ns physical path delay controller_marco/SDRAM_CTRL_INST/SLICE_875 to sdram_a[4]_MGIOL meets
8.000ns delay constraint less
-0.122ns skew and
0.113ns DO_SET requirement (totaling 8.009ns) by 1.346ns
Physical Path Details:
Data path controller_marco/SDRAM_CTRL_INST/SLICE_875 to sdram_a[4]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R8C33C.CLK to R8C33C.Q0 controller_marco/SDRAM_CTRL_INST/SLICE_875 (from controller_marco.sys_clk_sig_c)
ROUTE 37 1.027 R8C33C.Q0 to R8C35D.B0 controller_marco/SDRAM_CTRL_INST/sdram_fsm_st[0]
CTOF_DEL --- 0.374 R8C35D.B0 to R8C35D.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2185
ROUTE 5 0.798 R8C35D.F0 to R10C36A.C0 controller_marco/SDRAM_CTRL_INST/sdram_fsm_st_RNIOCJU1[5]
CTOF_DEL --- 0.374 R10C36A.C0 to R10C36A.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2149
ROUTE 6 0.461 R10C36A.F0 to R10C36A.D1 controller_marco/SDRAM_CTRL_INST/sdram_a_reg_9s2_i_a2_0_3_0
CTOF_DEL --- 0.374 R10C36A.D1 to R10C36A.F1 controller_marco/SDRAM_CTRL_INST/SLICE_2149
ROUTE 3 0.692 R10C36A.F1 to R12C37D.D0 controller_marco/SDRAM_CTRL_INST/N_344_tz
CTOF_DEL --- 0.374 R12C37D.D0 to R12C37D.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2613
ROUTE 1 1.853 R12C37D.F0 to IOL_R2A.OPOS controller_marco.N_343_i (to controller_marco.sys_clk_sig_c)
--------
6.663 (27.5% logic, 72.5% route), 5 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/SDRAM_CTRL_INST/SLICE_875:
Name Fanout Delay (ns) Site Resource
ROUTE 382 1.412 LPLL.CLKOP to R8C33C.CLK controller_marco.sys_clk_sig_c
--------
1.412 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to sdram_a[4]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 382 1.534 LPLL.CLKOP to IOL_R2A.CLK controller_marco.sys_clk_sig_c
--------
1.534 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.353ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/SDRAM_CTRL_INST/sdram_fsm_st[5] (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco_SDRAM_CTRL_INST_sdram_ba_regio[1] (to controller_marco.sys_clk_sig_c +)
Delay: 6.625ns (27.7% logic, 72.3% route), 5 logic levels.
Constraint Details:
6.625ns physical path delay controller_marco/SDRAM_CTRL_INST/SLICE_877 to sdram_ba[1]_MGIOL meets
8.000ns delay constraint less
-0.091ns skew and
0.113ns DO_SET requirement (totaling 7.978ns) by 1.353ns
Physical Path Details:
Data path controller_marco/SDRAM_CTRL_INST/SLICE_877 to sdram_ba[1]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R7C32C.CLK to R7C32C.Q1 controller_marco/SDRAM_CTRL_INST/SLICE_877 (from controller_marco.sys_clk_sig_c)
ROUTE 32 1.034 R7C32C.Q1 to R8C35D.D0 controller_marco/SDRAM_CTRL_INST/sdram_fsm_st[5]
CTOF_DEL --- 0.374 R8C35D.D0 to R8C35D.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2185
ROUTE 5 0.798 R8C35D.F0 to R10C36A.C0 controller_marco/SDRAM_CTRL_INST/sdram_fsm_st_RNIOCJU1[5]
CTOF_DEL --- 0.374 R10C36A.C0 to R10C36A.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2149
ROUTE 6 0.741 R10C36A.F0 to R12C36C.A1 controller_marco/SDRAM_CTRL_INST/sdram_a_reg_9s2_i_a2_0_3_0
CTOF_DEL --- 0.374 R12C36C.A1 to R12C36C.F1 controller_marco/SDRAM_CTRL_INST/SLICE_2194
ROUTE 6 0.548 R12C36C.F1 to R14C36B.D1 controller_marco/SDRAM_CTRL_INST/N_7
CTOF_DEL --- 0.374 R14C36B.D1 to R14C36B.F1 controller_marco/SDRAM_CTRL_INST/SLICE_2614
ROUTE 1 1.672 R14C36B.F1 to IOL_R23B.OPOS controller_marco.SDRAM_CTRL_INST.SDRAM_FSM_PROC.sdram_ba_reg_8[1] (to controller_marco.sys_clk_sig_c)
--------
6.625 (27.7% logic, 72.3% route), 5 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/SDRAM_CTRL_INST/SLICE_877:
Name Fanout Delay (ns) Site Resource
ROUTE 382 1.412 LPLL.CLKOP to R7C32C.CLK controller_marco.sys_clk_sig_c
--------
1.412 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to sdram_ba[1]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 382 1.503 LPLL.CLKOP to IOL_R23B.CLK controller_marco.sys_clk_sig_c
--------
1.503 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.360ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/SDRAM_CTRL_INST/sdram_fsm_st[0] (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco_SDRAM_CTRL_INST_sdram_ba_regio[1] (to controller_marco.sys_clk_sig_c +)
Delay: 6.618ns (27.7% logic, 72.3% route), 5 logic levels.
Constraint Details:
6.618ns physical path delay controller_marco/SDRAM_CTRL_INST/SLICE_875 to sdram_ba[1]_MGIOL meets
8.000ns delay constraint less
-0.091ns skew and
0.113ns DO_SET requirement (totaling 7.978ns) by 1.360ns
Physical Path Details:
Data path controller_marco/SDRAM_CTRL_INST/SLICE_875 to sdram_ba[1]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R8C33C.CLK to R8C33C.Q0 controller_marco/SDRAM_CTRL_INST/SLICE_875 (from controller_marco.sys_clk_sig_c)
ROUTE 37 1.027 R8C33C.Q0 to R8C35D.B0 controller_marco/SDRAM_CTRL_INST/sdram_fsm_st[0]
CTOF_DEL --- 0.374 R8C35D.B0 to R8C35D.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2185
ROUTE 5 0.798 R8C35D.F0 to R10C36A.C0 controller_marco/SDRAM_CTRL_INST/sdram_fsm_st_RNIOCJU1[5]
CTOF_DEL --- 0.374 R10C36A.C0 to R10C36A.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2149
ROUTE 6 0.741 R10C36A.F0 to R12C36C.A1 controller_marco/SDRAM_CTRL_INST/sdram_a_reg_9s2_i_a2_0_3_0
CTOF_DEL --- 0.374 R12C36C.A1 to R12C36C.F1 controller_marco/SDRAM_CTRL_INST/SLICE_2194
ROUTE 6 0.548 R12C36C.F1 to R14C36B.D1 controller_marco/SDRAM_CTRL_INST/N_7
CTOF_DEL --- 0.374 R14C36B.D1 to R14C36B.F1 controller_marco/SDRAM_CTRL_INST/SLICE_2614
ROUTE 1 1.672 R14C36B.F1 to IOL_R23B.OPOS controller_marco.SDRAM_CTRL_INST.SDRAM_FSM_PROC.sdram_ba_reg_8[1] (to controller_marco.sys_clk_sig_c)
--------
6.618 (27.7% logic, 72.3% route), 5 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/SDRAM_CTRL_INST/SLICE_875:
Name Fanout Delay (ns) Site Resource
ROUTE 382 1.412 LPLL.CLKOP to R8C33C.CLK controller_marco.sys_clk_sig_c
--------
1.412 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to sdram_ba[1]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 382 1.503 LPLL.CLKOP to IOL_R23B.CLK controller_marco.sys_clk_sig_c
--------
1.503 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.375ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/SDRAM_CTRL_INST/sdram_fsm_st[3] (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco_SDRAM_CTRL_INST_sdram_a_regio[4] (to controller_marco.sys_clk_sig_c +)
Delay: 6.634ns (27.6% logic, 72.4% route), 5 logic levels.
Constraint Details:
6.634ns physical path delay controller_marco/SDRAM_CTRL_INST/SLICE_876 to sdram_a[4]_MGIOL meets
8.000ns delay constraint less
-0.122ns skew and
0.113ns DO_SET requirement (totaling 8.009ns) by 1.375ns
Physical Path Details:
Data path controller_marco/SDRAM_CTRL_INST/SLICE_876 to sdram_a[4]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R8C33D.CLK to R8C33D.Q1 controller_marco/SDRAM_CTRL_INST/SLICE_876 (from controller_marco.sys_clk_sig_c)
ROUTE 36 0.998 R8C33D.Q1 to R8C35D.A0 controller_marco/SDRAM_CTRL_INST/sdram_fsm_st[3]
CTOF_DEL --- 0.374 R8C35D.A0 to R8C35D.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2185
ROUTE 5 0.798 R8C35D.F0 to R10C36A.C0 controller_marco/SDRAM_CTRL_INST/sdram_fsm_st_RNIOCJU1[5]
CTOF_DEL --- 0.374 R10C36A.C0 to R10C36A.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2149
ROUTE 6 0.461 R10C36A.F0 to R10C36A.D1 controller_marco/SDRAM_CTRL_INST/sdram_a_reg_9s2_i_a2_0_3_0
CTOF_DEL --- 0.374 R10C36A.D1 to R10C36A.F1 controller_marco/SDRAM_CTRL_INST/SLICE_2149
ROUTE 3 0.692 R10C36A.F1 to R12C37D.D0 controller_marco/SDRAM_CTRL_INST/N_344_tz
CTOF_DEL --- 0.374 R12C37D.D0 to R12C37D.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2613
ROUTE 1 1.853 R12C37D.F0 to IOL_R2A.OPOS controller_marco.N_343_i (to controller_marco.sys_clk_sig_c)
--------
6.634 (27.6% logic, 72.4% route), 5 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/SDRAM_CTRL_INST/SLICE_876:
Name Fanout Delay (ns) Site Resource
ROUTE 382 1.412 LPLL.CLKOP to R8C33D.CLK controller_marco.sys_clk_sig_c
--------
1.412 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to sdram_a[4]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 382 1.534 LPLL.CLKOP to IOL_R2A.CLK controller_marco.sys_clk_sig_c
--------
1.534 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.389ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/SDRAM_CTRL_INST/sdram_fsm_st[3] (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco_SDRAM_CTRL_INST_sdram_ba_regio[1] (to controller_marco.sys_clk_sig_c +)
Delay: 6.589ns (27.8% logic, 72.2% route), 5 logic levels.
Constraint Details:
6.589ns physical path delay controller_marco/SDRAM_CTRL_INST/SLICE_876 to sdram_ba[1]_MGIOL meets
8.000ns delay constraint less
-0.091ns skew and
0.113ns DO_SET requirement (totaling 7.978ns) by 1.389ns
Physical Path Details:
Data path controller_marco/SDRAM_CTRL_INST/SLICE_876 to sdram_ba[1]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R8C33D.CLK to R8C33D.Q1 controller_marco/SDRAM_CTRL_INST/SLICE_876 (from controller_marco.sys_clk_sig_c)
ROUTE 36 0.998 R8C33D.Q1 to R8C35D.A0 controller_marco/SDRAM_CTRL_INST/sdram_fsm_st[3]
CTOF_DEL --- 0.374 R8C35D.A0 to R8C35D.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2185
ROUTE 5 0.798 R8C35D.F0 to R10C36A.C0 controller_marco/SDRAM_CTRL_INST/sdram_fsm_st_RNIOCJU1[5]
CTOF_DEL --- 0.374 R10C36A.C0 to R10C36A.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2149
ROUTE 6 0.741 R10C36A.F0 to R12C36C.A1 controller_marco/SDRAM_CTRL_INST/sdram_a_reg_9s2_i_a2_0_3_0
CTOF_DEL --- 0.374 R12C36C.A1 to R12C36C.F1 controller_marco/SDRAM_CTRL_INST/SLICE_2194
ROUTE 6 0.548 R12C36C.F1 to R14C36B.D1 controller_marco/SDRAM_CTRL_INST/N_7
CTOF_DEL --- 0.374 R14C36B.D1 to R14C36B.F1 controller_marco/SDRAM_CTRL_INST/SLICE_2614
ROUTE 1 1.672 R14C36B.F1 to IOL_R23B.OPOS controller_marco.SDRAM_CTRL_INST.SDRAM_FSM_PROC.sdram_ba_reg_8[1] (to controller_marco.sys_clk_sig_c)
--------
6.589 (27.8% logic, 72.2% route), 5 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/SDRAM_CTRL_INST/SLICE_876:
Name Fanout Delay (ns) Site Resource
ROUTE 382 1.412 LPLL.CLKOP to R8C33D.CLK controller_marco.sys_clk_sig_c
--------
1.412 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to sdram_ba[1]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 382 1.503 LPLL.CLKOP to IOL_R23B.CLK controller_marco.sys_clk_sig_c
--------
1.503 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.393ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/SDRAM_CTRL_INST/sdram_fsm_st[5] (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco_SDRAM_CTRL_INST_sdram_ba_regio[0] (to controller_marco.sys_clk_sig_c +)
Delay: 6.585ns (27.8% logic, 72.2% route), 5 logic levels.
Constraint Details:
6.585ns physical path delay controller_marco/SDRAM_CTRL_INST/SLICE_877 to sdram_ba[0]_MGIOL meets
8.000ns delay constraint less
-0.091ns skew and
0.113ns DO_SET requirement (totaling 7.978ns) by 1.393ns
Physical Path Details:
Data path controller_marco/SDRAM_CTRL_INST/SLICE_877 to sdram_ba[0]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R7C32C.CLK to R7C32C.Q1 controller_marco/SDRAM_CTRL_INST/SLICE_877 (from controller_marco.sys_clk_sig_c)
ROUTE 32 1.034 R7C32C.Q1 to R8C35D.D0 controller_marco/SDRAM_CTRL_INST/sdram_fsm_st[5]
CTOF_DEL --- 0.374 R8C35D.D0 to R8C35D.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2185
ROUTE 5 0.798 R8C35D.F0 to R10C36A.C0 controller_marco/SDRAM_CTRL_INST/sdram_fsm_st_RNIOCJU1[5]
CTOF_DEL --- 0.374 R10C36A.C0 to R10C36A.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2149
ROUTE 6 0.741 R10C36A.F0 to R12C36C.A1 controller_marco/SDRAM_CTRL_INST/sdram_a_reg_9s2_i_a2_0_3_0
CTOF_DEL --- 0.374 R12C36C.A1 to R12C36C.F1 controller_marco/SDRAM_CTRL_INST/SLICE_2194
ROUTE 6 0.248 R12C36C.F1 to R12C36B.D1 controller_marco/SDRAM_CTRL_INST/N_7
CTOF_DEL --- 0.374 R12C36B.D1 to R12C36B.F1 controller_marco/SDRAM_CTRL_INST/SLICE_2615
ROUTE 1 1.932 R12C36B.F1 to IOL_R24A.OPOS controller_marco.SDRAM_CTRL_INST.SDRAM_FSM_PROC.sdram_ba_reg_8[0] (to controller_marco.sys_clk_sig_c)
--------
6.585 (27.8% logic, 72.2% route), 5 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/SDRAM_CTRL_INST/SLICE_877:
Name Fanout Delay (ns) Site Resource
ROUTE 382 1.412 LPLL.CLKOP to R7C32C.CLK controller_marco.sys_clk_sig_c
--------
1.412 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to sdram_ba[0]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 382 1.503 LPLL.CLKOP to IOL_R24A.CLK controller_marco.sys_clk_sig_c
--------
1.503 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.400ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/SDRAM_CTRL_INST/sdram_fsm_st[0] (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco_SDRAM_CTRL_INST_sdram_ba_regio[0] (to controller_marco.sys_clk_sig_c +)
Delay: 6.578ns (27.9% logic, 72.1% route), 5 logic levels.
Constraint Details:
6.578ns physical path delay controller_marco/SDRAM_CTRL_INST/SLICE_875 to sdram_ba[0]_MGIOL meets
8.000ns delay constraint less
-0.091ns skew and
0.113ns DO_SET requirement (totaling 7.978ns) by 1.400ns
Physical Path Details:
Data path controller_marco/SDRAM_CTRL_INST/SLICE_875 to sdram_ba[0]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R8C33C.CLK to R8C33C.Q0 controller_marco/SDRAM_CTRL_INST/SLICE_875 (from controller_marco.sys_clk_sig_c)
ROUTE 37 1.027 R8C33C.Q0 to R8C35D.B0 controller_marco/SDRAM_CTRL_INST/sdram_fsm_st[0]
CTOF_DEL --- 0.374 R8C35D.B0 to R8C35D.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2185
ROUTE 5 0.798 R8C35D.F0 to R10C36A.C0 controller_marco/SDRAM_CTRL_INST/sdram_fsm_st_RNIOCJU1[5]
CTOF_DEL --- 0.374 R10C36A.C0 to R10C36A.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2149
ROUTE 6 0.741 R10C36A.F0 to R12C36C.A1 controller_marco/SDRAM_CTRL_INST/sdram_a_reg_9s2_i_a2_0_3_0
CTOF_DEL --- 0.374 R12C36C.A1 to R12C36C.F1 controller_marco/SDRAM_CTRL_INST/SLICE_2194
ROUTE 6 0.248 R12C36C.F1 to R12C36B.D1 controller_marco/SDRAM_CTRL_INST/N_7
CTOF_DEL --- 0.374 R12C36B.D1 to R12C36B.F1 controller_marco/SDRAM_CTRL_INST/SLICE_2615
ROUTE 1 1.932 R12C36B.F1 to IOL_R24A.OPOS controller_marco.SDRAM_CTRL_INST.SDRAM_FSM_PROC.sdram_ba_reg_8[0] (to controller_marco.sys_clk_sig_c)
--------
6.578 (27.9% logic, 72.1% route), 5 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/SDRAM_CTRL_INST/SLICE_875:
Name Fanout Delay (ns) Site Resource
ROUTE 382 1.412 LPLL.CLKOP to R8C33C.CLK controller_marco.sys_clk_sig_c
--------
1.412 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to sdram_ba[0]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 382 1.503 LPLL.CLKOP to IOL_R24A.CLK controller_marco.sys_clk_sig_c
--------
1.503 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 1.416ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/SDRAM_CTRL_INST/sdram_fsm_st[4] (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco_SDRAM_CTRL_INST_sdram_a_regio[4] (to controller_marco.sys_clk_sig_c +)
Delay: 6.593ns (27.8% logic, 72.2% route), 5 logic levels.
Constraint Details:
6.593ns physical path delay controller_marco/SDRAM_CTRL_INST/SLICE_877 to sdram_a[4]_MGIOL meets
8.000ns delay constraint less
-0.122ns skew and
0.113ns DO_SET requirement (totaling 8.009ns) by 1.416ns
Physical Path Details:
Data path controller_marco/SDRAM_CTRL_INST/SLICE_877 to sdram_a[4]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R7C32C.CLK to R7C32C.Q0 controller_marco/SDRAM_CTRL_INST/SLICE_877 (from controller_marco.sys_clk_sig_c)
ROUTE 40 0.957 R7C32C.Q0 to R8C35D.C0 controller_marco/SDRAM_CTRL_INST/sdram_fsm_st[4]
CTOF_DEL --- 0.374 R8C35D.C0 to R8C35D.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2185
ROUTE 5 0.798 R8C35D.F0 to R10C36A.C0 controller_marco/SDRAM_CTRL_INST/sdram_fsm_st_RNIOCJU1[5]
CTOF_DEL --- 0.374 R10C36A.C0 to R10C36A.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2149
ROUTE 6 0.461 R10C36A.F0 to R10C36A.D1 controller_marco/SDRAM_CTRL_INST/sdram_a_reg_9s2_i_a2_0_3_0
CTOF_DEL --- 0.374 R10C36A.D1 to R10C36A.F1 controller_marco/SDRAM_CTRL_INST/SLICE_2149
ROUTE 3 0.692 R10C36A.F1 to R12C37D.D0 controller_marco/SDRAM_CTRL_INST/N_344_tz
CTOF_DEL --- 0.374 R12C37D.D0 to R12C37D.F0 controller_marco/SDRAM_CTRL_INST/SLICE_2613
ROUTE 1 1.853 R12C37D.F0 to IOL_R2A.OPOS controller_marco.N_343_i (to controller_marco.sys_clk_sig_c)
--------
6.593 (27.8% logic, 72.2% route), 5 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/SDRAM_CTRL_INST/SLICE_877:
Name Fanout Delay (ns) Site Resource
ROUTE 382 1.412 LPLL.CLKOP to R7C32C.CLK controller_marco.sys_clk_sig_c
--------
1.412 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to sdram_a[4]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 382 1.534 LPLL.CLKOP to IOL_R2A.CLK controller_marco.sys_clk_sig_c
--------
1.534 (0.0% logic, 100.0% route), 0 logic levels.
Report: 150.105MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "controller_marco/osch_clk_sig_c" 10.230000 MHz ;
310 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 91.908ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/timer_cnt_rst (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/timer_cnt[14] (to controller_marco/osch_clk_sig_c +)
Delay: 5.722ns (45.4% logic, 54.6% route), 10 logic levels.
Constraint Details:
5.722ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_860 to controller_marco/POWER_MANAGER_INST/SLICE_171 meets
97.751ns delay constraint less
0.000ns skew and
0.121ns DIN_SET requirement (totaling 97.630ns) by 91.908ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_860 to controller_marco/POWER_MANAGER_INST/SLICE_171:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R8C27C.CLK to R8C27C.Q0 controller_marco/POWER_MANAGER_INST/SLICE_860 (from controller_marco/osch_clk_sig_c)
ROUTE 1 0.815 R8C27C.Q0 to R10C24C.D0 controller_marco/POWER_MANAGER_INST/timer_cnt_rst
CTOF_DEL --- 0.374 R10C24C.D0 to R10C24C.F0 SLICE_2051
ROUTE 16 2.309 R10C24C.F0 to R9C39A.A0 controller_marco/POWER_MANAGER_INST/timer_cnt_rst_i
C0TOFCO_DE --- 0.721 R9C39A.A0 to R9C39A.FCO controller_marco/POWER_MANAGER_INST/SLICE_170
ROUTE 1 0.000 R9C39A.FCO to R9C39B.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[0]
FCITOFCO_D --- 0.119 R9C39B.FCI to R9C39B.FCO controller_marco/POWER_MANAGER_INST/SLICE_177
ROUTE 1 0.000 R9C39B.FCO to R9C39C.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[2]
FCITOFCO_D --- 0.119 R9C39C.FCI to R9C39C.FCO controller_marco/POWER_MANAGER_INST/SLICE_176
ROUTE 1 0.000 R9C39C.FCO to R9C39D.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[4]
FCITOFCO_D --- 0.119 R9C39D.FCI to R9C39D.FCO controller_marco/POWER_MANAGER_INST/SLICE_175
ROUTE 1 0.000 R9C39D.FCO to R9C40A.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[6]
FCITOFCO_D --- 0.119 R9C40A.FCI to R9C40A.FCO controller_marco/POWER_MANAGER_INST/SLICE_174
ROUTE 1 0.000 R9C40A.FCO to R9C40B.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[8]
FCITOFCO_D --- 0.119 R9C40B.FCI to R9C40B.FCO controller_marco/POWER_MANAGER_INST/SLICE_173
ROUTE 1 0.000 R9C40B.FCO to R9C40C.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[10]
FCITOFCO_D --- 0.119 R9C40C.FCI to R9C40C.FCO controller_marco/POWER_MANAGER_INST/SLICE_172
ROUTE 1 0.000 R9C40C.FCO to R9C40D.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[12]
FCITOF1_DE --- 0.453 R9C40D.FCI to R9C40D.F1 controller_marco/POWER_MANAGER_INST/SLICE_171
ROUTE 1 0.000 R9C40D.F1 to R9C40D.DI1 controller_marco/POWER_MANAGER_INST/timer_cnt_s[14] (to controller_marco/osch_clk_sig_c)
--------
5.722 (45.4% logic, 54.6% route), 10 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_860:
Name Fanout Delay (ns) Site Resource
ROUTE 17 3.051 OSC.OSC to R8C27C.CLK controller_marco/osch_clk_sig_c
--------
3.051 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_171:
Name Fanout Delay (ns) Site Resource
ROUTE 17 3.051 OSC.OSC to R9C40D.CLK controller_marco/osch_clk_sig_c
--------
3.051 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 91.949ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/timer_cnt_rst (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/timer_cnt[13] (to controller_marco/osch_clk_sig_c +)
Delay: 5.681ns (45.0% logic, 55.0% route), 10 logic levels.
Constraint Details:
5.681ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_860 to controller_marco/POWER_MANAGER_INST/SLICE_171 meets
97.751ns delay constraint less
0.000ns skew and
0.121ns DIN_SET requirement (totaling 97.630ns) by 91.949ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_860 to controller_marco/POWER_MANAGER_INST/SLICE_171:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R8C27C.CLK to R8C27C.Q0 controller_marco/POWER_MANAGER_INST/SLICE_860 (from controller_marco/osch_clk_sig_c)
ROUTE 1 0.815 R8C27C.Q0 to R10C24C.D0 controller_marco/POWER_MANAGER_INST/timer_cnt_rst
CTOF_DEL --- 0.374 R10C24C.D0 to R10C24C.F0 SLICE_2051
ROUTE 16 2.309 R10C24C.F0 to R9C39A.A0 controller_marco/POWER_MANAGER_INST/timer_cnt_rst_i
C0TOFCO_DE --- 0.721 R9C39A.A0 to R9C39A.FCO controller_marco/POWER_MANAGER_INST/SLICE_170
ROUTE 1 0.000 R9C39A.FCO to R9C39B.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[0]
FCITOFCO_D --- 0.119 R9C39B.FCI to R9C39B.FCO controller_marco/POWER_MANAGER_INST/SLICE_177
ROUTE 1 0.000 R9C39B.FCO to R9C39C.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[2]
FCITOFCO_D --- 0.119 R9C39C.FCI to R9C39C.FCO controller_marco/POWER_MANAGER_INST/SLICE_176
ROUTE 1 0.000 R9C39C.FCO to R9C39D.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[4]
FCITOFCO_D --- 0.119 R9C39D.FCI to R9C39D.FCO controller_marco/POWER_MANAGER_INST/SLICE_175
ROUTE 1 0.000 R9C39D.FCO to R9C40A.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[6]
FCITOFCO_D --- 0.119 R9C40A.FCI to R9C40A.FCO controller_marco/POWER_MANAGER_INST/SLICE_174
ROUTE 1 0.000 R9C40A.FCO to R9C40B.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[8]
FCITOFCO_D --- 0.119 R9C40B.FCI to R9C40B.FCO controller_marco/POWER_MANAGER_INST/SLICE_173
ROUTE 1 0.000 R9C40B.FCO to R9C40C.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[10]
FCITOFCO_D --- 0.119 R9C40C.FCI to R9C40C.FCO controller_marco/POWER_MANAGER_INST/SLICE_172
ROUTE 1 0.000 R9C40C.FCO to R9C40D.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[12]
FCITOF0_DE --- 0.412 R9C40D.FCI to R9C40D.F0 controller_marco/POWER_MANAGER_INST/SLICE_171
ROUTE 1 0.000 R9C40D.F0 to R9C40D.DI0 controller_marco/POWER_MANAGER_INST/timer_cnt_s[13] (to controller_marco/osch_clk_sig_c)
--------
5.681 (45.0% logic, 55.0% route), 10 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_860:
Name Fanout Delay (ns) Site Resource
ROUTE 17 3.051 OSC.OSC to R8C27C.CLK controller_marco/osch_clk_sig_c
--------
3.051 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_171:
Name Fanout Delay (ns) Site Resource
ROUTE 17 3.051 OSC.OSC to R9C40D.CLK controller_marco/osch_clk_sig_c
--------
3.051 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 92.002ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/timer_cnt_rst (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/timer_cnt[14] (to controller_marco/osch_clk_sig_c +)
Delay: 5.628ns (44.5% logic, 55.5% route), 10 logic levels.
Constraint Details:
5.628ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_860 to controller_marco/POWER_MANAGER_INST/SLICE_171 meets
97.751ns delay constraint less
0.000ns skew and
0.121ns DIN_SET requirement (totaling 97.630ns) by 92.002ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_860 to controller_marco/POWER_MANAGER_INST/SLICE_171:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R8C27C.CLK to R8C27C.Q0 controller_marco/POWER_MANAGER_INST/SLICE_860 (from controller_marco/osch_clk_sig_c)
ROUTE 1 0.815 R8C27C.Q0 to R10C24C.D0 controller_marco/POWER_MANAGER_INST/timer_cnt_rst
CTOF_DEL --- 0.374 R10C24C.D0 to R10C24C.F0 SLICE_2051
ROUTE 16 2.309 R10C24C.F0 to R9C39A.A1 controller_marco/POWER_MANAGER_INST/timer_cnt_rst_i
C1TOFCO_DE --- 0.627 R9C39A.A1 to R9C39A.FCO controller_marco/POWER_MANAGER_INST/SLICE_170
ROUTE 1 0.000 R9C39A.FCO to R9C39B.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[0]
FCITOFCO_D --- 0.119 R9C39B.FCI to R9C39B.FCO controller_marco/POWER_MANAGER_INST/SLICE_177
ROUTE 1 0.000 R9C39B.FCO to R9C39C.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[2]
FCITOFCO_D --- 0.119 R9C39C.FCI to R9C39C.FCO controller_marco/POWER_MANAGER_INST/SLICE_176
ROUTE 1 0.000 R9C39C.FCO to R9C39D.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[4]
FCITOFCO_D --- 0.119 R9C39D.FCI to R9C39D.FCO controller_marco/POWER_MANAGER_INST/SLICE_175
ROUTE 1 0.000 R9C39D.FCO to R9C40A.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[6]
FCITOFCO_D --- 0.119 R9C40A.FCI to R9C40A.FCO controller_marco/POWER_MANAGER_INST/SLICE_174
ROUTE 1 0.000 R9C40A.FCO to R9C40B.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[8]
FCITOFCO_D --- 0.119 R9C40B.FCI to R9C40B.FCO controller_marco/POWER_MANAGER_INST/SLICE_173
ROUTE 1 0.000 R9C40B.FCO to R9C40C.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[10]
FCITOFCO_D --- 0.119 R9C40C.FCI to R9C40C.FCO controller_marco/POWER_MANAGER_INST/SLICE_172
ROUTE 1 0.000 R9C40C.FCO to R9C40D.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[12]
FCITOF1_DE --- 0.453 R9C40D.FCI to R9C40D.F1 controller_marco/POWER_MANAGER_INST/SLICE_171
ROUTE 1 0.000 R9C40D.F1 to R9C40D.DI1 controller_marco/POWER_MANAGER_INST/timer_cnt_s[14] (to controller_marco/osch_clk_sig_c)
--------
5.628 (44.5% logic, 55.5% route), 10 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_860:
Name Fanout Delay (ns) Site Resource
ROUTE 17 3.051 OSC.OSC to R8C27C.CLK controller_marco/osch_clk_sig_c
--------
3.051 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_171:
Name Fanout Delay (ns) Site Resource
ROUTE 17 3.051 OSC.OSC to R9C40D.CLK controller_marco/osch_clk_sig_c
--------
3.051 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 92.005ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/timer_cnt_rst (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/timer_cnt[14] (to controller_marco/osch_clk_sig_c +)
Delay: 5.625ns (37.7% logic, 62.3% route), 6 logic levels.
Constraint Details:
5.625ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_860 to controller_marco/POWER_MANAGER_INST/SLICE_171 meets
97.751ns delay constraint less
0.000ns skew and
0.121ns DIN_SET requirement (totaling 97.630ns) by 92.005ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_860 to controller_marco/POWER_MANAGER_INST/SLICE_171:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R8C27C.CLK to R8C27C.Q0 controller_marco/POWER_MANAGER_INST/SLICE_860 (from controller_marco/osch_clk_sig_c)
ROUTE 1 0.815 R8C27C.Q0 to R10C24C.D0 controller_marco/POWER_MANAGER_INST/timer_cnt_rst
CTOF_DEL --- 0.374 R10C24C.D0 to R10C24C.F0 SLICE_2051
ROUTE 16 2.688 R10C24C.F0 to R9C40A.A0 controller_marco/POWER_MANAGER_INST/timer_cnt_rst_i
C0TOFCO_DE --- 0.721 R9C40A.A0 to R9C40A.FCO controller_marco/POWER_MANAGER_INST/SLICE_174
ROUTE 1 0.000 R9C40A.FCO to R9C40B.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[8]
FCITOFCO_D --- 0.119 R9C40B.FCI to R9C40B.FCO controller_marco/POWER_MANAGER_INST/SLICE_173
ROUTE 1 0.000 R9C40B.FCO to R9C40C.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[10]
FCITOFCO_D --- 0.119 R9C40C.FCI to R9C40C.FCO controller_marco/POWER_MANAGER_INST/SLICE_172
ROUTE 1 0.000 R9C40C.FCO to R9C40D.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[12]
FCITOF1_DE --- 0.453 R9C40D.FCI to R9C40D.F1 controller_marco/POWER_MANAGER_INST/SLICE_171
ROUTE 1 0.000 R9C40D.F1 to R9C40D.DI1 controller_marco/POWER_MANAGER_INST/timer_cnt_s[14] (to controller_marco/osch_clk_sig_c)
--------
5.625 (37.7% logic, 62.3% route), 6 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_860:
Name Fanout Delay (ns) Site Resource
ROUTE 17 3.051 OSC.OSC to R8C27C.CLK controller_marco/osch_clk_sig_c
--------
3.051 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_171:
Name Fanout Delay (ns) Site Resource
ROUTE 17 3.051 OSC.OSC to R9C40D.CLK controller_marco/osch_clk_sig_c
--------
3.051 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 92.027ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/timer_cnt_rst (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/timer_cnt[12] (to controller_marco/osch_clk_sig_c +)
Delay: 5.603ns (44.2% logic, 55.8% route), 9 logic levels.
Constraint Details:
5.603ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_860 to controller_marco/POWER_MANAGER_INST/SLICE_172 meets
97.751ns delay constraint less
0.000ns skew and
0.121ns DIN_SET requirement (totaling 97.630ns) by 92.027ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_860 to controller_marco/POWER_MANAGER_INST/SLICE_172:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R8C27C.CLK to R8C27C.Q0 controller_marco/POWER_MANAGER_INST/SLICE_860 (from controller_marco/osch_clk_sig_c)
ROUTE 1 0.815 R8C27C.Q0 to R10C24C.D0 controller_marco/POWER_MANAGER_INST/timer_cnt_rst
CTOF_DEL --- 0.374 R10C24C.D0 to R10C24C.F0 SLICE_2051
ROUTE 16 2.309 R10C24C.F0 to R9C39A.A0 controller_marco/POWER_MANAGER_INST/timer_cnt_rst_i
C0TOFCO_DE --- 0.721 R9C39A.A0 to R9C39A.FCO controller_marco/POWER_MANAGER_INST/SLICE_170
ROUTE 1 0.000 R9C39A.FCO to R9C39B.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[0]
FCITOFCO_D --- 0.119 R9C39B.FCI to R9C39B.FCO controller_marco/POWER_MANAGER_INST/SLICE_177
ROUTE 1 0.000 R9C39B.FCO to R9C39C.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[2]
FCITOFCO_D --- 0.119 R9C39C.FCI to R9C39C.FCO controller_marco/POWER_MANAGER_INST/SLICE_176
ROUTE 1 0.000 R9C39C.FCO to R9C39D.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[4]
FCITOFCO_D --- 0.119 R9C39D.FCI to R9C39D.FCO controller_marco/POWER_MANAGER_INST/SLICE_175
ROUTE 1 0.000 R9C39D.FCO to R9C40A.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[6]
FCITOFCO_D --- 0.119 R9C40A.FCI to R9C40A.FCO controller_marco/POWER_MANAGER_INST/SLICE_174
ROUTE 1 0.000 R9C40A.FCO to R9C40B.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[8]
FCITOFCO_D --- 0.119 R9C40B.FCI to R9C40B.FCO controller_marco/POWER_MANAGER_INST/SLICE_173
ROUTE 1 0.000 R9C40B.FCO to R9C40C.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[10]
FCITOF1_DE --- 0.453 R9C40C.FCI to R9C40C.F1 controller_marco/POWER_MANAGER_INST/SLICE_172
ROUTE 1 0.000 R9C40C.F1 to R9C40C.DI1 controller_marco/POWER_MANAGER_INST/timer_cnt_s[12] (to controller_marco/osch_clk_sig_c)
--------
5.603 (44.2% logic, 55.8% route), 9 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_860:
Name Fanout Delay (ns) Site Resource
ROUTE 17 3.051 OSC.OSC to R8C27C.CLK controller_marco/osch_clk_sig_c
--------
3.051 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_172:
Name Fanout Delay (ns) Site Resource
ROUTE 17 3.051 OSC.OSC to R9C40C.CLK controller_marco/osch_clk_sig_c
--------
3.051 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 92.043ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/timer_cnt_rst (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/timer_cnt[13] (to controller_marco/osch_clk_sig_c +)
Delay: 5.587ns (44.1% logic, 55.9% route), 10 logic levels.
Constraint Details:
5.587ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_860 to controller_marco/POWER_MANAGER_INST/SLICE_171 meets
97.751ns delay constraint less
0.000ns skew and
0.121ns DIN_SET requirement (totaling 97.630ns) by 92.043ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_860 to controller_marco/POWER_MANAGER_INST/SLICE_171:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R8C27C.CLK to R8C27C.Q0 controller_marco/POWER_MANAGER_INST/SLICE_860 (from controller_marco/osch_clk_sig_c)
ROUTE 1 0.815 R8C27C.Q0 to R10C24C.D0 controller_marco/POWER_MANAGER_INST/timer_cnt_rst
CTOF_DEL --- 0.374 R10C24C.D0 to R10C24C.F0 SLICE_2051
ROUTE 16 2.309 R10C24C.F0 to R9C39A.A1 controller_marco/POWER_MANAGER_INST/timer_cnt_rst_i
C1TOFCO_DE --- 0.627 R9C39A.A1 to R9C39A.FCO controller_marco/POWER_MANAGER_INST/SLICE_170
ROUTE 1 0.000 R9C39A.FCO to R9C39B.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[0]
FCITOFCO_D --- 0.119 R9C39B.FCI to R9C39B.FCO controller_marco/POWER_MANAGER_INST/SLICE_177
ROUTE 1 0.000 R9C39B.FCO to R9C39C.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[2]
FCITOFCO_D --- 0.119 R9C39C.FCI to R9C39C.FCO controller_marco/POWER_MANAGER_INST/SLICE_176
ROUTE 1 0.000 R9C39C.FCO to R9C39D.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[4]
FCITOFCO_D --- 0.119 R9C39D.FCI to R9C39D.FCO controller_marco/POWER_MANAGER_INST/SLICE_175
ROUTE 1 0.000 R9C39D.FCO to R9C40A.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[6]
FCITOFCO_D --- 0.119 R9C40A.FCI to R9C40A.FCO controller_marco/POWER_MANAGER_INST/SLICE_174
ROUTE 1 0.000 R9C40A.FCO to R9C40B.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[8]
FCITOFCO_D --- 0.119 R9C40B.FCI to R9C40B.FCO controller_marco/POWER_MANAGER_INST/SLICE_173
ROUTE 1 0.000 R9C40B.FCO to R9C40C.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[10]
FCITOFCO_D --- 0.119 R9C40C.FCI to R9C40C.FCO controller_marco/POWER_MANAGER_INST/SLICE_172
ROUTE 1 0.000 R9C40C.FCO to R9C40D.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[12]
FCITOF0_DE --- 0.412 R9C40D.FCI to R9C40D.F0 controller_marco/POWER_MANAGER_INST/SLICE_171
ROUTE 1 0.000 R9C40D.F0 to R9C40D.DI0 controller_marco/POWER_MANAGER_INST/timer_cnt_s[13] (to controller_marco/osch_clk_sig_c)
--------
5.587 (44.1% logic, 55.9% route), 10 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_860:
Name Fanout Delay (ns) Site Resource
ROUTE 17 3.051 OSC.OSC to R8C27C.CLK controller_marco/osch_clk_sig_c
--------
3.051 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_171:
Name Fanout Delay (ns) Site Resource
ROUTE 17 3.051 OSC.OSC to R9C40D.CLK controller_marco/osch_clk_sig_c
--------
3.051 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 92.046ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/timer_cnt_rst (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/timer_cnt[13] (to controller_marco/osch_clk_sig_c +)
Delay: 5.584ns (37.3% logic, 62.7% route), 6 logic levels.
Constraint Details:
5.584ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_860 to controller_marco/POWER_MANAGER_INST/SLICE_171 meets
97.751ns delay constraint less
0.000ns skew and
0.121ns DIN_SET requirement (totaling 97.630ns) by 92.046ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_860 to controller_marco/POWER_MANAGER_INST/SLICE_171:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R8C27C.CLK to R8C27C.Q0 controller_marco/POWER_MANAGER_INST/SLICE_860 (from controller_marco/osch_clk_sig_c)
ROUTE 1 0.815 R8C27C.Q0 to R10C24C.D0 controller_marco/POWER_MANAGER_INST/timer_cnt_rst
CTOF_DEL --- 0.374 R10C24C.D0 to R10C24C.F0 SLICE_2051
ROUTE 16 2.688 R10C24C.F0 to R9C40A.A0 controller_marco/POWER_MANAGER_INST/timer_cnt_rst_i
C0TOFCO_DE --- 0.721 R9C40A.A0 to R9C40A.FCO controller_marco/POWER_MANAGER_INST/SLICE_174
ROUTE 1 0.000 R9C40A.FCO to R9C40B.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[8]
FCITOFCO_D --- 0.119 R9C40B.FCI to R9C40B.FCO controller_marco/POWER_MANAGER_INST/SLICE_173
ROUTE 1 0.000 R9C40B.FCO to R9C40C.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[10]
FCITOFCO_D --- 0.119 R9C40C.FCI to R9C40C.FCO controller_marco/POWER_MANAGER_INST/SLICE_172
ROUTE 1 0.000 R9C40C.FCO to R9C40D.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[12]
FCITOF0_DE --- 0.412 R9C40D.FCI to R9C40D.F0 controller_marco/POWER_MANAGER_INST/SLICE_171
ROUTE 1 0.000 R9C40D.F0 to R9C40D.DI0 controller_marco/POWER_MANAGER_INST/timer_cnt_s[13] (to controller_marco/osch_clk_sig_c)
--------
5.584 (37.3% logic, 62.7% route), 6 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_860:
Name Fanout Delay (ns) Site Resource
ROUTE 17 3.051 OSC.OSC to R8C27C.CLK controller_marco/osch_clk_sig_c
--------
3.051 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_171:
Name Fanout Delay (ns) Site Resource
ROUTE 17 3.051 OSC.OSC to R9C40D.CLK controller_marco/osch_clk_sig_c
--------
3.051 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 92.068ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/timer_cnt_rst (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/timer_cnt[11] (to controller_marco/osch_clk_sig_c +)
Delay: 5.562ns (43.8% logic, 56.2% route), 9 logic levels.
Constraint Details:
5.562ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_860 to controller_marco/POWER_MANAGER_INST/SLICE_172 meets
97.751ns delay constraint less
0.000ns skew and
0.121ns DIN_SET requirement (totaling 97.630ns) by 92.068ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_860 to controller_marco/POWER_MANAGER_INST/SLICE_172:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R8C27C.CLK to R8C27C.Q0 controller_marco/POWER_MANAGER_INST/SLICE_860 (from controller_marco/osch_clk_sig_c)
ROUTE 1 0.815 R8C27C.Q0 to R10C24C.D0 controller_marco/POWER_MANAGER_INST/timer_cnt_rst
CTOF_DEL --- 0.374 R10C24C.D0 to R10C24C.F0 SLICE_2051
ROUTE 16 2.309 R10C24C.F0 to R9C39A.A0 controller_marco/POWER_MANAGER_INST/timer_cnt_rst_i
C0TOFCO_DE --- 0.721 R9C39A.A0 to R9C39A.FCO controller_marco/POWER_MANAGER_INST/SLICE_170
ROUTE 1 0.000 R9C39A.FCO to R9C39B.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[0]
FCITOFCO_D --- 0.119 R9C39B.FCI to R9C39B.FCO controller_marco/POWER_MANAGER_INST/SLICE_177
ROUTE 1 0.000 R9C39B.FCO to R9C39C.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[2]
FCITOFCO_D --- 0.119 R9C39C.FCI to R9C39C.FCO controller_marco/POWER_MANAGER_INST/SLICE_176
ROUTE 1 0.000 R9C39C.FCO to R9C39D.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[4]
FCITOFCO_D --- 0.119 R9C39D.FCI to R9C39D.FCO controller_marco/POWER_MANAGER_INST/SLICE_175
ROUTE 1 0.000 R9C39D.FCO to R9C40A.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[6]
FCITOFCO_D --- 0.119 R9C40A.FCI to R9C40A.FCO controller_marco/POWER_MANAGER_INST/SLICE_174
ROUTE 1 0.000 R9C40A.FCO to R9C40B.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[8]
FCITOFCO_D --- 0.119 R9C40B.FCI to R9C40B.FCO controller_marco/POWER_MANAGER_INST/SLICE_173
ROUTE 1 0.000 R9C40B.FCO to R9C40C.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[10]
FCITOF0_DE --- 0.412 R9C40C.FCI to R9C40C.F0 controller_marco/POWER_MANAGER_INST/SLICE_172
ROUTE 1 0.000 R9C40C.F0 to R9C40C.DI0 controller_marco/POWER_MANAGER_INST/timer_cnt_s[11] (to controller_marco/osch_clk_sig_c)
--------
5.562 (43.8% logic, 56.2% route), 9 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_860:
Name Fanout Delay (ns) Site Resource
ROUTE 17 3.051 OSC.OSC to R8C27C.CLK controller_marco/osch_clk_sig_c
--------
3.051 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_172:
Name Fanout Delay (ns) Site Resource
ROUTE 17 3.051 OSC.OSC to R9C40C.CLK controller_marco/osch_clk_sig_c
--------
3.051 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 92.099ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/timer_cnt_rst (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/timer_cnt[14] (to controller_marco/osch_clk_sig_c +)
Delay: 5.531ns (36.7% logic, 63.3% route), 6 logic levels.
Constraint Details:
5.531ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_860 to controller_marco/POWER_MANAGER_INST/SLICE_171 meets
97.751ns delay constraint less
0.000ns skew and
0.121ns DIN_SET requirement (totaling 97.630ns) by 92.099ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_860 to controller_marco/POWER_MANAGER_INST/SLICE_171:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R8C27C.CLK to R8C27C.Q0 controller_marco/POWER_MANAGER_INST/SLICE_860 (from controller_marco/osch_clk_sig_c)
ROUTE 1 0.815 R8C27C.Q0 to R10C24C.D0 controller_marco/POWER_MANAGER_INST/timer_cnt_rst
CTOF_DEL --- 0.374 R10C24C.D0 to R10C24C.F0 SLICE_2051
ROUTE 16 2.688 R10C24C.F0 to R9C40A.A1 controller_marco/POWER_MANAGER_INST/timer_cnt_rst_i
C1TOFCO_DE --- 0.627 R9C40A.A1 to R9C40A.FCO controller_marco/POWER_MANAGER_INST/SLICE_174
ROUTE 1 0.000 R9C40A.FCO to R9C40B.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[8]
FCITOFCO_D --- 0.119 R9C40B.FCI to R9C40B.FCO controller_marco/POWER_MANAGER_INST/SLICE_173
ROUTE 1 0.000 R9C40B.FCO to R9C40C.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[10]
FCITOFCO_D --- 0.119 R9C40C.FCI to R9C40C.FCO controller_marco/POWER_MANAGER_INST/SLICE_172
ROUTE 1 0.000 R9C40C.FCO to R9C40D.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[12]
FCITOF1_DE --- 0.453 R9C40D.FCI to R9C40D.F1 controller_marco/POWER_MANAGER_INST/SLICE_171
ROUTE 1 0.000 R9C40D.F1 to R9C40D.DI1 controller_marco/POWER_MANAGER_INST/timer_cnt_s[14] (to controller_marco/osch_clk_sig_c)
--------
5.531 (36.7% logic, 63.3% route), 6 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_860:
Name Fanout Delay (ns) Site Resource
ROUTE 17 3.051 OSC.OSC to R8C27C.CLK controller_marco/osch_clk_sig_c
--------
3.051 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_171:
Name Fanout Delay (ns) Site Resource
ROUTE 17 3.051 OSC.OSC to R9C40D.CLK controller_marco/osch_clk_sig_c
--------
3.051 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 92.121ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/timer_cnt_rst (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/timer_cnt[12] (to controller_marco/osch_clk_sig_c +)
Delay: 5.509ns (43.3% logic, 56.7% route), 9 logic levels.
Constraint Details:
5.509ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_860 to controller_marco/POWER_MANAGER_INST/SLICE_172 meets
97.751ns delay constraint less
0.000ns skew and
0.121ns DIN_SET requirement (totaling 97.630ns) by 92.121ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_860 to controller_marco/POWER_MANAGER_INST/SLICE_172:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R8C27C.CLK to R8C27C.Q0 controller_marco/POWER_MANAGER_INST/SLICE_860 (from controller_marco/osch_clk_sig_c)
ROUTE 1 0.815 R8C27C.Q0 to R10C24C.D0 controller_marco/POWER_MANAGER_INST/timer_cnt_rst
CTOF_DEL --- 0.374 R10C24C.D0 to R10C24C.F0 SLICE_2051
ROUTE 16 2.309 R10C24C.F0 to R9C39A.A1 controller_marco/POWER_MANAGER_INST/timer_cnt_rst_i
C1TOFCO_DE --- 0.627 R9C39A.A1 to R9C39A.FCO controller_marco/POWER_MANAGER_INST/SLICE_170
ROUTE 1 0.000 R9C39A.FCO to R9C39B.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[0]
FCITOFCO_D --- 0.119 R9C39B.FCI to R9C39B.FCO controller_marco/POWER_MANAGER_INST/SLICE_177
ROUTE 1 0.000 R9C39B.FCO to R9C39C.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[2]
FCITOFCO_D --- 0.119 R9C39C.FCI to R9C39C.FCO controller_marco/POWER_MANAGER_INST/SLICE_176
ROUTE 1 0.000 R9C39C.FCO to R9C39D.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[4]
FCITOFCO_D --- 0.119 R9C39D.FCI to R9C39D.FCO controller_marco/POWER_MANAGER_INST/SLICE_175
ROUTE 1 0.000 R9C39D.FCO to R9C40A.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[6]
FCITOFCO_D --- 0.119 R9C40A.FCI to R9C40A.FCO controller_marco/POWER_MANAGER_INST/SLICE_174
ROUTE 1 0.000 R9C40A.FCO to R9C40B.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[8]
FCITOFCO_D --- 0.119 R9C40B.FCI to R9C40B.FCO controller_marco/POWER_MANAGER_INST/SLICE_173
ROUTE 1 0.000 R9C40B.FCO to R9C40C.FCI controller_marco/POWER_MANAGER_INST/timer_cnt_cry[10]
FCITOF1_DE --- 0.453 R9C40C.FCI to R9C40C.F1 controller_marco/POWER_MANAGER_INST/SLICE_172
ROUTE 1 0.000 R9C40C.F1 to R9C40C.DI1 controller_marco/POWER_MANAGER_INST/timer_cnt_s[12] (to controller_marco/osch_clk_sig_c)
--------
5.509 (43.3% logic, 56.7% route), 9 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_860:
Name Fanout Delay (ns) Site Resource
ROUTE 17 3.051 OSC.OSC to R8C27C.CLK controller_marco/osch_clk_sig_c
--------
3.051 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_172:
Name Fanout Delay (ns) Site Resource
ROUTE 17 3.051 OSC.OSC to R9C40C.CLK controller_marco/osch_clk_sig_c
--------
3.051 (0.0% logic, 100.0% route), 0 logic levels.
Report: 171.145MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "tft_clk_c_c" 35.714286 MHz ;
3364 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 7.244ns (weighted slack = 14.488ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/move_view_st[8] (from tft_clk_c_c +)
Destination: FF Data in controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt[20] (to tft_clk_c_c -)
Delay: 6.603ns (43.3% logic, 56.7% route), 13 logic levels.
Constraint Details:
6.603ns physical path delay controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144 meets
13.999ns delay constraint less
0.031ns skew and
0.121ns DIN_SET requirement (totaling 13.847ns) by 7.244ns
Physical Path Details:
Data path controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R11C26B.CLK to R11C26B.Q0 controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 (from tft_clk_c_c)
ROUTE 24 2.711 R11C26B.Q0 to R24C28B.C1 controller_marco/TFTSURFER_DEMO_INST/spi_start_rd_sig
CTOF_DEL --- 0.374 R24C28B.C1 to R24C28B.F1 controller_marco/TFTSURFER_DEMO_INST/SLICE_2730
ROUTE 44 1.031 R24C28B.F1 to R25C28A.A1 controller_marco/TFTSURFER_DEMO_INST/spi_start_rd_sig_i
C1TOFCO_DE --- 0.627 R25C28A.A1 to R25C28A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_154
ROUTE 1 0.000 R25C28A.FCO to R25C28B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[0]
FCITOFCO_D --- 0.119 R25C28B.FCI to R25C28B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_153
ROUTE 1 0.000 R25C28B.FCO to R25C28C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[2]
FCITOFCO_D --- 0.119 R25C28C.FCI to R25C28C.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_152
ROUTE 1 0.000 R25C28C.FCO to R25C28D.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[4]
FCITOFCO_D --- 0.119 R25C28D.FCI to R25C28D.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_151
ROUTE 1 0.000 R25C28D.FCO to R25C29A.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[6]
FCITOFCO_D --- 0.119 R25C29A.FCI to R25C29A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_150
ROUTE 1 0.000 R25C29A.FCO to R25C29B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[8]
FCITOFCO_D --- 0.119 R25C29B.FCI to R25C29B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_149
ROUTE 1 0.000 R25C29B.FCO to R25C29C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[10]
FCITOFCO_D --- 0.119 R25C29C.FCI to R25C29C.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_148
ROUTE 1 0.000 R25C29C.FCO to R25C29D.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[12]
FCITOFCO_D --- 0.119 R25C29D.FCI to R25C29D.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_147
ROUTE 1 0.000 R25C29D.FCO to R25C30A.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[14]
FCITOFCO_D --- 0.119 R25C30A.FCI to R25C30A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_146
ROUTE 1 0.000 R25C30A.FCO to R25C30B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[16]
FCITOFCO_D --- 0.119 R25C30B.FCI to R25C30B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145
ROUTE 1 0.000 R25C30B.FCO to R25C30C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[18]
FCITOF1_DE --- 0.453 R25C30C.FCI to R25C30C.F1 controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144
ROUTE 1 0.000 R25C30C.F1 to R25C30C.DI1 controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_s[20] (to tft_clk_c_c)
--------
6.603 (43.3% logic, 56.7% route), 13 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989:
Name Fanout Delay (ns) Site Resource
ROUTE 287 1.412 LPLL.CLKOS3 to R11C26B.CLK tft_clk_c_c
--------
1.412 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144:
Name Fanout Delay (ns) Site Resource
ROUTE 287 1.381 LPLL.CLKOS3 to R25C30C.CLK tft_clk_c_c
--------
1.381 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.257ns (weighted slack = 14.514ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/move_view_st[8] (from tft_clk_c_c +)
Destination: FF Data in controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt[20] (to tft_clk_c_c -)
Delay: 6.590ns (43.0% logic, 57.0% route), 12 logic levels.
Constraint Details:
6.590ns physical path delay controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144 meets
13.999ns delay constraint less
0.031ns skew and
0.121ns DIN_SET requirement (totaling 13.847ns) by 7.257ns
Physical Path Details:
Data path controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R11C26B.CLK to R11C26B.Q0 controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 (from tft_clk_c_c)
ROUTE 24 2.711 R11C26B.Q0 to R24C28B.C1 controller_marco/TFTSURFER_DEMO_INST/spi_start_rd_sig
CTOF_DEL --- 0.374 R24C28B.C1 to R24C28B.F1 controller_marco/TFTSURFER_DEMO_INST/SLICE_2730
ROUTE 44 1.043 R24C28B.F1 to R25C28B.A0 controller_marco/TFTSURFER_DEMO_INST/spi_start_rd_sig_i
C0TOFCO_DE --- 0.721 R25C28B.A0 to R25C28B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_153
ROUTE 1 0.000 R25C28B.FCO to R25C28C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[2]
FCITOFCO_D --- 0.119 R25C28C.FCI to R25C28C.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_152
ROUTE 1 0.000 R25C28C.FCO to R25C28D.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[4]
FCITOFCO_D --- 0.119 R25C28D.FCI to R25C28D.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_151
ROUTE 1 0.000 R25C28D.FCO to R25C29A.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[6]
FCITOFCO_D --- 0.119 R25C29A.FCI to R25C29A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_150
ROUTE 1 0.000 R25C29A.FCO to R25C29B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[8]
FCITOFCO_D --- 0.119 R25C29B.FCI to R25C29B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_149
ROUTE 1 0.000 R25C29B.FCO to R25C29C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[10]
FCITOFCO_D --- 0.119 R25C29C.FCI to R25C29C.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_148
ROUTE 1 0.000 R25C29C.FCO to R25C29D.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[12]
FCITOFCO_D --- 0.119 R25C29D.FCI to R25C29D.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_147
ROUTE 1 0.000 R25C29D.FCO to R25C30A.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[14]
FCITOFCO_D --- 0.119 R25C30A.FCI to R25C30A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_146
ROUTE 1 0.000 R25C30A.FCO to R25C30B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[16]
FCITOFCO_D --- 0.119 R25C30B.FCI to R25C30B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145
ROUTE 1 0.000 R25C30B.FCO to R25C30C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[18]
FCITOF1_DE --- 0.453 R25C30C.FCI to R25C30C.F1 controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144
ROUTE 1 0.000 R25C30C.F1 to R25C30C.DI1 controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_s[20] (to tft_clk_c_c)
--------
6.590 (43.0% logic, 57.0% route), 12 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989:
Name Fanout Delay (ns) Site Resource
ROUTE 287 1.412 LPLL.CLKOS3 to R11C26B.CLK tft_clk_c_c
--------
1.412 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144:
Name Fanout Delay (ns) Site Resource
ROUTE 287 1.381 LPLL.CLKOS3 to R25C30C.CLK tft_clk_c_c
--------
1.381 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.285ns (weighted slack = 14.570ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/move_view_st[8] (from tft_clk_c_c +)
Destination: FF Data in controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt[19] (to tft_clk_c_c -)
Delay: 6.562ns (43.0% logic, 57.0% route), 13 logic levels.
Constraint Details:
6.562ns physical path delay controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144 meets
13.999ns delay constraint less
0.031ns skew and
0.121ns DIN_SET requirement (totaling 13.847ns) by 7.285ns
Physical Path Details:
Data path controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R11C26B.CLK to R11C26B.Q0 controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 (from tft_clk_c_c)
ROUTE 24 2.711 R11C26B.Q0 to R24C28B.C1 controller_marco/TFTSURFER_DEMO_INST/spi_start_rd_sig
CTOF_DEL --- 0.374 R24C28B.C1 to R24C28B.F1 controller_marco/TFTSURFER_DEMO_INST/SLICE_2730
ROUTE 44 1.031 R24C28B.F1 to R25C28A.A1 controller_marco/TFTSURFER_DEMO_INST/spi_start_rd_sig_i
C1TOFCO_DE --- 0.627 R25C28A.A1 to R25C28A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_154
ROUTE 1 0.000 R25C28A.FCO to R25C28B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[0]
FCITOFCO_D --- 0.119 R25C28B.FCI to R25C28B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_153
ROUTE 1 0.000 R25C28B.FCO to R25C28C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[2]
FCITOFCO_D --- 0.119 R25C28C.FCI to R25C28C.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_152
ROUTE 1 0.000 R25C28C.FCO to R25C28D.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[4]
FCITOFCO_D --- 0.119 R25C28D.FCI to R25C28D.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_151
ROUTE 1 0.000 R25C28D.FCO to R25C29A.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[6]
FCITOFCO_D --- 0.119 R25C29A.FCI to R25C29A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_150
ROUTE 1 0.000 R25C29A.FCO to R25C29B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[8]
FCITOFCO_D --- 0.119 R25C29B.FCI to R25C29B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_149
ROUTE 1 0.000 R25C29B.FCO to R25C29C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[10]
FCITOFCO_D --- 0.119 R25C29C.FCI to R25C29C.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_148
ROUTE 1 0.000 R25C29C.FCO to R25C29D.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[12]
FCITOFCO_D --- 0.119 R25C29D.FCI to R25C29D.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_147
ROUTE 1 0.000 R25C29D.FCO to R25C30A.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[14]
FCITOFCO_D --- 0.119 R25C30A.FCI to R25C30A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_146
ROUTE 1 0.000 R25C30A.FCO to R25C30B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[16]
FCITOFCO_D --- 0.119 R25C30B.FCI to R25C30B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145
ROUTE 1 0.000 R25C30B.FCO to R25C30C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[18]
FCITOF0_DE --- 0.412 R25C30C.FCI to R25C30C.F0 controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144
ROUTE 1 0.000 R25C30C.F0 to R25C30C.DI0 controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_s[19] (to tft_clk_c_c)
--------
6.562 (43.0% logic, 57.0% route), 13 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989:
Name Fanout Delay (ns) Site Resource
ROUTE 287 1.412 LPLL.CLKOS3 to R11C26B.CLK tft_clk_c_c
--------
1.412 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144:
Name Fanout Delay (ns) Site Resource
ROUTE 287 1.381 LPLL.CLKOS3 to R25C30C.CLK tft_clk_c_c
--------
1.381 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.298ns (weighted slack = 14.596ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/move_view_st[8] (from tft_clk_c_c +)
Destination: FF Data in controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt[19] (to tft_clk_c_c -)
Delay: 6.549ns (42.7% logic, 57.3% route), 12 logic levels.
Constraint Details:
6.549ns physical path delay controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144 meets
13.999ns delay constraint less
0.031ns skew and
0.121ns DIN_SET requirement (totaling 13.847ns) by 7.298ns
Physical Path Details:
Data path controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R11C26B.CLK to R11C26B.Q0 controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 (from tft_clk_c_c)
ROUTE 24 2.711 R11C26B.Q0 to R24C28B.C1 controller_marco/TFTSURFER_DEMO_INST/spi_start_rd_sig
CTOF_DEL --- 0.374 R24C28B.C1 to R24C28B.F1 controller_marco/TFTSURFER_DEMO_INST/SLICE_2730
ROUTE 44 1.043 R24C28B.F1 to R25C28B.A0 controller_marco/TFTSURFER_DEMO_INST/spi_start_rd_sig_i
C0TOFCO_DE --- 0.721 R25C28B.A0 to R25C28B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_153
ROUTE 1 0.000 R25C28B.FCO to R25C28C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[2]
FCITOFCO_D --- 0.119 R25C28C.FCI to R25C28C.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_152
ROUTE 1 0.000 R25C28C.FCO to R25C28D.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[4]
FCITOFCO_D --- 0.119 R25C28D.FCI to R25C28D.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_151
ROUTE 1 0.000 R25C28D.FCO to R25C29A.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[6]
FCITOFCO_D --- 0.119 R25C29A.FCI to R25C29A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_150
ROUTE 1 0.000 R25C29A.FCO to R25C29B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[8]
FCITOFCO_D --- 0.119 R25C29B.FCI to R25C29B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_149
ROUTE 1 0.000 R25C29B.FCO to R25C29C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[10]
FCITOFCO_D --- 0.119 R25C29C.FCI to R25C29C.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_148
ROUTE 1 0.000 R25C29C.FCO to R25C29D.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[12]
FCITOFCO_D --- 0.119 R25C29D.FCI to R25C29D.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_147
ROUTE 1 0.000 R25C29D.FCO to R25C30A.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[14]
FCITOFCO_D --- 0.119 R25C30A.FCI to R25C30A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_146
ROUTE 1 0.000 R25C30A.FCO to R25C30B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[16]
FCITOFCO_D --- 0.119 R25C30B.FCI to R25C30B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145
ROUTE 1 0.000 R25C30B.FCO to R25C30C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[18]
FCITOF0_DE --- 0.412 R25C30C.FCI to R25C30C.F0 controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144
ROUTE 1 0.000 R25C30C.F0 to R25C30C.DI0 controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_s[19] (to tft_clk_c_c)
--------
6.549 (42.7% logic, 57.3% route), 12 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989:
Name Fanout Delay (ns) Site Resource
ROUTE 287 1.412 LPLL.CLKOS3 to R11C26B.CLK tft_clk_c_c
--------
1.412 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144:
Name Fanout Delay (ns) Site Resource
ROUTE 287 1.381 LPLL.CLKOS3 to R25C30C.CLK tft_clk_c_c
--------
1.381 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.351ns (weighted slack = 14.702ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/move_view_st[8] (from tft_clk_c_c +)
Destination: FF Data in controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt[20] (to tft_clk_c_c -)
Delay: 6.496ns (42.2% logic, 57.8% route), 12 logic levels.
Constraint Details:
6.496ns physical path delay controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144 meets
13.999ns delay constraint less
0.031ns skew and
0.121ns DIN_SET requirement (totaling 13.847ns) by 7.351ns
Physical Path Details:
Data path controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R11C26B.CLK to R11C26B.Q0 controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 (from tft_clk_c_c)
ROUTE 24 2.711 R11C26B.Q0 to R24C28B.C1 controller_marco/TFTSURFER_DEMO_INST/spi_start_rd_sig
CTOF_DEL --- 0.374 R24C28B.C1 to R24C28B.F1 controller_marco/TFTSURFER_DEMO_INST/SLICE_2730
ROUTE 44 1.043 R24C28B.F1 to R25C28B.A1 controller_marco/TFTSURFER_DEMO_INST/spi_start_rd_sig_i
C1TOFCO_DE --- 0.627 R25C28B.A1 to R25C28B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_153
ROUTE 1 0.000 R25C28B.FCO to R25C28C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[2]
FCITOFCO_D --- 0.119 R25C28C.FCI to R25C28C.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_152
ROUTE 1 0.000 R25C28C.FCO to R25C28D.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[4]
FCITOFCO_D --- 0.119 R25C28D.FCI to R25C28D.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_151
ROUTE 1 0.000 R25C28D.FCO to R25C29A.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[6]
FCITOFCO_D --- 0.119 R25C29A.FCI to R25C29A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_150
ROUTE 1 0.000 R25C29A.FCO to R25C29B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[8]
FCITOFCO_D --- 0.119 R25C29B.FCI to R25C29B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_149
ROUTE 1 0.000 R25C29B.FCO to R25C29C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[10]
FCITOFCO_D --- 0.119 R25C29C.FCI to R25C29C.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_148
ROUTE 1 0.000 R25C29C.FCO to R25C29D.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[12]
FCITOFCO_D --- 0.119 R25C29D.FCI to R25C29D.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_147
ROUTE 1 0.000 R25C29D.FCO to R25C30A.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[14]
FCITOFCO_D --- 0.119 R25C30A.FCI to R25C30A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_146
ROUTE 1 0.000 R25C30A.FCO to R25C30B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[16]
FCITOFCO_D --- 0.119 R25C30B.FCI to R25C30B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145
ROUTE 1 0.000 R25C30B.FCO to R25C30C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[18]
FCITOF1_DE --- 0.453 R25C30C.FCI to R25C30C.F1 controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144
ROUTE 1 0.000 R25C30C.F1 to R25C30C.DI1 controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_s[20] (to tft_clk_c_c)
--------
6.496 (42.2% logic, 57.8% route), 12 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989:
Name Fanout Delay (ns) Site Resource
ROUTE 287 1.412 LPLL.CLKOS3 to R11C26B.CLK tft_clk_c_c
--------
1.412 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144:
Name Fanout Delay (ns) Site Resource
ROUTE 287 1.381 LPLL.CLKOS3 to R25C30C.CLK tft_clk_c_c
--------
1.381 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.363ns (weighted slack = 14.726ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/move_view_st[8] (from tft_clk_c_c +)
Destination: FF Data in controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt[18] (to tft_clk_c_c -)
Delay: 6.484ns (42.3% logic, 57.7% route), 12 logic levels.
Constraint Details:
6.484ns physical path delay controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145 meets
13.999ns delay constraint less
0.031ns skew and
0.121ns DIN_SET requirement (totaling 13.847ns) by 7.363ns
Physical Path Details:
Data path controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R11C26B.CLK to R11C26B.Q0 controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 (from tft_clk_c_c)
ROUTE 24 2.711 R11C26B.Q0 to R24C28B.C1 controller_marco/TFTSURFER_DEMO_INST/spi_start_rd_sig
CTOF_DEL --- 0.374 R24C28B.C1 to R24C28B.F1 controller_marco/TFTSURFER_DEMO_INST/SLICE_2730
ROUTE 44 1.031 R24C28B.F1 to R25C28A.A1 controller_marco/TFTSURFER_DEMO_INST/spi_start_rd_sig_i
C1TOFCO_DE --- 0.627 R25C28A.A1 to R25C28A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_154
ROUTE 1 0.000 R25C28A.FCO to R25C28B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[0]
FCITOFCO_D --- 0.119 R25C28B.FCI to R25C28B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_153
ROUTE 1 0.000 R25C28B.FCO to R25C28C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[2]
FCITOFCO_D --- 0.119 R25C28C.FCI to R25C28C.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_152
ROUTE 1 0.000 R25C28C.FCO to R25C28D.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[4]
FCITOFCO_D --- 0.119 R25C28D.FCI to R25C28D.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_151
ROUTE 1 0.000 R25C28D.FCO to R25C29A.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[6]
FCITOFCO_D --- 0.119 R25C29A.FCI to R25C29A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_150
ROUTE 1 0.000 R25C29A.FCO to R25C29B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[8]
FCITOFCO_D --- 0.119 R25C29B.FCI to R25C29B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_149
ROUTE 1 0.000 R25C29B.FCO to R25C29C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[10]
FCITOFCO_D --- 0.119 R25C29C.FCI to R25C29C.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_148
ROUTE 1 0.000 R25C29C.FCO to R25C29D.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[12]
FCITOFCO_D --- 0.119 R25C29D.FCI to R25C29D.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_147
ROUTE 1 0.000 R25C29D.FCO to R25C30A.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[14]
FCITOFCO_D --- 0.119 R25C30A.FCI to R25C30A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_146
ROUTE 1 0.000 R25C30A.FCO to R25C30B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[16]
FCITOF1_DE --- 0.453 R25C30B.FCI to R25C30B.F1 controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145
ROUTE 1 0.000 R25C30B.F1 to R25C30B.DI1 controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_s[18] (to tft_clk_c_c)
--------
6.484 (42.3% logic, 57.7% route), 12 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989:
Name Fanout Delay (ns) Site Resource
ROUTE 287 1.412 LPLL.CLKOS3 to R11C26B.CLK tft_clk_c_c
--------
1.412 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145:
Name Fanout Delay (ns) Site Resource
ROUTE 287 1.381 LPLL.CLKOS3 to R25C30B.CLK tft_clk_c_c
--------
1.381 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.376ns (weighted slack = 14.752ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/move_view_st[8] (from tft_clk_c_c +)
Destination: FF Data in controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt[18] (to tft_clk_c_c -)
Delay: 6.471ns (42.0% logic, 58.0% route), 11 logic levels.
Constraint Details:
6.471ns physical path delay controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145 meets
13.999ns delay constraint less
0.031ns skew and
0.121ns DIN_SET requirement (totaling 13.847ns) by 7.376ns
Physical Path Details:
Data path controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R11C26B.CLK to R11C26B.Q0 controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 (from tft_clk_c_c)
ROUTE 24 2.711 R11C26B.Q0 to R24C28B.C1 controller_marco/TFTSURFER_DEMO_INST/spi_start_rd_sig
CTOF_DEL --- 0.374 R24C28B.C1 to R24C28B.F1 controller_marco/TFTSURFER_DEMO_INST/SLICE_2730
ROUTE 44 1.043 R24C28B.F1 to R25C28B.A0 controller_marco/TFTSURFER_DEMO_INST/spi_start_rd_sig_i
C0TOFCO_DE --- 0.721 R25C28B.A0 to R25C28B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_153
ROUTE 1 0.000 R25C28B.FCO to R25C28C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[2]
FCITOFCO_D --- 0.119 R25C28C.FCI to R25C28C.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_152
ROUTE 1 0.000 R25C28C.FCO to R25C28D.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[4]
FCITOFCO_D --- 0.119 R25C28D.FCI to R25C28D.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_151
ROUTE 1 0.000 R25C28D.FCO to R25C29A.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[6]
FCITOFCO_D --- 0.119 R25C29A.FCI to R25C29A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_150
ROUTE 1 0.000 R25C29A.FCO to R25C29B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[8]
FCITOFCO_D --- 0.119 R25C29B.FCI to R25C29B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_149
ROUTE 1 0.000 R25C29B.FCO to R25C29C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[10]
FCITOFCO_D --- 0.119 R25C29C.FCI to R25C29C.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_148
ROUTE 1 0.000 R25C29C.FCO to R25C29D.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[12]
FCITOFCO_D --- 0.119 R25C29D.FCI to R25C29D.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_147
ROUTE 1 0.000 R25C29D.FCO to R25C30A.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[14]
FCITOFCO_D --- 0.119 R25C30A.FCI to R25C30A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_146
ROUTE 1 0.000 R25C30A.FCO to R25C30B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[16]
FCITOF1_DE --- 0.453 R25C30B.FCI to R25C30B.F1 controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145
ROUTE 1 0.000 R25C30B.F1 to R25C30B.DI1 controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_s[18] (to tft_clk_c_c)
--------
6.471 (42.0% logic, 58.0% route), 11 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989:
Name Fanout Delay (ns) Site Resource
ROUTE 287 1.412 LPLL.CLKOS3 to R11C26B.CLK tft_clk_c_c
--------
1.412 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145:
Name Fanout Delay (ns) Site Resource
ROUTE 287 1.381 LPLL.CLKOS3 to R25C30B.CLK tft_clk_c_c
--------
1.381 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.392ns (weighted slack = 14.784ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/move_view_st[8] (from tft_clk_c_c +)
Destination: FF Data in controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt[19] (to tft_clk_c_c -)
Delay: 6.455ns (41.8% logic, 58.2% route), 12 logic levels.
Constraint Details:
6.455ns physical path delay controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144 meets
13.999ns delay constraint less
0.031ns skew and
0.121ns DIN_SET requirement (totaling 13.847ns) by 7.392ns
Physical Path Details:
Data path controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R11C26B.CLK to R11C26B.Q0 controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 (from tft_clk_c_c)
ROUTE 24 2.711 R11C26B.Q0 to R24C28B.C1 controller_marco/TFTSURFER_DEMO_INST/spi_start_rd_sig
CTOF_DEL --- 0.374 R24C28B.C1 to R24C28B.F1 controller_marco/TFTSURFER_DEMO_INST/SLICE_2730
ROUTE 44 1.043 R24C28B.F1 to R25C28B.A1 controller_marco/TFTSURFER_DEMO_INST/spi_start_rd_sig_i
C1TOFCO_DE --- 0.627 R25C28B.A1 to R25C28B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_153
ROUTE 1 0.000 R25C28B.FCO to R25C28C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[2]
FCITOFCO_D --- 0.119 R25C28C.FCI to R25C28C.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_152
ROUTE 1 0.000 R25C28C.FCO to R25C28D.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[4]
FCITOFCO_D --- 0.119 R25C28D.FCI to R25C28D.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_151
ROUTE 1 0.000 R25C28D.FCO to R25C29A.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[6]
FCITOFCO_D --- 0.119 R25C29A.FCI to R25C29A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_150
ROUTE 1 0.000 R25C29A.FCO to R25C29B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[8]
FCITOFCO_D --- 0.119 R25C29B.FCI to R25C29B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_149
ROUTE 1 0.000 R25C29B.FCO to R25C29C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[10]
FCITOFCO_D --- 0.119 R25C29C.FCI to R25C29C.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_148
ROUTE 1 0.000 R25C29C.FCO to R25C29D.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[12]
FCITOFCO_D --- 0.119 R25C29D.FCI to R25C29D.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_147
ROUTE 1 0.000 R25C29D.FCO to R25C30A.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[14]
FCITOFCO_D --- 0.119 R25C30A.FCI to R25C30A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_146
ROUTE 1 0.000 R25C30A.FCO to R25C30B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[16]
FCITOFCO_D --- 0.119 R25C30B.FCI to R25C30B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145
ROUTE 1 0.000 R25C30B.FCO to R25C30C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[18]
FCITOF0_DE --- 0.412 R25C30C.FCI to R25C30C.F0 controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144
ROUTE 1 0.000 R25C30C.F0 to R25C30C.DI0 controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_s[19] (to tft_clk_c_c)
--------
6.455 (41.8% logic, 58.2% route), 12 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989:
Name Fanout Delay (ns) Site Resource
ROUTE 287 1.412 LPLL.CLKOS3 to R11C26B.CLK tft_clk_c_c
--------
1.412 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_144:
Name Fanout Delay (ns) Site Resource
ROUTE 287 1.381 LPLL.CLKOS3 to R25C30C.CLK tft_clk_c_c
--------
1.381 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.404ns (weighted slack = 14.808ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/move_view_st[8] (from tft_clk_c_c +)
Destination: FF Data in controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt[17] (to tft_clk_c_c -)
Delay: 6.443ns (41.9% logic, 58.1% route), 12 logic levels.
Constraint Details:
6.443ns physical path delay controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145 meets
13.999ns delay constraint less
0.031ns skew and
0.121ns DIN_SET requirement (totaling 13.847ns) by 7.404ns
Physical Path Details:
Data path controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R11C26B.CLK to R11C26B.Q0 controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 (from tft_clk_c_c)
ROUTE 24 2.711 R11C26B.Q0 to R24C28B.C1 controller_marco/TFTSURFER_DEMO_INST/spi_start_rd_sig
CTOF_DEL --- 0.374 R24C28B.C1 to R24C28B.F1 controller_marco/TFTSURFER_DEMO_INST/SLICE_2730
ROUTE 44 1.031 R24C28B.F1 to R25C28A.A1 controller_marco/TFTSURFER_DEMO_INST/spi_start_rd_sig_i
C1TOFCO_DE --- 0.627 R25C28A.A1 to R25C28A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_154
ROUTE 1 0.000 R25C28A.FCO to R25C28B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[0]
FCITOFCO_D --- 0.119 R25C28B.FCI to R25C28B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_153
ROUTE 1 0.000 R25C28B.FCO to R25C28C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[2]
FCITOFCO_D --- 0.119 R25C28C.FCI to R25C28C.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_152
ROUTE 1 0.000 R25C28C.FCO to R25C28D.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[4]
FCITOFCO_D --- 0.119 R25C28D.FCI to R25C28D.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_151
ROUTE 1 0.000 R25C28D.FCO to R25C29A.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[6]
FCITOFCO_D --- 0.119 R25C29A.FCI to R25C29A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_150
ROUTE 1 0.000 R25C29A.FCO to R25C29B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[8]
FCITOFCO_D --- 0.119 R25C29B.FCI to R25C29B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_149
ROUTE 1 0.000 R25C29B.FCO to R25C29C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[10]
FCITOFCO_D --- 0.119 R25C29C.FCI to R25C29C.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_148
ROUTE 1 0.000 R25C29C.FCO to R25C29D.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[12]
FCITOFCO_D --- 0.119 R25C29D.FCI to R25C29D.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_147
ROUTE 1 0.000 R25C29D.FCO to R25C30A.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[14]
FCITOFCO_D --- 0.119 R25C30A.FCI to R25C30A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_146
ROUTE 1 0.000 R25C30A.FCO to R25C30B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[16]
FCITOF0_DE --- 0.412 R25C30B.FCI to R25C30B.F0 controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145
ROUTE 1 0.000 R25C30B.F0 to R25C30B.DI0 controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_s[17] (to tft_clk_c_c)
--------
6.443 (41.9% logic, 58.1% route), 12 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989:
Name Fanout Delay (ns) Site Resource
ROUTE 287 1.412 LPLL.CLKOS3 to R11C26B.CLK tft_clk_c_c
--------
1.412 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145:
Name Fanout Delay (ns) Site Resource
ROUTE 287 1.381 LPLL.CLKOS3 to R25C30B.CLK tft_clk_c_c
--------
1.381 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 7.417ns (weighted slack = 14.834ns)
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/move_view_st[8] (from tft_clk_c_c +)
Destination: FF Data in controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt[17] (to tft_clk_c_c -)
Delay: 6.430ns (41.6% logic, 58.4% route), 11 logic levels.
Constraint Details:
6.430ns physical path delay controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145 meets
13.999ns delay constraint less
0.031ns skew and
0.121ns DIN_SET requirement (totaling 13.847ns) by 7.417ns
Physical Path Details:
Data path controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R11C26B.CLK to R11C26B.Q0 controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989 (from tft_clk_c_c)
ROUTE 24 2.711 R11C26B.Q0 to R24C28B.C1 controller_marco/TFTSURFER_DEMO_INST/spi_start_rd_sig
CTOF_DEL --- 0.374 R24C28B.C1 to R24C28B.F1 controller_marco/TFTSURFER_DEMO_INST/SLICE_2730
ROUTE 44 1.043 R24C28B.F1 to R25C28B.A0 controller_marco/TFTSURFER_DEMO_INST/spi_start_rd_sig_i
C0TOFCO_DE --- 0.721 R25C28B.A0 to R25C28B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_153
ROUTE 1 0.000 R25C28B.FCO to R25C28C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[2]
FCITOFCO_D --- 0.119 R25C28C.FCI to R25C28C.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_152
ROUTE 1 0.000 R25C28C.FCO to R25C28D.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[4]
FCITOFCO_D --- 0.119 R25C28D.FCI to R25C28D.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_151
ROUTE 1 0.000 R25C28D.FCO to R25C29A.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[6]
FCITOFCO_D --- 0.119 R25C29A.FCI to R25C29A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_150
ROUTE 1 0.000 R25C29A.FCO to R25C29B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[8]
FCITOFCO_D --- 0.119 R25C29B.FCI to R25C29B.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_149
ROUTE 1 0.000 R25C29B.FCO to R25C29C.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[10]
FCITOFCO_D --- 0.119 R25C29C.FCI to R25C29C.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_148
ROUTE 1 0.000 R25C29C.FCO to R25C29D.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[12]
FCITOFCO_D --- 0.119 R25C29D.FCI to R25C29D.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_147
ROUTE 1 0.000 R25C29D.FCO to R25C30A.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[14]
FCITOFCO_D --- 0.119 R25C30A.FCI to R25C30A.FCO controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_146
ROUTE 1 0.000 R25C30A.FCO to R25C30B.FCI controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_cry[16]
FCITOF0_DE --- 0.412 R25C30B.FCI to R25C30B.F0 controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145
ROUTE 1 0.000 R25C30B.F0 to R25C30B.DI0 controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/spi_byte_cnt_s[17] (to tft_clk_c_c)
--------
6.430 (41.6% logic, 58.4% route), 11 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_989:
Name Fanout Delay (ns) Site Resource
ROUTE 287 1.412 LPLL.CLKOS3 to R11C26B.CLK tft_clk_c_c
--------
1.412 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/SPI_FLASH_READER_INST/SLICE_145:
Name Fanout Delay (ns) Site Resource
ROUTE 287 1.381 LPLL.CLKOS3 to R25C30B.CLK tft_clk_c_c
--------
1.381 (0.0% logic, 100.0% route), 0 logic levels.
Report: 74.019MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY PORT "ext_osc_clk" 25.000000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 33.340ns
The internal maximum frequency of the following component is 150.150 MHz
Logical Details: Cell type Pin name Component name
Destination: PIO PAD ext_osc_clk
Delay: 6.660ns -- based on Minimum Pulse Width
Report: 150.150MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "ext_osc_clk_c" 25.000000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 21.638ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm32_inst/platform_u/LM32/cpu/operand_0_x_fast[7] (from ext_osc_clk_c +)
Destination: FF Data in lm32_inst/platform_u/LM32/cpu/multiplier/product[31] (to ext_osc_clk_c +)
Delay: 18.241ns (28.5% logic, 71.5% route), 17 logic levels.
Constraint Details:
18.241ns physical path delay lm32_inst/platform_u/LM32/cpu/SLICE_1680 to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292 meets
40.000ns delay constraint less
0.000ns skew and
0.121ns DIN_SET requirement (totaling 39.879ns) by 21.638ns
Physical Path Details:
Data path lm32_inst/platform_u/LM32/cpu/SLICE_1680 to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R7C9D.CLK to R7C9D.Q1 lm32_inst/platform_u/LM32/cpu/SLICE_1680 (from ext_osc_clk_c)
ROUTE 5 2.311 R7C9D.Q1 to R3C6D.D1 lm32_inst/platform_u/LM32/cpu/operand_0_x_fast[7]
C1TOFCO_DE --- 0.627 R3C6D.D1 to R3C6D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_457
ROUTE 1 0.000 R3C6D.FCO to R3C7A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_7
FCITOFCO_D --- 0.119 R3C7A.FCI to R3C7A.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_456
ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_9
FCITOFCO_D --- 0.119 R3C7B.FCI to R3C7B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_455
ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_11
FCITOFCO_D --- 0.119 R3C7C.FCI to R3C7C.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_454
ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_13
FCITOFCO_D --- 0.119 R3C7D.FCI to R3C7D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_453
ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_15
FCITOFCO_D --- 0.119 R3C8A.FCI to R3C8A.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_452
ROUTE 1 0.000 R3C8A.FCO to R3C8B.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_17
FCITOFCO_D --- 0.119 R3C8B.FCI to R3C8B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_451
ROUTE 1 0.000 R3C8B.FCO to R3C8C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_19
FCITOF0_DE --- 0.412 R3C8C.FCI to R3C8C.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_450
ROUTE 1 3.336 R3C8C.F0 to R10C7B.B1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2[24]
C1TOFCO_DE --- 0.627 R10C7B.B1 to R10C7B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_232
ROUTE 1 0.000 R10C7B.FCO to R10C7C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_4
FCITOFCO_D --- 0.119 R10C7C.FCI to R10C7C.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_231
ROUTE 1 0.000 R10C7C.FCO to R10C7D.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_6
FCITOFCO_D --- 0.119 R10C7D.FCI to R10C7D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_230
ROUTE 1 0.000 R10C7D.FCO to R10C8A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_8
FCITOF1_DE --- 0.453 R10C8A.FCI to R10C8A.F1 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_229
ROUTE 1 3.227 R10C8A.F1 to R7C5B.A1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21[30]
CTOF_DEL --- 0.374 R7C5B.A1 to R7C5B.F1 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_254
ROUTE 1 2.957 R7C5B.F1 to R2C8D.A1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_25[30]
C1TOFCO_DE --- 0.627 R2C8D.A1 to R2C8D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_288
ROUTE 1 0.000 R2C8D.FCO to R2C9A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_29_cry_14
FCITOF0_DE --- 0.412 R2C9A.FCI to R2C9A.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_287
ROUTE 1 1.216 R2C9A.F0 to R4C10A.A0 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_29[31]
CTOF_DEL --- 0.374 R4C10A.A0 to R4C10A.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292
ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 lm32_inst/platform_u/LM32/cpu/multiplier/product_2[31] (to ext_osc_clk_c)
--------
18.241 (28.5% logic, 71.5% route), 17 logic levels.
Clock Skew Details:
Source Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/SLICE_1680:
Name Fanout Delay (ns) Site Resource
ROUTE 999 5.360 3.PADDI to R7C9D.CLK ext_osc_clk_c
--------
5.360 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292:
Name Fanout Delay (ns) Site Resource
ROUTE 999 5.360 3.PADDI to R4C10A.CLK ext_osc_clk_c
--------
5.360 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 21.642ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm32_inst/platform_u/LM32/cpu/operand_0_x[12] (from ext_osc_clk_c +)
Destination: FF Data in lm32_inst/platform_u/LM32/cpu/multiplier/product[31] (to ext_osc_clk_c +)
Delay: 18.237ns (26.5% logic, 73.5% route), 14 logic levels.
Constraint Details:
18.237ns physical path delay lm32_inst/platform_u/LM32/cpu/SLICE_1655 to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292 meets
40.000ns delay constraint less
0.000ns skew and
0.121ns DIN_SET requirement (totaling 39.879ns) by 21.642ns
Physical Path Details:
Data path lm32_inst/platform_u/LM32/cpu/SLICE_1655 to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R7C12C.CLK to R7C12C.Q0 lm32_inst/platform_u/LM32/cpu/SLICE_1655 (from ext_osc_clk_c)
ROUTE 24 2.664 R7C12C.Q0 to R3C7C.A1 lm32_inst/platform_u/LM32/cpu/operand_0_x[12]
C1TOFCO_DE --- 0.627 R3C7C.A1 to R3C7C.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_454
ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_13
FCITOFCO_D --- 0.119 R3C7D.FCI to R3C7D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_453
ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_15
FCITOFCO_D --- 0.119 R3C8A.FCI to R3C8A.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_452
ROUTE 1 0.000 R3C8A.FCO to R3C8B.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_17
FCITOFCO_D --- 0.119 R3C8B.FCI to R3C8B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_451
ROUTE 1 0.000 R3C8B.FCO to R3C8C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_19
FCITOF0_DE --- 0.412 R3C8C.FCI to R3C8C.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_450
ROUTE 1 3.336 R3C8C.F0 to R10C7B.B1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2[24]
C1TOFCO_DE --- 0.627 R10C7B.B1 to R10C7B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_232
ROUTE 1 0.000 R10C7B.FCO to R10C7C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_4
FCITOFCO_D --- 0.119 R10C7C.FCI to R10C7C.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_231
ROUTE 1 0.000 R10C7C.FCO to R10C7D.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_6
FCITOFCO_D --- 0.119 R10C7D.FCI to R10C7D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_230
ROUTE 1 0.000 R10C7D.FCO to R10C8A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_8
FCITOF1_DE --- 0.453 R10C8A.FCI to R10C8A.F1 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_229
ROUTE 1 3.227 R10C8A.F1 to R7C5B.A1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21[30]
CTOF_DEL --- 0.374 R7C5B.A1 to R7C5B.F1 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_254
ROUTE 1 2.957 R7C5B.F1 to R2C8D.A1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_25[30]
C1TOFCO_DE --- 0.627 R2C8D.A1 to R2C8D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_288
ROUTE 1 0.000 R2C8D.FCO to R2C9A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_29_cry_14
FCITOF0_DE --- 0.412 R2C9A.FCI to R2C9A.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_287
ROUTE 1 1.216 R2C9A.F0 to R4C10A.A0 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_29[31]
CTOF_DEL --- 0.374 R4C10A.A0 to R4C10A.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292
ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 lm32_inst/platform_u/LM32/cpu/multiplier/product_2[31] (to ext_osc_clk_c)
--------
18.237 (26.5% logic, 73.5% route), 14 logic levels.
Clock Skew Details:
Source Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/SLICE_1655:
Name Fanout Delay (ns) Site Resource
ROUTE 999 5.360 3.PADDI to R7C12C.CLK ext_osc_clk_c
--------
5.360 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292:
Name Fanout Delay (ns) Site Resource
ROUTE 999 5.360 3.PADDI to R4C10A.CLK ext_osc_clk_c
--------
5.360 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 21.645ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm32_inst/platform_u/LM32/cpu/operand_0_x_2_rep1 (from ext_osc_clk_c +)
Destination: FF Data in lm32_inst/platform_u/LM32/cpu/multiplier/product[31] (to ext_osc_clk_c +)
Delay: 18.234ns (29.8% logic, 70.2% route), 19 logic levels.
Constraint Details:
18.234ns physical path delay lm32_inst/platform_u/LM32/cpu/SLICE_1669 to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292 meets
40.000ns delay constraint less
0.000ns skew and
0.121ns DIN_SET requirement (totaling 39.879ns) by 21.645ns
Physical Path Details:
Data path lm32_inst/platform_u/LM32/cpu/SLICE_1669 to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R12C2C.CLK to R12C2C.Q0 lm32_inst/platform_u/LM32/cpu/SLICE_1669 (from ext_osc_clk_c)
ROUTE 6 2.066 R12C2C.Q0 to R3C6B.A1 lm32_inst/platform_u/LM32/cpu/operand_0_x_2_rep1
C1TOFCO_DE --- 0.627 R3C6B.A1 to R3C6B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_459
ROUTE 1 0.000 R3C6B.FCO to R3C6C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_3
FCITOFCO_D --- 0.119 R3C6C.FCI to R3C6C.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_458
ROUTE 1 0.000 R3C6C.FCO to R3C6D.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_5
FCITOFCO_D --- 0.119 R3C6D.FCI to R3C6D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_457
ROUTE 1 0.000 R3C6D.FCO to R3C7A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_7
FCITOFCO_D --- 0.119 R3C7A.FCI to R3C7A.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_456
ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_9
FCITOFCO_D --- 0.119 R3C7B.FCI to R3C7B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_455
ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_11
FCITOFCO_D --- 0.119 R3C7C.FCI to R3C7C.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_454
ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_13
FCITOFCO_D --- 0.119 R3C7D.FCI to R3C7D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_453
ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_15
FCITOFCO_D --- 0.119 R3C8A.FCI to R3C8A.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_452
ROUTE 1 0.000 R3C8A.FCO to R3C8B.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_17
FCITOFCO_D --- 0.119 R3C8B.FCI to R3C8B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_451
ROUTE 1 0.000 R3C8B.FCO to R3C8C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_19
FCITOF0_DE --- 0.412 R3C8C.FCI to R3C8C.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_450
ROUTE 1 3.336 R3C8C.F0 to R10C7B.B1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2[24]
C1TOFCO_DE --- 0.627 R10C7B.B1 to R10C7B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_232
ROUTE 1 0.000 R10C7B.FCO to R10C7C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_4
FCITOFCO_D --- 0.119 R10C7C.FCI to R10C7C.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_231
ROUTE 1 0.000 R10C7C.FCO to R10C7D.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_6
FCITOFCO_D --- 0.119 R10C7D.FCI to R10C7D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_230
ROUTE 1 0.000 R10C7D.FCO to R10C8A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_8
FCITOF1_DE --- 0.453 R10C8A.FCI to R10C8A.F1 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_229
ROUTE 1 3.227 R10C8A.F1 to R7C5B.A1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21[30]
CTOF_DEL --- 0.374 R7C5B.A1 to R7C5B.F1 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_254
ROUTE 1 2.957 R7C5B.F1 to R2C8D.A1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_25[30]
C1TOFCO_DE --- 0.627 R2C8D.A1 to R2C8D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_288
ROUTE 1 0.000 R2C8D.FCO to R2C9A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_29_cry_14
FCITOF0_DE --- 0.412 R2C9A.FCI to R2C9A.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_287
ROUTE 1 1.216 R2C9A.F0 to R4C10A.A0 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_29[31]
CTOF_DEL --- 0.374 R4C10A.A0 to R4C10A.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292
ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 lm32_inst/platform_u/LM32/cpu/multiplier/product_2[31] (to ext_osc_clk_c)
--------
18.234 (29.8% logic, 70.2% route), 19 logic levels.
Clock Skew Details:
Source Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/SLICE_1669:
Name Fanout Delay (ns) Site Resource
ROUTE 999 5.360 3.PADDI to R12C2C.CLK ext_osc_clk_c
--------
5.360 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292:
Name Fanout Delay (ns) Site Resource
ROUTE 999 5.360 3.PADDI to R4C10A.CLK ext_osc_clk_c
--------
5.360 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 21.673ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm32_inst/platform_u/LM32/cpu/operand_0_x_fast[8] (from ext_osc_clk_c +)
Destination: FF Data in lm32_inst/platform_u/LM32/cpu/multiplier/product[31] (to ext_osc_clk_c +)
Delay: 18.206ns (27.9% logic, 72.1% route), 16 logic levels.
Constraint Details:
18.206ns physical path delay lm32_inst/platform_u/LM32/cpu/SLICE_1681 to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292 meets
40.000ns delay constraint less
0.000ns skew and
0.121ns DIN_SET requirement (totaling 39.879ns) by 21.673ns
Physical Path Details:
Data path lm32_inst/platform_u/LM32/cpu/SLICE_1681 to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R9C9C.CLK to R9C9C.Q0 lm32_inst/platform_u/LM32/cpu/SLICE_1681 (from ext_osc_clk_c)
ROUTE 6 2.395 R9C9C.Q0 to R3C7A.A1 lm32_inst/platform_u/LM32/cpu/operand_0_x_fast[8]
C1TOFCO_DE --- 0.627 R3C7A.A1 to R3C7A.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_456
ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_9
FCITOFCO_D --- 0.119 R3C7B.FCI to R3C7B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_455
ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_11
FCITOFCO_D --- 0.119 R3C7C.FCI to R3C7C.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_454
ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_13
FCITOFCO_D --- 0.119 R3C7D.FCI to R3C7D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_453
ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_15
FCITOFCO_D --- 0.119 R3C8A.FCI to R3C8A.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_452
ROUTE 1 0.000 R3C8A.FCO to R3C8B.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_17
FCITOFCO_D --- 0.119 R3C8B.FCI to R3C8B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_451
ROUTE 1 0.000 R3C8B.FCO to R3C8C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_19
FCITOF0_DE --- 0.412 R3C8C.FCI to R3C8C.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_450
ROUTE 1 3.336 R3C8C.F0 to R10C7B.B1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2[24]
C1TOFCO_DE --- 0.627 R10C7B.B1 to R10C7B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_232
ROUTE 1 0.000 R10C7B.FCO to R10C7C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_4
FCITOFCO_D --- 0.119 R10C7C.FCI to R10C7C.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_231
ROUTE 1 0.000 R10C7C.FCO to R10C7D.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_6
FCITOFCO_D --- 0.119 R10C7D.FCI to R10C7D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_230
ROUTE 1 0.000 R10C7D.FCO to R10C8A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_8
FCITOF1_DE --- 0.453 R10C8A.FCI to R10C8A.F1 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_229
ROUTE 1 3.227 R10C8A.F1 to R7C5B.A1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21[30]
CTOF_DEL --- 0.374 R7C5B.A1 to R7C5B.F1 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_254
ROUTE 1 2.957 R7C5B.F1 to R2C8D.A1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_25[30]
C1TOFCO_DE --- 0.627 R2C8D.A1 to R2C8D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_288
ROUTE 1 0.000 R2C8D.FCO to R2C9A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_29_cry_14
FCITOF0_DE --- 0.412 R2C9A.FCI to R2C9A.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_287
ROUTE 1 1.216 R2C9A.F0 to R4C10A.A0 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_29[31]
CTOF_DEL --- 0.374 R4C10A.A0 to R4C10A.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292
ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 lm32_inst/platform_u/LM32/cpu/multiplier/product_2[31] (to ext_osc_clk_c)
--------
18.206 (27.9% logic, 72.1% route), 16 logic levels.
Clock Skew Details:
Source Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/SLICE_1681:
Name Fanout Delay (ns) Site Resource
ROUTE 999 5.360 3.PADDI to R9C9C.CLK ext_osc_clk_c
--------
5.360 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292:
Name Fanout Delay (ns) Site Resource
ROUTE 999 5.360 3.PADDI to R4C10A.CLK ext_osc_clk_c
--------
5.360 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 21.720ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm32_inst/platform_u/LM32/cpu/instruction_unit/instruction_d[23] (from ext_osc_clk_c +)
Destination: FF Data in lm32_inst/platform_u/LM32/cpu/mc_arithmetic/b[16] (to ext_osc_clk_c +)
Delay: 18.191ns (23.4% logic, 76.6% route), 11 logic levels.
Constraint Details:
18.191ns physical path delay lm32_inst/platform_u/LM32/cpu/instruction_unit/SLICE_1800 to lm32_inst/platform_u/LM32/cpu/mc_arithmetic/SLICE_1583 meets
40.000ns delay constraint less
-0.032ns skew and
0.121ns DIN_SET requirement (totaling 39.911ns) by 21.720ns
Physical Path Details:
Data path lm32_inst/platform_u/LM32/cpu/instruction_unit/SLICE_1800 to lm32_inst/platform_u/LM32/cpu/mc_arithmetic/SLICE_1583:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R22C16A.CLK to R22C16A.Q0 lm32_inst/platform_u/LM32/cpu/instruction_unit/SLICE_1800 (from ext_osc_clk_c)
ROUTE 85 2.943 R22C16A.Q0 to R24C4B.B1 lm32_inst/platform_u/LM32/cpu/read_idx_0_d[2]
CTOF_DEL --- 0.374 R24C4B.B1 to R24C4B.F1 lm32_inst/platform_u/LM32/cpu/decoder/SLICE_2420
ROUTE 4 0.716 R24C4B.F1 to R24C4A.A0 lm32_inst/platform_u/LM32/cpu/N_175
CTOF_DEL --- 0.374 R24C4A.A0 to R24C4A.F0 lm32_inst/platform_u/LM32/cpu/SLICE_2423
ROUTE 1 0.441 R24C4A.F0 to R24C4A.D1 lm32_inst/platform_u/LM32/cpu/registersria_21
CTOF_DEL --- 0.374 R24C4A.D1 to R24C4A.F1 lm32_inst/platform_u/LM32/cpu/SLICE_2423
ROUTE 1 1.509 R24C4A.F1 to R24C7A.C1 lm32_inst/platform_u/LM32/cpu/registersror_6
CTOF_DEL --- 0.374 R24C7A.C1 to R24C7A.F1 lm32_inst/platform_u/LM32/cpu/SLICE_2409
ROUTE 1 1.529 R24C7A.F1 to R23C7D.A0 lm32_inst/platform_u/LM32/cpu/registersror_21
CTOF_DEL --- 0.374 R23C7D.A0 to R23C7D.F0 lm32_inst/platform_u/LM32/cpu/SLICE_2453
ROUTE 32 1.429 R23C7D.F0 to R18C9C.A0 lm32_inst/platform_u/LM32/cpu/registersror
CTOOFX_DEL --- 0.550 R18C9C.A0 to R18C9C.OFX0 lm32_inst/platform_u/LM32/cpu/bypass_data_0_m1[16]/SLICE_2106
ROUTE 1 0.826 R18C9C.OFX0 to R15C11B.D0 lm32_inst/platform_u/LM32/cpu/bypass_data_0_m1[16]
CTOF_DEL --- 0.374 R15C11B.D0 to R15C11B.F0 lm32_inst/platform_u/LM32/cpu/SLICE_2833
ROUTE 2 2.288 R15C11B.F0 to R7C14A.B0 lm32_inst/platform_u/LM32/cpu/bypass_data_0[16]
CTOF_DEL --- 0.374 R7C14A.B0 to R7C14A.F0 lm32_inst/platform_u/LM32/cpu/SLICE_1657
ROUTE 3 1.323 R7C14A.F0 to R8C12B.A0 lm32_inst/platform_u/LM32/cpu/d_result_0[16]
CTOF_DEL --- 0.374 R8C12B.A0 to R8C12B.F0 lm32_inst/platform_u/LM32/cpu/mc_arithmetic/SLICE_2750
ROUTE 1 0.935 R8C12B.F0 to R7C13B.A0 lm32_inst/platform_u/LM32/cpu/mc_arithmetic/N_525
CTOF_DEL --- 0.374 R7C13B.A0 to R7C13B.F0 lm32_inst/platform_u/LM32/cpu/mc_arithmetic/SLICE_1583
ROUTE 1 0.000 R7C13B.F0 to R7C13B.DI0 lm32_inst/platform_u/LM32/cpu/mc_arithmetic/b_RNO[16] (to ext_osc_clk_c)
--------
18.191 (23.4% logic, 76.6% route), 11 logic levels.
Clock Skew Details:
Source Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/instruction_unit/SLICE_1800:
Name Fanout Delay (ns) Site Resource
ROUTE 999 5.328 3.PADDI to R22C16A.CLK ext_osc_clk_c
--------
5.328 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/mc_arithmetic/SLICE_1583:
Name Fanout Delay (ns) Site Resource
ROUTE 999 5.360 3.PADDI to R7C13B.CLK ext_osc_clk_c
--------
5.360 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 21.731ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm32_inst/platform_u/LM32/cpu/operand_0_x_fast[6] (from ext_osc_clk_c +)
Destination: FF Data in lm32_inst/platform_u/LM32/cpu/multiplier/product[31] (to ext_osc_clk_c +)
Delay: 18.148ns (28.6% logic, 71.4% route), 17 logic levels.
Constraint Details:
18.148ns physical path delay lm32_inst/platform_u/LM32/cpu/SLICE_1680 to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292 meets
40.000ns delay constraint less
0.000ns skew and
0.121ns DIN_SET requirement (totaling 39.879ns) by 21.731ns
Physical Path Details:
Data path lm32_inst/platform_u/LM32/cpu/SLICE_1680 to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R7C9D.CLK to R7C9D.Q0 lm32_inst/platform_u/LM32/cpu/SLICE_1680 (from ext_osc_clk_c)
ROUTE 6 2.218 R7C9D.Q0 to R3C6D.A1 lm32_inst/platform_u/LM32/cpu/operand_0_x_fast[6]
C1TOFCO_DE --- 0.627 R3C6D.A1 to R3C6D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_457
ROUTE 1 0.000 R3C6D.FCO to R3C7A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_7
FCITOFCO_D --- 0.119 R3C7A.FCI to R3C7A.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_456
ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_9
FCITOFCO_D --- 0.119 R3C7B.FCI to R3C7B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_455
ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_11
FCITOFCO_D --- 0.119 R3C7C.FCI to R3C7C.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_454
ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_13
FCITOFCO_D --- 0.119 R3C7D.FCI to R3C7D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_453
ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_15
FCITOFCO_D --- 0.119 R3C8A.FCI to R3C8A.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_452
ROUTE 1 0.000 R3C8A.FCO to R3C8B.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_17
FCITOFCO_D --- 0.119 R3C8B.FCI to R3C8B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_451
ROUTE 1 0.000 R3C8B.FCO to R3C8C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_19
FCITOF0_DE --- 0.412 R3C8C.FCI to R3C8C.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_450
ROUTE 1 3.336 R3C8C.F0 to R10C7B.B1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2[24]
C1TOFCO_DE --- 0.627 R10C7B.B1 to R10C7B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_232
ROUTE 1 0.000 R10C7B.FCO to R10C7C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_4
FCITOFCO_D --- 0.119 R10C7C.FCI to R10C7C.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_231
ROUTE 1 0.000 R10C7C.FCO to R10C7D.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_6
FCITOFCO_D --- 0.119 R10C7D.FCI to R10C7D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_230
ROUTE 1 0.000 R10C7D.FCO to R10C8A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_8
FCITOF1_DE --- 0.453 R10C8A.FCI to R10C8A.F1 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_229
ROUTE 1 3.227 R10C8A.F1 to R7C5B.A1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21[30]
CTOF_DEL --- 0.374 R7C5B.A1 to R7C5B.F1 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_254
ROUTE 1 2.957 R7C5B.F1 to R2C8D.A1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_25[30]
C1TOFCO_DE --- 0.627 R2C8D.A1 to R2C8D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_288
ROUTE 1 0.000 R2C8D.FCO to R2C9A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_29_cry_14
FCITOF0_DE --- 0.412 R2C9A.FCI to R2C9A.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_287
ROUTE 1 1.216 R2C9A.F0 to R4C10A.A0 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_29[31]
CTOF_DEL --- 0.374 R4C10A.A0 to R4C10A.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292
ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 lm32_inst/platform_u/LM32/cpu/multiplier/product_2[31] (to ext_osc_clk_c)
--------
18.148 (28.6% logic, 71.4% route), 17 logic levels.
Clock Skew Details:
Source Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/SLICE_1680:
Name Fanout Delay (ns) Site Resource
ROUTE 999 5.360 3.PADDI to R7C9D.CLK ext_osc_clk_c
--------
5.360 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292:
Name Fanout Delay (ns) Site Resource
ROUTE 999 5.360 3.PADDI to R4C10A.CLK ext_osc_clk_c
--------
5.360 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 21.805ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm32_inst/platform_u/LM32/cpu/operand_0_x[12] (from ext_osc_clk_c +)
Destination: FF Data in lm32_inst/platform_u/LM32/cpu/multiplier/product[31] (to ext_osc_clk_c +)
Delay: 18.074ns (27.3% logic, 72.7% route), 14 logic levels.
Constraint Details:
18.074ns physical path delay lm32_inst/platform_u/LM32/cpu/SLICE_1655 to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292 meets
40.000ns delay constraint less
0.000ns skew and
0.121ns DIN_SET requirement (totaling 39.879ns) by 21.805ns
Physical Path Details:
Data path lm32_inst/platform_u/LM32/cpu/SLICE_1655 to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R7C12C.CLK to R7C12C.Q0 lm32_inst/platform_u/LM32/cpu/SLICE_1655 (from ext_osc_clk_c)
ROUTE 24 2.407 R7C12C.Q0 to R3C7C.D0 lm32_inst/platform_u/LM32/cpu/operand_0_x[12]
C0TOFCO_DE --- 0.721 R3C7C.D0 to R3C7C.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_454
ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_13
FCITOFCO_D --- 0.119 R3C7D.FCI to R3C7D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_453
ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_15
FCITOFCO_D --- 0.119 R3C8A.FCI to R3C8A.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_452
ROUTE 1 0.000 R3C8A.FCO to R3C8B.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_17
FCITOFCO_D --- 0.119 R3C8B.FCI to R3C8B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_451
ROUTE 1 0.000 R3C8B.FCO to R3C8C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_19
FCITOF0_DE --- 0.412 R3C8C.FCI to R3C8C.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_450
ROUTE 1 3.336 R3C8C.F0 to R10C7B.B1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2[24]
C1TOFCO_DE --- 0.627 R10C7B.B1 to R10C7B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_232
ROUTE 1 0.000 R10C7B.FCO to R10C7C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_4
FCITOFCO_D --- 0.119 R10C7C.FCI to R10C7C.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_231
ROUTE 1 0.000 R10C7C.FCO to R10C7D.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_6
FCITOFCO_D --- 0.119 R10C7D.FCI to R10C7D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_230
ROUTE 1 0.000 R10C7D.FCO to R10C8A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_8
FCITOF1_DE --- 0.453 R10C8A.FCI to R10C8A.F1 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_229
ROUTE 1 3.227 R10C8A.F1 to R7C5B.A1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21[30]
CTOF_DEL --- 0.374 R7C5B.A1 to R7C5B.F1 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_254
ROUTE 1 2.957 R7C5B.F1 to R2C8D.A1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_25[30]
C1TOFCO_DE --- 0.627 R2C8D.A1 to R2C8D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_288
ROUTE 1 0.000 R2C8D.FCO to R2C9A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_29_cry_14
FCITOF0_DE --- 0.412 R2C9A.FCI to R2C9A.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_287
ROUTE 1 1.216 R2C9A.F0 to R4C10A.A0 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_29[31]
CTOF_DEL --- 0.374 R4C10A.A0 to R4C10A.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292
ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 lm32_inst/platform_u/LM32/cpu/multiplier/product_2[31] (to ext_osc_clk_c)
--------
18.074 (27.3% logic, 72.7% route), 14 logic levels.
Clock Skew Details:
Source Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/SLICE_1655:
Name Fanout Delay (ns) Site Resource
ROUTE 999 5.360 3.PADDI to R7C12C.CLK ext_osc_clk_c
--------
5.360 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292:
Name Fanout Delay (ns) Site Resource
ROUTE 999 5.360 3.PADDI to R4C10A.CLK ext_osc_clk_c
--------
5.360 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 21.861ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm32_inst/platform_u/LM32/cpu/instruction_unit/instruction_d[23] (from ext_osc_clk_c +)
Destination: FF Data in lm32_inst/platform_u/LM32/cpu/mc_arithmetic/b[19] (to ext_osc_clk_c +)
Delay: 18.050ns (23.6% logic, 76.4% route), 11 logic levels.
Constraint Details:
18.050ns physical path delay lm32_inst/platform_u/LM32/cpu/instruction_unit/SLICE_1800 to lm32_inst/platform_u/LM32/cpu/mc_arithmetic/SLICE_1584 meets
40.000ns delay constraint less
-0.032ns skew and
0.121ns DIN_SET requirement (totaling 39.911ns) by 21.861ns
Physical Path Details:
Data path lm32_inst/platform_u/LM32/cpu/instruction_unit/SLICE_1800 to lm32_inst/platform_u/LM32/cpu/mc_arithmetic/SLICE_1584:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R22C16A.CLK to R22C16A.Q0 lm32_inst/platform_u/LM32/cpu/instruction_unit/SLICE_1800 (from ext_osc_clk_c)
ROUTE 85 2.943 R22C16A.Q0 to R24C4B.B1 lm32_inst/platform_u/LM32/cpu/read_idx_0_d[2]
CTOF_DEL --- 0.374 R24C4B.B1 to R24C4B.F1 lm32_inst/platform_u/LM32/cpu/decoder/SLICE_2420
ROUTE 4 0.716 R24C4B.F1 to R24C4A.A0 lm32_inst/platform_u/LM32/cpu/N_175
CTOF_DEL --- 0.374 R24C4A.A0 to R24C4A.F0 lm32_inst/platform_u/LM32/cpu/SLICE_2423
ROUTE 1 0.441 R24C4A.F0 to R24C4A.D1 lm32_inst/platform_u/LM32/cpu/registersria_21
CTOF_DEL --- 0.374 R24C4A.D1 to R24C4A.F1 lm32_inst/platform_u/LM32/cpu/SLICE_2423
ROUTE 1 1.509 R24C4A.F1 to R24C7A.C1 lm32_inst/platform_u/LM32/cpu/registersror_6
CTOF_DEL --- 0.374 R24C7A.C1 to R24C7A.F1 lm32_inst/platform_u/LM32/cpu/SLICE_2409
ROUTE 1 1.529 R24C7A.F1 to R23C7D.A0 lm32_inst/platform_u/LM32/cpu/registersror_21
CTOF_DEL --- 0.374 R23C7D.A0 to R23C7D.F0 lm32_inst/platform_u/LM32/cpu/SLICE_2453
ROUTE 32 1.209 R23C7D.F0 to R19C13B.D0 lm32_inst/platform_u/LM32/cpu/registersror
CTOOFX_DEL --- 0.550 R19C13B.D0 to R19C13B.OFX0 lm32_inst/platform_u/LM32/cpu/bypass_data_0_m1[19]/SLICE_2127
ROUTE 1 1.176 R19C13B.OFX0 to R14C13C.A0 lm32_inst/platform_u/LM32/cpu/bypass_data_0_m1[19]
CTOF_DEL --- 0.374 R14C13C.A0 to R14C13C.F0 lm32_inst/platform_u/LM32/cpu/SLICE_2834
ROUTE 2 2.077 R14C13C.F0 to R7C13A.B1 lm32_inst/platform_u/LM32/cpu/bypass_data_0[19]
CTOF_DEL --- 0.374 R7C13A.B1 to R7C13A.F1 lm32_inst/platform_u/LM32/cpu/SLICE_1658
ROUTE 3 0.753 R7C13A.F1 to R7C11A.D0 lm32_inst/platform_u/LM32/cpu/d_result_0[19]
CTOF_DEL --- 0.374 R7C11A.D0 to R7C11A.F0 lm32_inst/platform_u/LM32/cpu/mc_arithmetic/SLICE_2746
ROUTE 1 1.445 R7C11A.F0 to R6C12A.B1 lm32_inst/platform_u/LM32/cpu/mc_arithmetic/N_576
CTOF_DEL --- 0.374 R6C12A.B1 to R6C12A.F1 lm32_inst/platform_u/LM32/cpu/mc_arithmetic/SLICE_1584
ROUTE 1 0.000 R6C12A.F1 to R6C12A.DI1 lm32_inst/platform_u/LM32/cpu/mc_arithmetic/b_RNO[19] (to ext_osc_clk_c)
--------
18.050 (23.6% logic, 76.4% route), 11 logic levels.
Clock Skew Details:
Source Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/instruction_unit/SLICE_1800:
Name Fanout Delay (ns) Site Resource
ROUTE 999 5.328 3.PADDI to R22C16A.CLK ext_osc_clk_c
--------
5.328 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/mc_arithmetic/SLICE_1584:
Name Fanout Delay (ns) Site Resource
ROUTE 999 5.360 3.PADDI to R6C12A.CLK ext_osc_clk_c
--------
5.360 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 21.861ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm32_inst/platform_u/LM32/cpu/operand_0_x_10_rep1 (from ext_osc_clk_c +)
Destination: FF Data in lm32_inst/platform_u/LM32/cpu/multiplier/product[31] (to ext_osc_clk_c +)
Delay: 18.018ns (27.5% logic, 72.5% route), 15 logic levels.
Constraint Details:
18.018ns physical path delay lm32_inst/platform_u/LM32/cpu/SLICE_1666 to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292 meets
40.000ns delay constraint less
0.000ns skew and
0.121ns DIN_SET requirement (totaling 39.879ns) by 21.861ns
Physical Path Details:
Data path lm32_inst/platform_u/LM32/cpu/SLICE_1666 to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R6C10A.CLK to R6C10A.Q0 lm32_inst/platform_u/LM32/cpu/SLICE_1666 (from ext_osc_clk_c)
ROUTE 8 2.326 R6C10A.Q0 to R3C7B.A1 lm32_inst/platform_u/LM32/cpu/operand_0_x_10_rep1
C1TOFCO_DE --- 0.627 R3C7B.A1 to R3C7B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_455
ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_11
FCITOFCO_D --- 0.119 R3C7C.FCI to R3C7C.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_454
ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_13
FCITOFCO_D --- 0.119 R3C7D.FCI to R3C7D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_453
ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_15
FCITOFCO_D --- 0.119 R3C8A.FCI to R3C8A.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_452
ROUTE 1 0.000 R3C8A.FCO to R3C8B.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_17
FCITOFCO_D --- 0.119 R3C8B.FCI to R3C8B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_451
ROUTE 1 0.000 R3C8B.FCO to R3C8C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_19
FCITOF0_DE --- 0.412 R3C8C.FCI to R3C8C.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_450
ROUTE 1 3.336 R3C8C.F0 to R10C7B.B1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2[24]
C1TOFCO_DE --- 0.627 R10C7B.B1 to R10C7B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_232
ROUTE 1 0.000 R10C7B.FCO to R10C7C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_4
FCITOFCO_D --- 0.119 R10C7C.FCI to R10C7C.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_231
ROUTE 1 0.000 R10C7C.FCO to R10C7D.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_6
FCITOFCO_D --- 0.119 R10C7D.FCI to R10C7D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_230
ROUTE 1 0.000 R10C7D.FCO to R10C8A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_8
FCITOF1_DE --- 0.453 R10C8A.FCI to R10C8A.F1 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_229
ROUTE 1 3.227 R10C8A.F1 to R7C5B.A1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21[30]
CTOF_DEL --- 0.374 R7C5B.A1 to R7C5B.F1 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_254
ROUTE 1 2.957 R7C5B.F1 to R2C8D.A1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_25[30]
C1TOFCO_DE --- 0.627 R2C8D.A1 to R2C8D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_288
ROUTE 1 0.000 R2C8D.FCO to R2C9A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_29_cry_14
FCITOF0_DE --- 0.412 R2C9A.FCI to R2C9A.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_287
ROUTE 1 1.216 R2C9A.F0 to R4C10A.A0 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_29[31]
CTOF_DEL --- 0.374 R4C10A.A0 to R4C10A.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292
ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 lm32_inst/platform_u/LM32/cpu/multiplier/product_2[31] (to ext_osc_clk_c)
--------
18.018 (27.5% logic, 72.5% route), 15 logic levels.
Clock Skew Details:
Source Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/SLICE_1666:
Name Fanout Delay (ns) Site Resource
ROUTE 999 5.360 3.PADDI to R6C10A.CLK ext_osc_clk_c
--------
5.360 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292:
Name Fanout Delay (ns) Site Resource
ROUTE 999 5.360 3.PADDI to R4C10A.CLK ext_osc_clk_c
--------
5.360 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 21.888ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm32_inst/platform_u/LM32/cpu/operand_0_x_1_rep1 (from ext_osc_clk_c +)
Destination: FF Data in lm32_inst/platform_u/LM32/cpu/multiplier/product[31] (to ext_osc_clk_c +)
Delay: 17.991ns (30.7% logic, 69.3% route), 19 logic levels.
Constraint Details:
17.991ns physical path delay lm32_inst/platform_u/LM32/cpu/SLICE_1668 to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292 meets
40.000ns delay constraint less
0.000ns skew and
0.121ns DIN_SET requirement (totaling 39.879ns) by 21.888ns
Physical Path Details:
Data path lm32_inst/platform_u/LM32/cpu/SLICE_1668 to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.336 R11C9C.CLK to R11C9C.Q0 lm32_inst/platform_u/LM32/cpu/SLICE_1668 (from ext_osc_clk_c)
ROUTE 7 1.729 R11C9C.Q0 to R3C6B.A0 lm32_inst/platform_u/LM32/cpu/operand_0_x_1_rep1
C0TOFCO_DE --- 0.721 R3C6B.A0 to R3C6B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_459
ROUTE 1 0.000 R3C6B.FCO to R3C6C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_3
FCITOFCO_D --- 0.119 R3C6C.FCI to R3C6C.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_458
ROUTE 1 0.000 R3C6C.FCO to R3C6D.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_5
FCITOFCO_D --- 0.119 R3C6D.FCI to R3C6D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_457
ROUTE 1 0.000 R3C6D.FCO to R3C7A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_7
FCITOFCO_D --- 0.119 R3C7A.FCI to R3C7A.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_456
ROUTE 1 0.000 R3C7A.FCO to R3C7B.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_9
FCITOFCO_D --- 0.119 R3C7B.FCI to R3C7B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_455
ROUTE 1 0.000 R3C7B.FCO to R3C7C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_11
FCITOFCO_D --- 0.119 R3C7C.FCI to R3C7C.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_454
ROUTE 1 0.000 R3C7C.FCO to R3C7D.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_13
FCITOFCO_D --- 0.119 R3C7D.FCI to R3C7D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_453
ROUTE 1 0.000 R3C7D.FCO to R3C8A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_15
FCITOFCO_D --- 0.119 R3C8A.FCI to R3C8A.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_452
ROUTE 1 0.000 R3C8A.FCO to R3C8B.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_17
FCITOFCO_D --- 0.119 R3C8B.FCI to R3C8B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_451
ROUTE 1 0.000 R3C8B.FCO to R3C8C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2_cry_19
FCITOF0_DE --- 0.412 R3C8C.FCI to R3C8C.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_450
ROUTE 1 3.336 R3C8C.F0 to R10C7B.B1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_2[24]
C1TOFCO_DE --- 0.627 R10C7B.B1 to R10C7B.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_232
ROUTE 1 0.000 R10C7B.FCO to R10C7C.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_4
FCITOFCO_D --- 0.119 R10C7C.FCI to R10C7C.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_231
ROUTE 1 0.000 R10C7C.FCO to R10C7D.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_6
FCITOFCO_D --- 0.119 R10C7D.FCI to R10C7D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_230
ROUTE 1 0.000 R10C7D.FCO to R10C8A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21_cry_8
FCITOF1_DE --- 0.453 R10C8A.FCI to R10C8A.F1 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_229
ROUTE 1 3.227 R10C8A.F1 to R7C5B.A1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_21[30]
CTOF_DEL --- 0.374 R7C5B.A1 to R7C5B.F1 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_254
ROUTE 1 2.957 R7C5B.F1 to R2C8D.A1 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_25[30]
C1TOFCO_DE --- 0.627 R2C8D.A1 to R2C8D.FCO lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_288
ROUTE 1 0.000 R2C8D.FCO to R2C9A.FCI lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_29_cry_14
FCITOF0_DE --- 0.412 R2C9A.FCI to R2C9A.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_287
ROUTE 1 1.216 R2C9A.F0 to R4C10A.A0 lm32_inst/platform_u/LM32/cpu/multiplier/product_2_madd_29[31]
CTOF_DEL --- 0.374 R4C10A.A0 to R4C10A.F0 lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292
ROUTE 1 0.000 R4C10A.F0 to R4C10A.DI0 lm32_inst/platform_u/LM32/cpu/multiplier/product_2[31] (to ext_osc_clk_c)
--------
17.991 (30.7% logic, 69.3% route), 19 logic levels.
Clock Skew Details:
Source Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/SLICE_1668:
Name Fanout Delay (ns) Site Resource
ROUTE 999 5.360 3.PADDI to R11C9C.CLK ext_osc_clk_c
--------
5.360 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/multiplier/SLICE_292:
Name Fanout Delay (ns) Site Resource
ROUTE 999 5.360 3.PADDI to R4C10A.CLK ext_osc_clk_c
--------
5.360 (0.0% logic, 100.0% route), 0 logic levels.
Report: 54.460MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET | | |
"controller_marco.sys_clk_sig_c" | | |
125.000000 MHz ; | 125.000 MHz| 150.105 MHz| 5
| | |
FREQUENCY NET | | |
"controller_marco/osch_clk_sig_c" | | |
10.230000 MHz ; | 10.230 MHz| 171.145 MHz| 10
| | |
FREQUENCY NET "tft_clk_c_c" 35.714286 | | |
MHz ; | 35.714 MHz| 74.019 MHz| 13
| | |
FREQUENCY PORT "ext_osc_clk" 25.000000 | | |
MHz ; | 25.000 MHz| 150.150 MHz| 0
| | |
FREQUENCY NET "ext_osc_clk_c" 25.000000 | | |
MHz ; | 25.000 MHz| 54.460 MHz| 17
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
No clock domain analysis is done. To analyze clock domains, please remove the BLOCK INTERCLOCKDOMAIN PATHS preference.
Timing summary (Setup):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 16647227 paths, 6 nets, and 20997 connections (98.3% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond Version 2.2.0.101
Fri Aug 02 10:00:26 2013
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 6 -sphld m -o tftsurfer_tftsurfer.twr tftsurfer_tftsurfer.ncd tftsurfer_tftsurfer.prf
Design file: tftsurfer_tftsurfer.ncd
Preference file: tftsurfer_tftsurfer.prf
Device,speed: LCMXO2-7000HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "controller_marco.sys_clk_sig_c" 125.000000 MHz (0 errors) 2888 items scored, 0 timing errors detected.
FREQUENCY NET "controller_marco/osch_clk_sig_c" 10.230000 MHz (0 errors) 310 items scored, 0 timing errors detected.
FREQUENCY NET "tft_clk_c_c" 35.714286 MHz (0 errors) 3364 items scored, 0 timing errors detected.
FREQUENCY PORT "ext_osc_clk" 25.000000 MHz (0 errors) 0 items scored, 0 timing errors detected.
FREQUENCY NET "ext_osc_clk_c" 25.000000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
BLOCK INTERCLOCKDOMAIN PATHS
--------------------------------------------------------------------------------
Derating parameters
-------------------
Voltage: 1.180 V
================================================================================
Preference: FREQUENCY NET "controller_marco.sys_clk_sig_c" 125.000000 MHz ;
2888 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.155ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/MONSTER_MANAGER_INST/wb_data[14] (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco/inst_wb_data_fifo/fifo_pfu_0_0/RAM1 (to controller_marco.sys_clk_sig_c +)
FF controller_marco/inst_wb_data_fifo/fifo_pfu_0_0/RAM1
Delay: 0.302ns (49.7% logic, 50.3% route), 2 logic levels.
Constraint Details:
0.302ns physical path delay controller_marco/MONSTER_MANAGER_INST/SLICE_1312 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_0.11 meets
0.147ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.155ns
Physical Path Details:
Data path controller_marco/MONSTER_MANAGER_INST/SLICE_1312 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_0.11:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R18C37D.CLK to R18C37D.Q0 controller_marco/MONSTER_MANAGER_INST/SLICE_1312 (from controller_marco.sys_clk_sig_c)
ROUTE 1 0.152 R18C37D.Q0 to R18C37C.C1 controller_marco/wb_data_sig[14]
ZERO_DEL --- 0.000 R18C37C.C1 to R18C37C.WDO2 controller_marco/inst_wb_data_fifo/fifo_pfu_0_0.12
ROUTE 1 0.000 R18C37C.WDO2 to R18C37B.WD0 controller_marco/inst_wb_data_fifo/fifo_pfu_0_0/WD2_INT (to controller_marco.sys_clk_sig_c)
--------
0.302 (49.7% logic, 50.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/MONSTER_MANAGER_INST/SLICE_1312:
Name Fanout Delay (ns) Site Resource
ROUTE 382 0.783 LPLL.CLKOP to R18C37D.CLK controller_marco.sys_clk_sig_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_0.11:
Name Fanout Delay (ns) Site Resource
ROUTE 382 0.783 LPLL.CLKOP to R18C37B.WCK controller_marco.sys_clk_sig_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.157ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/MONSTER_MANAGER_INST/wb_data[2] (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco/inst_wb_data_fifo/fifo_pfu_0_3/RAM1 (to controller_marco.sys_clk_sig_c +)
FF controller_marco/inst_wb_data_fifo/fifo_pfu_0_3/RAM1
Delay: 0.304ns (49.3% logic, 50.7% route), 2 logic levels.
Constraint Details:
0.304ns physical path delay controller_marco/MONSTER_MANAGER_INST/SLICE_1306 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_3.18 meets
0.147ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.157ns
Physical Path Details:
Data path controller_marco/MONSTER_MANAGER_INST/SLICE_1306 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_3.18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R21C36B.CLK to R21C36B.Q0 controller_marco/MONSTER_MANAGER_INST/SLICE_1306 (from controller_marco.sys_clk_sig_c)
ROUTE 1 0.154 R21C36B.Q0 to R21C35C.C1 controller_marco/wb_data_sig[2]
ZERO_DEL --- 0.000 R21C35C.C1 to R21C35C.WDO2 controller_marco/inst_wb_data_fifo/fifo_pfu_0_3.17
ROUTE 1 0.000 R21C35C.WDO2 to R21C35B.WD0 controller_marco/inst_wb_data_fifo/fifo_pfu_0_3/WD2_INT (to controller_marco.sys_clk_sig_c)
--------
0.304 (49.3% logic, 50.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/MONSTER_MANAGER_INST/SLICE_1306:
Name Fanout Delay (ns) Site Resource
ROUTE 382 0.762 LPLL.CLKOP to R21C36B.CLK controller_marco.sys_clk_sig_c
--------
0.762 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_3.18:
Name Fanout Delay (ns) Site Resource
ROUTE 382 0.762 LPLL.CLKOP to R21C35B.WCK controller_marco.sys_clk_sig_c
--------
0.762 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.158ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/MONSTER_MANAGER_INST/wb_data[6] (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco/inst_wb_data_fifo/fifo_pfu_0_2/RAM1 (to controller_marco.sys_clk_sig_c +)
FF controller_marco/inst_wb_data_fifo/fifo_pfu_0_2/RAM1
Delay: 0.305ns (49.2% logic, 50.8% route), 2 logic levels.
Constraint Details:
0.305ns physical path delay controller_marco/MONSTER_MANAGER_INST/SLICE_1308 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_2.15 meets
0.147ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.158ns
Physical Path Details:
Data path controller_marco/MONSTER_MANAGER_INST/SLICE_1308 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_2.15:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R22C37A.CLK to R22C37A.Q0 controller_marco/MONSTER_MANAGER_INST/SLICE_1308 (from controller_marco.sys_clk_sig_c)
ROUTE 1 0.155 R22C37A.Q0 to R22C36C.C1 controller_marco/wb_data_sig[6]
ZERO_DEL --- 0.000 R22C36C.C1 to R22C36C.WDO2 controller_marco/inst_wb_data_fifo/fifo_pfu_0_2.16
ROUTE 1 0.000 R22C36C.WDO2 to R22C36B.WD0 controller_marco/inst_wb_data_fifo/fifo_pfu_0_2/WD2_INT (to controller_marco.sys_clk_sig_c)
--------
0.305 (49.2% logic, 50.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/MONSTER_MANAGER_INST/SLICE_1308:
Name Fanout Delay (ns) Site Resource
ROUTE 382 0.762 LPLL.CLKOP to R22C37A.CLK controller_marco.sys_clk_sig_c
--------
0.762 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_2.15:
Name Fanout Delay (ns) Site Resource
ROUTE 382 0.762 LPLL.CLKOP to R22C36B.WCK controller_marco.sys_clk_sig_c
--------
0.762 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.238ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/MONSTER_MANAGER_INST/tft_sdram_red[1] (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_0/RAM0 (to controller_marco.sys_clk_sig_c +)
FF controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_0/RAM0
Delay: 0.385ns (39.0% logic, 61.0% route), 2 logic levels.
Constraint Details:
0.385ns physical path delay controller_marco/MONSTER_MANAGER_INST/SLICE_1297 to controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_0.58 meets
0.147ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.238ns
Physical Path Details:
Data path controller_marco/MONSTER_MANAGER_INST/SLICE_1297 to controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_0.58:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R11C39D.CLK to R11C39D.Q1 controller_marco/MONSTER_MANAGER_INST/SLICE_1297 (from controller_marco.sys_clk_sig_c)
ROUTE 1 0.235 R11C39D.Q1 to R11C39C.A1 controller_marco/tft_sdram_red_in_sig[1]
ZERO_DEL --- 0.000 R11C39C.A1 to R11C39C.WDO0 controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_0.57
ROUTE 1 0.000 R11C39C.WDO0 to R11C39A.WD0 controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_0/WD0_INT (to controller_marco.sys_clk_sig_c)
--------
0.385 (39.0% logic, 61.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/MONSTER_MANAGER_INST/SLICE_1297:
Name Fanout Delay (ns) Site Resource
ROUTE 382 0.783 LPLL.CLKOP to R11C39D.CLK controller_marco.sys_clk_sig_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_0.58:
Name Fanout Delay (ns) Site Resource
ROUTE 382 0.783 LPLL.CLKOP to R11C39A.WCK controller_marco.sys_clk_sig_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.239ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/MONSTER_MANAGER_INST/wb_data[12] (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco/inst_wb_data_fifo/fifo_pfu_0_0/RAM0 (to controller_marco.sys_clk_sig_c +)
FF controller_marco/inst_wb_data_fifo/fifo_pfu_0_0/RAM0
Delay: 0.386ns (38.9% logic, 61.1% route), 2 logic levels.
Constraint Details:
0.386ns physical path delay controller_marco/MONSTER_MANAGER_INST/SLICE_1311 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_0 meets
0.147ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.239ns
Physical Path Details:
Data path controller_marco/MONSTER_MANAGER_INST/SLICE_1311 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R17C37C.CLK to R17C37C.Q0 controller_marco/MONSTER_MANAGER_INST/SLICE_1311 (from controller_marco.sys_clk_sig_c)
ROUTE 1 0.236 R17C37C.Q0 to R18C37C.A1 controller_marco/wb_data_sig[12]
ZERO_DEL --- 0.000 R18C37C.A1 to R18C37C.WDO0 controller_marco/inst_wb_data_fifo/fifo_pfu_0_0.12
ROUTE 1 0.000 R18C37C.WDO0 to R18C37A.WD0 controller_marco/inst_wb_data_fifo/fifo_pfu_0_0/WD0_INT (to controller_marco.sys_clk_sig_c)
--------
0.386 (38.9% logic, 61.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/MONSTER_MANAGER_INST/SLICE_1311:
Name Fanout Delay (ns) Site Resource
ROUTE 382 0.783 LPLL.CLKOP to R17C37C.CLK controller_marco.sys_clk_sig_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_0:
Name Fanout Delay (ns) Site Resource
ROUTE 382 0.783 LPLL.CLKOP to R18C37A.WCK controller_marco.sys_clk_sig_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.247ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/MONSTER_MANAGER_INST/wb_data[11] (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco/inst_wb_data_fifo/fifo_pfu_0_1/RAM1 (to controller_marco.sys_clk_sig_c +)
FF controller_marco/inst_wb_data_fifo/fifo_pfu_0_1/RAM1
Delay: 0.394ns (38.1% logic, 61.9% route), 2 logic levels.
Constraint Details:
0.394ns physical path delay controller_marco/MONSTER_MANAGER_INST/SLICE_1310 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_1 meets
0.147ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.247ns
Physical Path Details:
Data path controller_marco/MONSTER_MANAGER_INST/SLICE_1310 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R18C38C.CLK to R18C38C.Q1 controller_marco/MONSTER_MANAGER_INST/SLICE_1310 (from controller_marco.sys_clk_sig_c)
ROUTE 1 0.244 R18C38C.Q1 to R19C37C.D1 controller_marco/wb_data_sig[11]
ZERO_DEL --- 0.000 R19C37C.D1 to R19C37C.WDO3 controller_marco/inst_wb_data_fifo/fifo_pfu_0_1.13
ROUTE 1 0.000 R19C37C.WDO3 to R19C37B.WD1 controller_marco/inst_wb_data_fifo/fifo_pfu_0_1/WD3_INT (to controller_marco.sys_clk_sig_c)
--------
0.394 (38.1% logic, 61.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/MONSTER_MANAGER_INST/SLICE_1310:
Name Fanout Delay (ns) Site Resource
ROUTE 382 0.783 LPLL.CLKOP to R18C38C.CLK controller_marco.sys_clk_sig_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_1:
Name Fanout Delay (ns) Site Resource
ROUTE 382 0.783 LPLL.CLKOP to R19C37B.WCK controller_marco.sys_clk_sig_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.252ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/MONSTER_MANAGER_INST/wb_data[1] (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco/inst_wb_data_fifo/fifo_pfu_0_3/RAM0 (to controller_marco.sys_clk_sig_c +)
FF controller_marco/inst_wb_data_fifo/fifo_pfu_0_3/RAM0
Delay: 0.399ns (37.6% logic, 62.4% route), 2 logic levels.
Constraint Details:
0.399ns physical path delay controller_marco/MONSTER_MANAGER_INST/SLICE_1305 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_3 meets
0.147ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.252ns
Physical Path Details:
Data path controller_marco/MONSTER_MANAGER_INST/SLICE_1305 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R21C35D.CLK to R21C35D.Q1 controller_marco/MONSTER_MANAGER_INST/SLICE_1305 (from controller_marco.sys_clk_sig_c)
ROUTE 1 0.249 R21C35D.Q1 to R21C35C.B1 controller_marco/wb_data_sig[1]
ZERO_DEL --- 0.000 R21C35C.B1 to R21C35C.WDO1 controller_marco/inst_wb_data_fifo/fifo_pfu_0_3.17
ROUTE 1 0.000 R21C35C.WDO1 to R21C35A.WD1 controller_marco/inst_wb_data_fifo/fifo_pfu_0_3/WD1_INT (to controller_marco.sys_clk_sig_c)
--------
0.399 (37.6% logic, 62.4% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/MONSTER_MANAGER_INST/SLICE_1305:
Name Fanout Delay (ns) Site Resource
ROUTE 382 0.762 LPLL.CLKOP to R21C35D.CLK controller_marco.sys_clk_sig_c
--------
0.762 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_3:
Name Fanout Delay (ns) Site Resource
ROUTE 382 0.762 LPLL.CLKOP to R21C35A.WCK controller_marco.sys_clk_sig_c
--------
0.762 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.253ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/MONSTER_MANAGER_INST/wb_data[5] (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco/inst_wb_data_fifo/fifo_pfu_0_2/RAM0 (to controller_marco.sys_clk_sig_c +)
FF controller_marco/inst_wb_data_fifo/fifo_pfu_0_2/RAM0
Delay: 0.400ns (37.5% logic, 62.5% route), 2 logic levels.
Constraint Details:
0.400ns physical path delay controller_marco/MONSTER_MANAGER_INST/SLICE_1307 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_2 meets
0.147ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.253ns
Physical Path Details:
Data path controller_marco/MONSTER_MANAGER_INST/SLICE_1307 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R22C35D.CLK to R22C35D.Q1 controller_marco/MONSTER_MANAGER_INST/SLICE_1307 (from controller_marco.sys_clk_sig_c)
ROUTE 1 0.250 R22C35D.Q1 to R22C36C.B1 controller_marco/wb_data_sig[5]
ZERO_DEL --- 0.000 R22C36C.B1 to R22C36C.WDO1 controller_marco/inst_wb_data_fifo/fifo_pfu_0_2.16
ROUTE 1 0.000 R22C36C.WDO1 to R22C36A.WD1 controller_marco/inst_wb_data_fifo/fifo_pfu_0_2/WD1_INT (to controller_marco.sys_clk_sig_c)
--------
0.400 (37.5% logic, 62.5% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/MONSTER_MANAGER_INST/SLICE_1307:
Name Fanout Delay (ns) Site Resource
ROUTE 382 0.762 LPLL.CLKOP to R22C35D.CLK controller_marco.sys_clk_sig_c
--------
0.762 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_2:
Name Fanout Delay (ns) Site Resource
ROUTE 382 0.762 LPLL.CLKOP to R22C36A.WCK controller_marco.sys_clk_sig_c
--------
0.762 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.270ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/MONSTER_MANAGER_INST/tft_sdram_green[2] (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_2/RAM1 (to controller_marco.sys_clk_sig_c +)
FF controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_2/RAM1
Delay: 0.417ns (36.0% logic, 64.0% route), 2 logic levels.
Constraint Details:
0.417ns physical path delay controller_marco/MONSTER_MANAGER_INST/SLICE_1292 to controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_2 meets
0.147ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.270ns
Physical Path Details:
Data path controller_marco/MONSTER_MANAGER_INST/SLICE_1292 to controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R14C38B.CLK to R14C38B.Q0 controller_marco/MONSTER_MANAGER_INST/SLICE_1292 (from controller_marco.sys_clk_sig_c)
ROUTE 1 0.267 R14C38B.Q0 to R12C38C.D1 controller_marco/tft_sdram_green_in_sig[2]
ZERO_DEL --- 0.000 R12C38C.D1 to R12C38C.WDO3 controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_2.61
ROUTE 1 0.000 R12C38C.WDO3 to R12C38B.WD1 controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_2/WD3_INT (to controller_marco.sys_clk_sig_c)
--------
0.417 (36.0% logic, 64.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/MONSTER_MANAGER_INST/SLICE_1292:
Name Fanout Delay (ns) Site Resource
ROUTE 382 0.783 LPLL.CLKOP to R14C38B.CLK controller_marco.sys_clk_sig_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFT_PIXEL_RGB_PIPELINER_INST/PIXEL_RGB_FIFO_INST/fifo_pfu_0_2:
Name Fanout Delay (ns) Site Resource
ROUTE 382 0.783 LPLL.CLKOP to R12C38B.WCK controller_marco.sys_clk_sig_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.279ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/MONSTER_MANAGER_INST/wb_data[3] (from controller_marco.sys_clk_sig_c +)
Destination: FF Data in controller_marco/inst_wb_data_fifo/fifo_pfu_0_3/RAM1 (to controller_marco.sys_clk_sig_c +)
FF controller_marco/inst_wb_data_fifo/fifo_pfu_0_3/RAM1
Delay: 0.426ns (35.2% logic, 64.8% route), 2 logic levels.
Constraint Details:
0.426ns physical path delay controller_marco/MONSTER_MANAGER_INST/SLICE_1306 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_3.18 meets
0.147ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.279ns
Physical Path Details:
Data path controller_marco/MONSTER_MANAGER_INST/SLICE_1306 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_3.18:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R21C36B.CLK to R21C36B.Q1 controller_marco/MONSTER_MANAGER_INST/SLICE_1306 (from controller_marco.sys_clk_sig_c)
ROUTE 1 0.276 R21C36B.Q1 to R21C35C.D1 controller_marco/wb_data_sig[3]
ZERO_DEL --- 0.000 R21C35C.D1 to R21C35C.WDO3 controller_marco/inst_wb_data_fifo/fifo_pfu_0_3.17
ROUTE 1 0.000 R21C35C.WDO3 to R21C35B.WD1 controller_marco/inst_wb_data_fifo/fifo_pfu_0_3/WD3_INT (to controller_marco.sys_clk_sig_c)
--------
0.426 (35.2% logic, 64.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/MONSTER_MANAGER_INST/SLICE_1306:
Name Fanout Delay (ns) Site Resource
ROUTE 382 0.762 LPLL.CLKOP to R21C36B.CLK controller_marco.sys_clk_sig_c
--------
0.762 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/inst_wb_data_fifo/fifo_pfu_0_3.18:
Name Fanout Delay (ns) Site Resource
ROUTE 382 0.762 LPLL.CLKOP to R21C35B.WCK controller_marco.sys_clk_sig_c
--------
0.762 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
Preference: FREQUENCY NET "controller_marco/osch_clk_sig_c" 10.230000 MHz ;
310 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.342ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/pll_lock_reg0 (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/pll_lock_reg1 (to controller_marco/osch_clk_sig_c +)
Delay: 0.321ns (46.7% logic, 53.3% route), 1 logic levels.
Constraint Details:
0.321ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_857 to controller_marco/POWER_MANAGER_INST/SLICE_857 meets
-0.021ns M_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.021ns) by 0.342ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_857 to controller_marco/POWER_MANAGER_INST/SLICE_857:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R7C23C.CLK to R7C23C.Q0 controller_marco/POWER_MANAGER_INST/SLICE_857 (from controller_marco/osch_clk_sig_c)
ROUTE 1 0.171 R7C23C.Q0 to R7C23C.M1 controller_marco/POWER_MANAGER_INST/pll_lock_reg0 (to controller_marco/osch_clk_sig_c)
--------
0.321 (46.7% logic, 53.3% route), 1 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_857:
Name Fanout Delay (ns) Site Resource
ROUTE 17 1.618 OSC.OSC to R7C23C.CLK controller_marco/osch_clk_sig_c
--------
1.618 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_857:
Name Fanout Delay (ns) Site Resource
ROUTE 17 1.618 OSC.OSC to R7C23C.CLK controller_marco/osch_clk_sig_c
--------
1.618 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.425ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/delay_st[0] (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/delay_st[0] (to controller_marco/osch_clk_sig_c +)
Delay: 0.411ns (64.0% logic, 36.0% route), 2 logic levels.
Constraint Details:
0.411ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_853 to controller_marco/POWER_MANAGER_INST/SLICE_853 meets
-0.014ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.014ns) by 0.425ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_853 to controller_marco/POWER_MANAGER_INST/SLICE_853:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R9C30B.CLK to R9C30B.Q0 controller_marco/POWER_MANAGER_INST/SLICE_853 (from controller_marco/osch_clk_sig_c)
ROUTE 2 0.148 R9C30B.Q0 to R9C30B.A0 controller_marco/POWER_MANAGER_INST/delay_st[0]
CTOF_DEL --- 0.113 R9C30B.A0 to R9C30B.F0 controller_marco/POWER_MANAGER_INST/SLICE_853
ROUTE 1 0.000 R9C30B.F0 to R9C30B.DI0 controller_marco/POWER_MANAGER_INST/N_12078_0 (to controller_marco/osch_clk_sig_c)
--------
0.411 (64.0% logic, 36.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_853:
Name Fanout Delay (ns) Site Resource
ROUTE 17 1.618 OSC.OSC to R9C30B.CLK controller_marco/osch_clk_sig_c
--------
1.618 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_853:
Name Fanout Delay (ns) Site Resource
ROUTE 17 1.618 OSC.OSC to R9C30B.CLK controller_marco/osch_clk_sig_c
--------
1.618 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.425ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/delay_st[3] (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/delay_st[3] (to controller_marco/osch_clk_sig_c +)
Delay: 0.411ns (64.0% logic, 36.0% route), 2 logic levels.
Constraint Details:
0.411ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_854 to controller_marco/POWER_MANAGER_INST/SLICE_854 meets
-0.014ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.014ns) by 0.425ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_854 to controller_marco/POWER_MANAGER_INST/SLICE_854:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R8C27B.CLK to R8C27B.Q1 controller_marco/POWER_MANAGER_INST/SLICE_854 (from controller_marco/osch_clk_sig_c)
ROUTE 4 0.148 R8C27B.Q1 to R8C27B.A1 controller_marco/POWER_MANAGER_INST/delay_st[3]
CTOF_DEL --- 0.113 R8C27B.A1 to R8C27B.F1 controller_marco/POWER_MANAGER_INST/SLICE_854
ROUTE 1 0.000 R8C27B.F1 to R8C27B.DI1 controller_marco/POWER_MANAGER_INST/delay_st_ns[3] (to controller_marco/osch_clk_sig_c)
--------
0.411 (64.0% logic, 36.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_854:
Name Fanout Delay (ns) Site Resource
ROUTE 17 1.618 OSC.OSC to R8C27B.CLK controller_marco/osch_clk_sig_c
--------
1.618 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_854:
Name Fanout Delay (ns) Site Resource
ROUTE 17 1.618 OSC.OSC to R8C27B.CLK controller_marco/osch_clk_sig_c
--------
1.618 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.425ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/delay_st[4] (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/delay_st[4] (to controller_marco/osch_clk_sig_c +)
Delay: 0.411ns (64.0% logic, 36.0% route), 2 logic levels.
Constraint Details:
0.411ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_855 to controller_marco/POWER_MANAGER_INST/SLICE_855 meets
-0.014ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.014ns) by 0.425ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_855 to controller_marco/POWER_MANAGER_INST/SLICE_855:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R8C27A.CLK to R8C27A.Q0 controller_marco/POWER_MANAGER_INST/SLICE_855 (from controller_marco/osch_clk_sig_c)
ROUTE 2 0.148 R8C27A.Q0 to R8C27A.A0 controller_marco/POWER_MANAGER_INST/delay_st[4]
CTOF_DEL --- 0.113 R8C27A.A0 to R8C27A.F0 controller_marco/POWER_MANAGER_INST/SLICE_855
ROUTE 1 0.000 R8C27A.F0 to R8C27A.DI0 controller_marco/POWER_MANAGER_INST/delay_st_ns[2] (to controller_marco/osch_clk_sig_c)
--------
0.411 (64.0% logic, 36.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_855:
Name Fanout Delay (ns) Site Resource
ROUTE 17 1.618 OSC.OSC to R8C27A.CLK controller_marco/osch_clk_sig_c
--------
1.618 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_855:
Name Fanout Delay (ns) Site Resource
ROUTE 17 1.618 OSC.OSC to R8C27A.CLK controller_marco/osch_clk_sig_c
--------
1.618 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.425ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/delay_st[1] (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/delay_st[1] (to controller_marco/osch_clk_sig_c +)
Delay: 0.411ns (64.0% logic, 36.0% route), 2 logic levels.
Constraint Details:
0.411ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_853 to controller_marco/POWER_MANAGER_INST/SLICE_853 meets
-0.014ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.014ns) by 0.425ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_853 to controller_marco/POWER_MANAGER_INST/SLICE_853:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R9C30B.CLK to R9C30B.Q1 controller_marco/POWER_MANAGER_INST/SLICE_853 (from controller_marco/osch_clk_sig_c)
ROUTE 4 0.148 R9C30B.Q1 to R9C30B.A1 controller_marco/POWER_MANAGER_INST/delay_st[1]
CTOF_DEL --- 0.113 R9C30B.A1 to R9C30B.F1 controller_marco/POWER_MANAGER_INST/SLICE_853
ROUTE 1 0.000 R9C30B.F1 to R9C30B.DI1 controller_marco/POWER_MANAGER_INST/delay_st_ns[5] (to controller_marco/osch_clk_sig_c)
--------
0.411 (64.0% logic, 36.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_853:
Name Fanout Delay (ns) Site Resource
ROUTE 17 1.618 OSC.OSC to R9C30B.CLK controller_marco/osch_clk_sig_c
--------
1.618 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_853:
Name Fanout Delay (ns) Site Resource
ROUTE 17 1.618 OSC.OSC to R9C30B.CLK controller_marco/osch_clk_sig_c
--------
1.618 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.425ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/timer_cnt[1] (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/timer_cnt[1] (to controller_marco/osch_clk_sig_c +)
Delay: 0.411ns (64.0% logic, 36.0% route), 2 logic levels.
Constraint Details:
0.411ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_177 to controller_marco/POWER_MANAGER_INST/SLICE_177 meets
-0.014ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.014ns) by 0.425ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_177 to controller_marco/POWER_MANAGER_INST/SLICE_177:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R9C39B.CLK to R9C39B.Q0 controller_marco/POWER_MANAGER_INST/SLICE_177 (from controller_marco/osch_clk_sig_c)
ROUTE 2 0.148 R9C39B.Q0 to R9C39B.A0 controller_marco/POWER_MANAGER_INST/timer_cnt[1]
CTOF_DEL --- 0.113 R9C39B.A0 to R9C39B.F0 controller_marco/POWER_MANAGER_INST/SLICE_177
ROUTE 1 0.000 R9C39B.F0 to R9C39B.DI0 controller_marco/POWER_MANAGER_INST/timer_cnt_s[1] (to controller_marco/osch_clk_sig_c)
--------
0.411 (64.0% logic, 36.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_177:
Name Fanout Delay (ns) Site Resource
ROUTE 17 1.618 OSC.OSC to R9C39B.CLK controller_marco/osch_clk_sig_c
--------
1.618 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_177:
Name Fanout Delay (ns) Site Resource
ROUTE 17 1.618 OSC.OSC to R9C39B.CLK controller_marco/osch_clk_sig_c
--------
1.618 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.425ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/timer_cnt[2] (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/timer_cnt[2] (to controller_marco/osch_clk_sig_c +)
Delay: 0.411ns (64.0% logic, 36.0% route), 2 logic levels.
Constraint Details:
0.411ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_177 to controller_marco/POWER_MANAGER_INST/SLICE_177 meets
-0.014ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.014ns) by 0.425ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_177 to controller_marco/POWER_MANAGER_INST/SLICE_177:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R9C39B.CLK to R9C39B.Q1 controller_marco/POWER_MANAGER_INST/SLICE_177 (from controller_marco/osch_clk_sig_c)
ROUTE 2 0.148 R9C39B.Q1 to R9C39B.A1 controller_marco/POWER_MANAGER_INST/timer_cnt[2]
CTOF_DEL --- 0.113 R9C39B.A1 to R9C39B.F1 controller_marco/POWER_MANAGER_INST/SLICE_177
ROUTE 1 0.000 R9C39B.F1 to R9C39B.DI1 controller_marco/POWER_MANAGER_INST/timer_cnt_s[2] (to controller_marco/osch_clk_sig_c)
--------
0.411 (64.0% logic, 36.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_177:
Name Fanout Delay (ns) Site Resource
ROUTE 17 1.618 OSC.OSC to R9C39B.CLK controller_marco/osch_clk_sig_c
--------
1.618 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_177:
Name Fanout Delay (ns) Site Resource
ROUTE 17 1.618 OSC.OSC to R9C39B.CLK controller_marco/osch_clk_sig_c
--------
1.618 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.429ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/delay_st[5] (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/delay_st[4] (to controller_marco/osch_clk_sig_c +)
Delay: 0.415ns (63.4% logic, 36.6% route), 2 logic levels.
Constraint Details:
0.415ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_855 to controller_marco/POWER_MANAGER_INST/SLICE_855 meets
-0.014ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.014ns) by 0.429ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_855 to controller_marco/POWER_MANAGER_INST/SLICE_855:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R8C27A.CLK to R8C27A.Q1 controller_marco/POWER_MANAGER_INST/SLICE_855 (from controller_marco/osch_clk_sig_c)
ROUTE 1 0.152 R8C27A.Q1 to R8C27A.C0 controller_marco/POWER_MANAGER_INST/delay_st[5]
CTOF_DEL --- 0.113 R8C27A.C0 to R8C27A.F0 controller_marco/POWER_MANAGER_INST/SLICE_855
ROUTE 1 0.000 R8C27A.F0 to R8C27A.DI0 controller_marco/POWER_MANAGER_INST/delay_st_ns[2] (to controller_marco/osch_clk_sig_c)
--------
0.415 (63.4% logic, 36.6% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_855:
Name Fanout Delay (ns) Site Resource
ROUTE 17 1.618 OSC.OSC to R8C27A.CLK controller_marco/osch_clk_sig_c
--------
1.618 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_855:
Name Fanout Delay (ns) Site Resource
ROUTE 17 1.618 OSC.OSC to R8C27A.CLK controller_marco/osch_clk_sig_c
--------
1.618 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.432ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/timer_cnt[0] (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/timer_cnt_100us_reg (to controller_marco/osch_clk_sig_c +)
Delay: 0.418ns (62.9% logic, 37.1% route), 2 logic levels.
Constraint Details:
0.418ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_170 to controller_marco/POWER_MANAGER_INST/SLICE_858 meets
-0.014ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.014ns) by 0.432ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_170 to controller_marco/POWER_MANAGER_INST/SLICE_858:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R9C39A.CLK to R9C39A.Q1 controller_marco/POWER_MANAGER_INST/SLICE_170 (from controller_marco/osch_clk_sig_c)
ROUTE 3 0.155 R9C39A.Q1 to R8C39A.D0 controller_marco/POWER_MANAGER_INST/timer_cnt[0]
CTOF_DEL --- 0.113 R8C39A.D0 to R8C39A.F0 controller_marco/POWER_MANAGER_INST/SLICE_858
ROUTE 1 0.000 R8C39A.F0 to R8C39A.DI0 controller_marco/POWER_MANAGER_INST/N_17_mux (to controller_marco/osch_clk_sig_c)
--------
0.418 (62.9% logic, 37.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_170:
Name Fanout Delay (ns) Site Resource
ROUTE 17 1.618 OSC.OSC to R9C39A.CLK controller_marco/osch_clk_sig_c
--------
1.618 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_858:
Name Fanout Delay (ns) Site Resource
ROUTE 17 1.618 OSC.OSC to R8C39A.CLK controller_marco/osch_clk_sig_c
--------
1.618 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.432ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/POWER_MANAGER_INST/delay_st[4] (from controller_marco/osch_clk_sig_c +)
Destination: FF Data in controller_marco/POWER_MANAGER_INST/delay_st[3] (to controller_marco/osch_clk_sig_c +)
Delay: 0.418ns (62.9% logic, 37.1% route), 2 logic levels.
Constraint Details:
0.418ns physical path delay controller_marco/POWER_MANAGER_INST/SLICE_855 to controller_marco/POWER_MANAGER_INST/SLICE_854 meets
-0.014ns DIN_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling -0.014ns) by 0.432ns
Physical Path Details:
Data path controller_marco/POWER_MANAGER_INST/SLICE_855 to controller_marco/POWER_MANAGER_INST/SLICE_854:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R8C27A.CLK to R8C27A.Q0 controller_marco/POWER_MANAGER_INST/SLICE_855 (from controller_marco/osch_clk_sig_c)
ROUTE 2 0.155 R8C27A.Q0 to R8C27B.C1 controller_marco/POWER_MANAGER_INST/delay_st[4]
CTOF_DEL --- 0.113 R8C27B.C1 to R8C27B.F1 controller_marco/POWER_MANAGER_INST/SLICE_854
ROUTE 1 0.000 R8C27B.F1 to R8C27B.DI1 controller_marco/POWER_MANAGER_INST/delay_st_ns[3] (to controller_marco/osch_clk_sig_c)
--------
0.418 (62.9% logic, 37.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_855:
Name Fanout Delay (ns) Site Resource
ROUTE 17 1.618 OSC.OSC to R8C27A.CLK controller_marco/osch_clk_sig_c
--------
1.618 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/OSCH_INST to controller_marco/POWER_MANAGER_INST/SLICE_854:
Name Fanout Delay (ns) Site Resource
ROUTE 17 1.618 OSC.OSC to R8C27B.CLK controller_marco/osch_clk_sig_c
--------
1.618 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
Preference: FREQUENCY NET "tft_clk_c_c" 35.714286 MHz ;
3364 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.154ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/pixel_data_reg[11] (from tft_clk_c_c +)
Destination: FF Data in controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_1/RAM1 (to tft_clk_c_c +)
FF controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_1/RAM1
Delay: 0.301ns (49.8% logic, 50.2% route), 2 logic levels.
Constraint Details:
0.301ns physical path delay controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1169 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_1.33 meets
0.147ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.154ns
Physical Path Details:
Data path controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1169 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_1.33:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R5C29D.CLK to R5C29D.Q1 controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1169 (from tft_clk_c_c)
ROUTE 1 0.151 R5C29D.Q1 to R5C31C.D1 controller_marco/fifo_wr_rgb_sig[11]
ZERO_DEL --- 0.000 R5C31C.D1 to R5C31C.WDO3 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_1.32
ROUTE 1 0.000 R5C31C.WDO3 to R5C31B.WD1 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_1/WD3_INT (to tft_clk_c_c)
--------
0.301 (49.8% logic, 50.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1169:
Name Fanout Delay (ns) Site Resource
ROUTE 287 0.783 LPLL.CLKOS3 to R5C29D.CLK tft_clk_c_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_1.33:
Name Fanout Delay (ns) Site Resource
ROUTE 287 0.783 LPLL.CLKOS3 to R5C31B.WCK tft_clk_c_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.157ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/FF_75 (from tft_clk_c_c +)
Destination: FF Data in controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_2/RAM0 (to tft_clk_c_c +)
FF controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_2/RAM0
Delay: 0.304ns (49.3% logic, 50.7% route), 2 logic levels.
Constraint Details:
0.304ns physical path delay controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/SLICE_849 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_2.35 meets
0.147ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.157ns
Physical Path Details:
Data path controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/SLICE_849 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_2.35:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R4C30C.CLK to R4C30C.Q1 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/SLICE_849 (from tft_clk_c_c)
ROUTE 4 0.154 R4C30C.Q1 to R5C30C.D0 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/wptr_3
ZERO_DEL --- 0.000 R5C30C.D0 to R5C30C.WADO3 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_2.34
ROUTE 2 0.000 R5C30C.WADO3 to R5C30A.WAD3 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_2/WAD3_INT (to tft_clk_c_c)
--------
0.304 (49.3% logic, 50.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/SLICE_849:
Name Fanout Delay (ns) Site Resource
ROUTE 287 0.783 LPLL.CLKOS3 to R4C30C.CLK tft_clk_c_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_2.35:
Name Fanout Delay (ns) Site Resource
ROUTE 287 0.783 LPLL.CLKOS3 to R5C30A.WCK tft_clk_c_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.157ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/FF_75 (from tft_clk_c_c +)
Destination: FF Data in controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_2/RAM1 (to tft_clk_c_c +)
FF controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_2/RAM1
Delay: 0.304ns (49.3% logic, 50.7% route), 2 logic levels.
Constraint Details:
0.304ns physical path delay controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/SLICE_849 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_2 meets
0.147ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.157ns
Physical Path Details:
Data path controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/SLICE_849 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R4C30C.CLK to R4C30C.Q1 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/SLICE_849 (from tft_clk_c_c)
ROUTE 4 0.154 R4C30C.Q1 to R5C30C.D0 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/wptr_3
ZERO_DEL --- 0.000 R5C30C.D0 to R5C30C.WADO3 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_2.34
ROUTE 2 0.000 R5C30C.WADO3 to R5C30B.WAD3 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_2/WAD3_INT (to tft_clk_c_c)
--------
0.304 (49.3% logic, 50.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/SLICE_849:
Name Fanout Delay (ns) Site Resource
ROUTE 287 0.783 LPLL.CLKOS3 to R4C30C.CLK tft_clk_c_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_2:
Name Fanout Delay (ns) Site Resource
ROUTE 287 0.783 LPLL.CLKOS3 to R5C30B.WCK tft_clk_c_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.240ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/pixel_data_reg[12] (from tft_clk_c_c +)
Destination: FF Data in controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_0/RAM0 (to tft_clk_c_c +)
FF controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_0/RAM0
Delay: 0.387ns (38.8% logic, 61.2% route), 2 logic levels.
Constraint Details:
0.387ns physical path delay controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1170 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_0.31 meets
0.147ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.240ns
Physical Path Details:
Data path controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1170 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_0.31:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R6C29C.CLK to R6C29C.Q0 controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1170 (from tft_clk_c_c)
ROUTE 1 0.237 R6C29C.Q0 to R6C31C.A1 controller_marco/fifo_wr_rgb_sig[12]
ZERO_DEL --- 0.000 R6C31C.A1 to R6C31C.WDO0 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_0.30
ROUTE 1 0.000 R6C31C.WDO0 to R6C31A.WD0 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_0/WD0_INT (to tft_clk_c_c)
--------
0.387 (38.8% logic, 61.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1170:
Name Fanout Delay (ns) Site Resource
ROUTE 287 0.783 LPLL.CLKOS3 to R6C29C.CLK tft_clk_c_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_0.31:
Name Fanout Delay (ns) Site Resource
ROUTE 287 0.783 LPLL.CLKOS3 to R6C31A.WCK tft_clk_c_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.247ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/pixel_data_reg[3] (from tft_clk_c_c +)
Destination: FF Data in controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_3/RAM1 (to tft_clk_c_c +)
FF controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_3/RAM1
Delay: 0.394ns (38.1% logic, 61.9% route), 2 logic levels.
Constraint Details:
0.394ns physical path delay controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1165 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_3.36 meets
0.147ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.247ns
Physical Path Details:
Data path controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1165 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_3.36:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R6C28D.CLK to R6C28D.Q1 controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1165 (from tft_clk_c_c)
ROUTE 1 0.244 R6C28D.Q1 to R6C30C.D1 controller_marco/fifo_wr_rgb_sig[3]
ZERO_DEL --- 0.000 R6C30C.D1 to R6C30C.WDO3 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_3.37
ROUTE 1 0.000 R6C30C.WDO3 to R6C30B.WD1 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_3/WD3_INT (to tft_clk_c_c)
--------
0.394 (38.1% logic, 61.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1165:
Name Fanout Delay (ns) Site Resource
ROUTE 287 0.783 LPLL.CLKOS3 to R6C28D.CLK tft_clk_c_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_3.36:
Name Fanout Delay (ns) Site Resource
ROUTE 287 0.783 LPLL.CLKOS3 to R6C30B.WCK tft_clk_c_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.247ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/pixel_addr_reg[11] (from tft_clk_c_c +)
Destination: FF Data in controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3/RAM1 (to tft_clk_c_c +)
FF controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3/RAM1
Delay: 0.394ns (38.1% logic, 61.9% route), 2 logic levels.
Constraint Details:
0.394ns physical path delay controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1157 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3.25 meets
0.147ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.247ns
Physical Path Details:
Data path controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1157 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3.25:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R23C32D.CLK to R23C32D.Q1 controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1157 (from tft_clk_c_c)
ROUTE 1 0.244 R23C32D.Q1 to R23C34C.D1 controller_marco/fifo_wr_add_sig[11]
ZERO_DEL --- 0.000 R23C34C.D1 to R23C34C.WDO3 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3
ROUTE 1 0.000 R23C34C.WDO3 to R23C34B.WD1 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3/WD3_INT (to tft_clk_c_c)
--------
0.394 (38.1% logic, 61.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1157:
Name Fanout Delay (ns) Site Resource
ROUTE 287 0.762 LPLL.CLKOS3 to R23C32D.CLK tft_clk_c_c
--------
0.762 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3.25:
Name Fanout Delay (ns) Site Resource
ROUTE 287 0.762 LPLL.CLKOS3 to R23C34B.WCK tft_clk_c_c
--------
0.762 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.247ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/pixel_addr_reg[19] (from tft_clk_c_c +)
Destination: FF Data in controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_1/RAM1 (to tft_clk_c_c +)
FF controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_1/RAM1
Delay: 0.394ns (38.1% logic, 61.9% route), 2 logic levels.
Constraint Details:
0.394ns physical path delay controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1161 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_1.21 meets
0.147ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.247ns
Physical Path Details:
Data path controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1161 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_1.21:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R25C33A.CLK to R25C33A.Q1 controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1161 (from tft_clk_c_c)
ROUTE 1 0.244 R25C33A.Q1 to R23C33C.D1 controller_marco/fifo_wr_add_sig[19]
ZERO_DEL --- 0.000 R23C33C.D1 to R23C33C.WDO3 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_1.20
ROUTE 1 0.000 R23C33C.WDO3 to R23C33B.WD1 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_1/WD3_INT (to tft_clk_c_c)
--------
0.394 (38.1% logic, 61.9% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1161:
Name Fanout Delay (ns) Site Resource
ROUTE 287 0.762 LPLL.CLKOS3 to R25C33A.CLK tft_clk_c_c
--------
0.762 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_1.21:
Name Fanout Delay (ns) Site Resource
ROUTE 287 0.762 LPLL.CLKOS3 to R23C33B.WCK tft_clk_c_c
--------
0.762 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.251ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/pixel_addr_reg[10] (from tft_clk_c_c +)
Destination: FF Data in controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3/RAM1 (to tft_clk_c_c +)
FF controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3/RAM1
Delay: 0.398ns (37.7% logic, 62.3% route), 2 logic levels.
Constraint Details:
0.398ns physical path delay controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1157 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3.25 meets
0.147ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.251ns
Physical Path Details:
Data path controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1157 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3.25:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R23C32D.CLK to R23C32D.Q0 controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1157 (from tft_clk_c_c)
ROUTE 1 0.248 R23C32D.Q0 to R23C34C.C1 controller_marco/fifo_wr_add_sig[10]
ZERO_DEL --- 0.000 R23C34C.C1 to R23C34C.WDO2 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3
ROUTE 1 0.000 R23C34C.WDO2 to R23C34B.WD0 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3/WD2_INT (to tft_clk_c_c)
--------
0.398 (37.7% logic, 62.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1157:
Name Fanout Delay (ns) Site Resource
ROUTE 287 0.762 LPLL.CLKOS3 to R23C32D.CLK tft_clk_c_c
--------
0.762 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_3.25:
Name Fanout Delay (ns) Site Resource
ROUTE 287 0.762 LPLL.CLKOS3 to R23C34B.WCK tft_clk_c_c
--------
0.762 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.251ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/pixel_data_reg[2] (from tft_clk_c_c +)
Destination: FF Data in controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_3/RAM1 (to tft_clk_c_c +)
FF controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_3/RAM1
Delay: 0.398ns (37.7% logic, 62.3% route), 2 logic levels.
Constraint Details:
0.398ns physical path delay controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1165 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_3.36 meets
0.147ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.251ns
Physical Path Details:
Data path controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1165 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_3.36:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R6C28D.CLK to R6C28D.Q0 controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1165 (from tft_clk_c_c)
ROUTE 1 0.248 R6C28D.Q0 to R6C30C.C1 controller_marco/fifo_wr_rgb_sig[2]
ZERO_DEL --- 0.000 R6C30C.C1 to R6C30C.WDO2 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_3.37
ROUTE 1 0.000 R6C30C.WDO2 to R6C30B.WD0 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_3/WD2_INT (to tft_clk_c_c)
--------
0.398 (37.7% logic, 62.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1165:
Name Fanout Delay (ns) Site Resource
ROUTE 287 0.783 LPLL.CLKOS3 to R6C28D.CLK tft_clk_c_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_3.36:
Name Fanout Delay (ns) Site Resource
ROUTE 287 0.783 LPLL.CLKOS3 to R6C30B.WCK tft_clk_c_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.251ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/pixel_data_reg[10] (from tft_clk_c_c +)
Destination: FF Data in controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_1/RAM1 (to tft_clk_c_c +)
FF controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_1/RAM1
Delay: 0.398ns (37.7% logic, 62.3% route), 2 logic levels.
Constraint Details:
0.398ns physical path delay controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1169 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_1.33 meets
0.147ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.251ns
Physical Path Details:
Data path controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1169 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_1.33:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R5C29D.CLK to R5C29D.Q0 controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1169 (from tft_clk_c_c)
ROUTE 1 0.248 R5C29D.Q0 to R5C31C.C1 controller_marco/fifo_wr_rgb_sig[10]
ZERO_DEL --- 0.000 R5C31C.C1 to R5C31C.WDO2 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_1.32
ROUTE 1 0.000 R5C31C.WDO2 to R5C31B.WD0 controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_1/WD2_INT (to tft_clk_c_c)
--------
0.398 (37.7% logic, 62.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/TFTSURFER_DEMO_INST/IMG_MOVER_VIEWER_INST/SLICE_1169:
Name Fanout Delay (ns) Site Resource
ROUTE 287 0.783 LPLL.CLKOS3 to R5C29D.CLK tft_clk_c_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path controller_marco/PLL_BLOCK_INST/PLLInst_0 to controller_marco/PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/fifo_pfu_0_1.33:
Name Fanout Delay (ns) Site Resource
ROUTE 287 0.783 LPLL.CLKOS3 to R5C31B.WCK tft_clk_c_c
--------
0.783 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
Preference: FREQUENCY PORT "ext_osc_clk" 25.000000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "ext_osc_clk_c" 25.000000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.154ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q SPI_top_INST/Data[11] (from ext_osc_clk_c +)
Destination: FF Data in SPI_top_INST/inst_memoria/mem_0_1/RAM1 (to ext_osc_clk_c +)
FF SPI_top_INST/inst_memoria/mem_0_1/RAM1
Delay: 0.301ns (49.8% logic, 50.2% route), 2 logic levels.
Constraint Details:
0.301ns physical path delay SPI_top_INST/SLICE_768 to SPI_top_INST/inst_memoria/mem_0_1 meets
0.147ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.154ns
Physical Path Details:
Data path SPI_top_INST/SLICE_768 to SPI_top_INST/inst_memoria/mem_0_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R18C27D.CLK to R18C27D.Q1 SPI_top_INST/SLICE_768 (from ext_osc_clk_c)
ROUTE 2 0.151 R18C27D.Q1 to R18C27C.D1 SPI_top_INST/Data[11]
ZERO_DEL --- 0.000 R18C27C.D1 to R18C27C.WDO3 SPI_top_INST/inst_memoria/mem_0_1.67
ROUTE 1 0.000 R18C27C.WDO3 to R18C27B.WD1 SPI_top_INST/inst_memoria/mem_0_1/WD3_INT (to ext_osc_clk_c)
--------
0.301 (49.8% logic, 50.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path ext_osc_clk to SPI_top_INST/SLICE_768:
Name Fanout Delay (ns) Site Resource
ROUTE 999 2.774 3.PADDI to R18C27D.CLK ext_osc_clk_c
--------
2.774 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path ext_osc_clk to SPI_top_INST/inst_memoria/mem_0_1:
Name Fanout Delay (ns) Site Resource
ROUTE 999 2.774 3.PADDI to R18C27B.WCK ext_osc_clk_c
--------
2.774 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.157ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm32_inst/platform_u/LM32/cpu/write_idx_w[3] (from ext_osc_clk_c +)
Destination: FF Data in lm32_inst/platform_u/LM32/cpu/registers_ram_7/RAM0 (to ext_osc_clk_c +)
FF lm32_inst/platform_u/LM32/cpu/registers_ram_7/RAM0
Delay: 0.304ns (49.3% logic, 50.7% route), 2 logic levels.
Constraint Details:
0.304ns physical path delay lm32_inst/platform_u/LM32/cpu/SLICE_1879 to lm32_inst/platform_u/LM32/cpu/registers_ram_7/SLICE_673 meets
0.147ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.157ns
Physical Path Details:
Data path lm32_inst/platform_u/LM32/cpu/SLICE_1879 to lm32_inst/platform_u/LM32/cpu/registers_ram_7/SLICE_673:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R21C10D.CLK to R21C10D.Q1 lm32_inst/platform_u/LM32/cpu/SLICE_1879 (from ext_osc_clk_c)
ROUTE 38 0.154 R21C10D.Q1 to R21C10C.D0 lm32_inst/platform_u/LM32/cpu/write_idx_w[3]
ZERO_DEL --- 0.000 R21C10C.D0 to R21C10C.WADO3 lm32_inst/platform_u/LM32/cpu/registers_ram_7/SLICE_672
ROUTE 2 0.000 R21C10C.WADO3 to R21C10A.WAD3 lm32_inst/platform_u/LM32/cpu/registers_ram_7/WAD3_INT (to ext_osc_clk_c)
--------
0.304 (49.3% logic, 50.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/SLICE_1879:
Name Fanout Delay (ns) Site Resource
ROUTE 999 2.754 3.PADDI to R21C10D.CLK ext_osc_clk_c
--------
2.754 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/registers_ram_7/SLICE_673:
Name Fanout Delay (ns) Site Resource
ROUTE 999 2.754 3.PADDI to R21C10A.WCK ext_osc_clk_c
--------
2.754 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.157ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q SPI_top_INST/WrAddress[3] (from ext_osc_clk_c +)
Destination: FF Data in SPI_top_INST/inst_memoria/mem_0_2/RAM1 (to ext_osc_clk_c +)
FF SPI_top_INST/inst_memoria/mem_0_2/RAM1
Delay: 0.304ns (49.3% logic, 50.7% route), 2 logic levels.
Constraint Details:
0.304ns physical path delay SPI_top_INST/SLICE_775 to SPI_top_INST/inst_memoria/mem_0_2.69 meets
0.147ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.157ns
Physical Path Details:
Data path SPI_top_INST/SLICE_775 to SPI_top_INST/inst_memoria/mem_0_2.69:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R18C28D.CLK to R18C28D.Q1 SPI_top_INST/SLICE_775 (from ext_osc_clk_c)
ROUTE 5 0.154 R18C28D.Q1 to R19C28C.D0 SPI_top_INST/WrAddress[3]
ZERO_DEL --- 0.000 R19C28C.D0 to R19C28C.WADO3 SPI_top_INST/inst_memoria/mem_0_2.70
ROUTE 2 0.000 R19C28C.WADO3 to R19C28B.WAD3 SPI_top_INST/inst_memoria/mem_0_2/WAD3_INT (to ext_osc_clk_c)
--------
0.304 (49.3% logic, 50.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path ext_osc_clk to SPI_top_INST/SLICE_775:
Name Fanout Delay (ns) Site Resource
ROUTE 999 2.774 3.PADDI to R18C28D.CLK ext_osc_clk_c
--------
2.774 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path ext_osc_clk to SPI_top_INST/inst_memoria/mem_0_2.69:
Name Fanout Delay (ns) Site Resource
ROUTE 999 2.774 3.PADDI to R19C28B.WCK ext_osc_clk_c
--------
2.774 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.157ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q SPI_top_INST/WrAddress[3] (from ext_osc_clk_c +)
Destination: FF Data in SPI_top_INST/inst_memoria/mem_0_2/RAM0 (to ext_osc_clk_c +)
FF SPI_top_INST/inst_memoria/mem_0_2/RAM0
Delay: 0.304ns (49.3% logic, 50.7% route), 2 logic levels.
Constraint Details:
0.304ns physical path delay SPI_top_INST/SLICE_775 to SPI_top_INST/inst_memoria/mem_0_2 meets
0.147ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.157ns
Physical Path Details:
Data path SPI_top_INST/SLICE_775 to SPI_top_INST/inst_memoria/mem_0_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R18C28D.CLK to R18C28D.Q1 SPI_top_INST/SLICE_775 (from ext_osc_clk_c)
ROUTE 5 0.154 R18C28D.Q1 to R19C28C.D0 SPI_top_INST/WrAddress[3]
ZERO_DEL --- 0.000 R19C28C.D0 to R19C28C.WADO3 SPI_top_INST/inst_memoria/mem_0_2.70
ROUTE 2 0.000 R19C28C.WADO3 to R19C28A.WAD3 SPI_top_INST/inst_memoria/mem_0_2/WAD3_INT (to ext_osc_clk_c)
--------
0.304 (49.3% logic, 50.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path ext_osc_clk to SPI_top_INST/SLICE_775:
Name Fanout Delay (ns) Site Resource
ROUTE 999 2.774 3.PADDI to R18C28D.CLK ext_osc_clk_c
--------
2.774 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path ext_osc_clk to SPI_top_INST/inst_memoria/mem_0_2:
Name Fanout Delay (ns) Site Resource
ROUTE 999 2.774 3.PADDI to R19C28A.WCK ext_osc_clk_c
--------
2.774 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.157ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q controller_marco/inst_wb_interface/W_fifo_wr_add_sig[14] (from ext_osc_clk_c +)
Destination: FF Data in controller_marco/scrittura_da_wishbone_pixel_addr_data_fifo/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_2/RAM1 (to ext_osc_clk_c +)
FF controller_marco/scrittura_da_wishbone_pixel_addr_data_fifo/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_2/RAM1
Delay: 0.304ns (49.3% logic, 50.7% route), 2 logic levels.
Constraint Details:
0.304ns physical path delay controller_marco/inst_wb_interface/SLICE_1119 to controller_marco/scrittura_da_wishbone_pixel_addr_data_fifo/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_2.42 meets
0.147ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.157ns
Physical Path Details:
Data path controller_marco/inst_wb_interface/SLICE_1119 to controller_marco/scrittura_da_wishbone_pixel_addr_data_fifo/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_2.42:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R17C28A.CLK to R17C28A.Q0 controller_marco/inst_wb_interface/SLICE_1119 (from ext_osc_clk_c)
ROUTE 1 0.154 R17C28A.Q0 to R17C29C.C1 controller_marco/W_fifo_wr_add_sig[14]
ZERO_DEL --- 0.000 R17C29C.C1 to R17C29C.WDO2 controller_marco/scrittura_da_wishbone_pixel_addr_data_fifo/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_2
ROUTE 1 0.000 R17C29C.WDO2 to R17C29B.WD0 controller_marco/scrittura_da_wishbone_pixel_addr_data_fifo/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_2/WD2_INT (to ext_osc_clk_c)
--------
0.304 (49.3% logic, 50.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path ext_osc_clk to controller_marco/inst_wb_interface/SLICE_1119:
Name Fanout Delay (ns) Site Resource
ROUTE 999 2.774 3.PADDI to R17C28A.CLK ext_osc_clk_c
--------
2.774 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path ext_osc_clk to controller_marco/scrittura_da_wishbone_pixel_addr_data_fifo/PIXEL_ADDR_FIFO_INST/fifo_pfu_0_2.42:
Name Fanout Delay (ns) Site Resource
ROUTE 999 2.774 3.PADDI to R17C29B.WCK ext_osc_clk_c
--------
2.774 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.157ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm32_inst/platform_u/LM32/cpu/write_idx_w[3] (from ext_osc_clk_c +)
Destination: FF Data in lm32_inst/platform_u/LM32/cpu/registers_ram_7/RAM1 (to ext_osc_clk_c +)
FF lm32_inst/platform_u/LM32/cpu/registers_ram_7/RAM1
Delay: 0.304ns (49.3% logic, 50.7% route), 2 logic levels.
Constraint Details:
0.304ns physical path delay lm32_inst/platform_u/LM32/cpu/SLICE_1879 to lm32_inst/platform_u/LM32/cpu/registers_ram_7/SLICE_674 meets
0.147ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.157ns
Physical Path Details:
Data path lm32_inst/platform_u/LM32/cpu/SLICE_1879 to lm32_inst/platform_u/LM32/cpu/registers_ram_7/SLICE_674:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R21C10D.CLK to R21C10D.Q1 lm32_inst/platform_u/LM32/cpu/SLICE_1879 (from ext_osc_clk_c)
ROUTE 38 0.154 R21C10D.Q1 to R21C10C.D0 lm32_inst/platform_u/LM32/cpu/write_idx_w[3]
ZERO_DEL --- 0.000 R21C10C.D0 to R21C10C.WADO3 lm32_inst/platform_u/LM32/cpu/registers_ram_7/SLICE_672
ROUTE 2 0.000 R21C10C.WADO3 to R21C10B.WAD3 lm32_inst/platform_u/LM32/cpu/registers_ram_7/WAD3_INT (to ext_osc_clk_c)
--------
0.304 (49.3% logic, 50.7% route), 2 logic levels.
Clock Skew Details:
Source Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/SLICE_1879:
Name Fanout Delay (ns) Site Resource
ROUTE 999 2.754 3.PADDI to R21C10D.CLK ext_osc_clk_c
--------
2.754 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/registers_ram_7/SLICE_674:
Name Fanout Delay (ns) Site Resource
ROUTE 999 2.754 3.PADDI to R21C10B.WCK ext_osc_clk_c
--------
2.754 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.159ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q SPI_top_INST/Data[2] (from ext_osc_clk_c +)
Destination: FF Data in SPI_top_INST/inst_memoria/mem_0_3/RAM1 (to ext_osc_clk_c +)
FF SPI_top_INST/inst_memoria/mem_0_3/RAM1
Delay: 0.306ns (49.0% logic, 51.0% route), 2 logic levels.
Constraint Details:
0.306ns physical path delay SPI_top_INST/SLICE_764 to SPI_top_INST/inst_memoria/mem_0_3.71 meets
0.147ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.159ns
Physical Path Details:
Data path SPI_top_INST/SLICE_764 to SPI_top_INST/inst_memoria/mem_0_3.71:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R19C27D.CLK to R19C27D.Q0 SPI_top_INST/SLICE_764 (from ext_osc_clk_c)
ROUTE 2 0.156 R19C27D.Q0 to R19C26C.C1 SPI_top_INST/Data[2]
ZERO_DEL --- 0.000 R19C26C.C1 to R19C26C.WDO2 SPI_top_INST/inst_memoria/mem_0_3.72
ROUTE 1 0.000 R19C26C.WDO2 to R19C26B.WD0 SPI_top_INST/inst_memoria/mem_0_3/WD2_INT (to ext_osc_clk_c)
--------
0.306 (49.0% logic, 51.0% route), 2 logic levels.
Clock Skew Details:
Source Clock Path ext_osc_clk to SPI_top_INST/SLICE_764:
Name Fanout Delay (ns) Site Resource
ROUTE 999 2.774 3.PADDI to R19C27D.CLK ext_osc_clk_c
--------
2.774 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path ext_osc_clk to SPI_top_INST/inst_memoria/mem_0_3.71:
Name Fanout Delay (ns) Site Resource
ROUTE 999 2.774 3.PADDI to R19C26B.WCK ext_osc_clk_c
--------
2.774 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.160ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm32_inst/platform_u/LM32/cpu/write_idx_w[2] (from ext_osc_clk_c +)
Destination: FF Data in lm32_inst/platform_u/LM32/cpu/registers_ram_7/RAM0 (to ext_osc_clk_c +)
FF lm32_inst/platform_u/LM32/cpu/registers_ram_7/RAM0
Delay: 0.307ns (48.9% logic, 51.1% route), 2 logic levels.
Constraint Details:
0.307ns physical path delay lm32_inst/platform_u/LM32/cpu/SLICE_1879 to lm32_inst/platform_u/LM32/cpu/registers_ram_7/SLICE_673 meets
0.147ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.160ns
Physical Path Details:
Data path lm32_inst/platform_u/LM32/cpu/SLICE_1879 to lm32_inst/platform_u/LM32/cpu/registers_ram_7/SLICE_673:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R21C10D.CLK to R21C10D.Q0 lm32_inst/platform_u/LM32/cpu/SLICE_1879 (from ext_osc_clk_c)
ROUTE 66 0.157 R21C10D.Q0 to R21C10C.C0 lm32_inst/platform_u/LM32/cpu/write_idx_w[2]
ZERO_DEL --- 0.000 R21C10C.C0 to R21C10C.WADO2 lm32_inst/platform_u/LM32/cpu/registers_ram_7/SLICE_672
ROUTE 2 0.000 R21C10C.WADO2 to R21C10A.WAD2 lm32_inst/platform_u/LM32/cpu/registers_ram_7/WAD2_INT (to ext_osc_clk_c)
--------
0.307 (48.9% logic, 51.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/SLICE_1879:
Name Fanout Delay (ns) Site Resource
ROUTE 999 2.754 3.PADDI to R21C10D.CLK ext_osc_clk_c
--------
2.754 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/registers_ram_7/SLICE_673:
Name Fanout Delay (ns) Site Resource
ROUTE 999 2.754 3.PADDI to R21C10A.WCK ext_osc_clk_c
--------
2.754 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.160ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q lm32_inst/platform_u/LM32/cpu/write_idx_w[2] (from ext_osc_clk_c +)
Destination: FF Data in lm32_inst/platform_u/LM32/cpu/registers_ram_7/RAM1 (to ext_osc_clk_c +)
FF lm32_inst/platform_u/LM32/cpu/registers_ram_7/RAM1
Delay: 0.307ns (48.9% logic, 51.1% route), 2 logic levels.
Constraint Details:
0.307ns physical path delay lm32_inst/platform_u/LM32/cpu/SLICE_1879 to lm32_inst/platform_u/LM32/cpu/registers_ram_7/SLICE_674 meets
0.147ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.160ns
Physical Path Details:
Data path lm32_inst/platform_u/LM32/cpu/SLICE_1879 to lm32_inst/platform_u/LM32/cpu/registers_ram_7/SLICE_674:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R21C10D.CLK to R21C10D.Q0 lm32_inst/platform_u/LM32/cpu/SLICE_1879 (from ext_osc_clk_c)
ROUTE 66 0.157 R21C10D.Q0 to R21C10C.C0 lm32_inst/platform_u/LM32/cpu/write_idx_w[2]
ZERO_DEL --- 0.000 R21C10C.C0 to R21C10C.WADO2 lm32_inst/platform_u/LM32/cpu/registers_ram_7/SLICE_672
ROUTE 2 0.000 R21C10C.WADO2 to R21C10B.WAD2 lm32_inst/platform_u/LM32/cpu/registers_ram_7/WAD2_INT (to ext_osc_clk_c)
--------
0.307 (48.9% logic, 51.1% route), 2 logic levels.
Clock Skew Details:
Source Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/SLICE_1879:
Name Fanout Delay (ns) Site Resource
ROUTE 999 2.754 3.PADDI to R21C10D.CLK ext_osc_clk_c
--------
2.754 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path ext_osc_clk to lm32_inst/platform_u/LM32/cpu/registers_ram_7/SLICE_674:
Name Fanout Delay (ns) Site Resource
ROUTE 999 2.754 3.PADDI to R21C10B.WCK ext_osc_clk_c
--------
2.754 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.161ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q SPI_top_INST/WrAddress[3] (from ext_osc_clk_c +)
Destination: FF Data in SPI_top_INST/inst_memoria/mem_0_1/RAM1 (to ext_osc_clk_c +)
FF SPI_top_INST/inst_memoria/mem_0_1/RAM1
Delay: 0.308ns (48.7% logic, 51.3% route), 2 logic levels.
Constraint Details:
0.308ns physical path delay SPI_top_INST/SLICE_775 to SPI_top_INST/inst_memoria/mem_0_1 meets
0.147ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.147ns) by 0.161ns
Physical Path Details:
Data path SPI_top_INST/SLICE_775 to SPI_top_INST/inst_memoria/mem_0_1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.150 R18C28D.CLK to R18C28D.Q1 SPI_top_INST/SLICE_775 (from ext_osc_clk_c)
ROUTE 5 0.158 R18C28D.Q1 to R18C27C.D0 SPI_top_INST/WrAddress[3]
ZERO_DEL --- 0.000 R18C27C.D0 to R18C27C.WADO3 SPI_top_INST/inst_memoria/mem_0_1.67
ROUTE 2 0.000 R18C27C.WADO3 to R18C27B.WAD3 SPI_top_INST/inst_memoria/mem_0_1/WAD3_INT (to ext_osc_clk_c)
--------
0.308 (48.7% logic, 51.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path ext_osc_clk to SPI_top_INST/SLICE_775:
Name Fanout Delay (ns) Site Resource
ROUTE 999 2.774 3.PADDI to R18C28D.CLK ext_osc_clk_c
--------
2.774 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path ext_osc_clk to SPI_top_INST/inst_memoria/mem_0_1:
Name Fanout Delay (ns) Site Resource
ROUTE 999 2.774 3.PADDI to R18C27B.WCK ext_osc_clk_c
--------
2.774 (0.0% logic, 100.0% route), 0 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET | | |
"controller_marco.sys_clk_sig_c" | | |
125.000000 MHz ; | -| -| 2
| | |
FREQUENCY NET | | |
"controller_marco/osch_clk_sig_c" | | |
10.230000 MHz ; | -| -| 1
| | |
FREQUENCY NET "tft_clk_c_c" 35.714286 | | |
MHz ; | -| -| 2
| | |
FREQUENCY PORT "ext_osc_clk" 25.000000 | | |
MHz ; | -| -| 0
| | |
FREQUENCY NET "ext_osc_clk_c" 25.000000 | | |
MHz ; | -| -| 2
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
No clock domain analysis is done. To analyze clock domains, please remove the BLOCK INTERCLOCKDOMAIN PATHS preference.
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 16647227 paths, 6 nets, and 20997 connections (98.3% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 0 (setup), 0 (hold)
Score: 0 (setup), 0 (hold)
Cumulative negative slack: 0 (0+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------