-------------------------------------------------------------------------------- Lattice TRACE Report - Setup Sat Sep 17 22:58:27 2011 Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved. Copyright (c) 1995 AT&T Corp. All rights reserved. Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved. Copyright (c) 2001 Agere Systems All rights reserved. Copyright (c) 2002-2011 Lattice Semiconductor Corporation, All rights reserved. Report Information ------------------ Design file: tftsurfer_top Device,speed: LCMXO2-1200HC,6 Report level: verbose report, limited to 10 items per preference -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY NET "sys_clk_sig_c" 130.000000 MHz ; 30 items scored, 4 timing errors detected. -------------------------------------------------------------------------------- Error: The following path exceeds requirements by 0.224ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/FF_1 (from sys_clk_sig_c +) Destination: FF Data in PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/FF_1 (to sys_clk_sig_c +) Delay: 7.770ns (32.5% logic, 67.5% route), 7 logic levels. Constraint Details: 7.770ns physical path delay SLICE_58 to SLICE_58 exceeds 7.692ns delay constraint less 0.000ns skew and 0.146ns DIN_SET requirement (totaling 7.546ns) by 0.224ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R9C16A.CLK to R9C16A.Q0 SLICE_58 (from sys_clk_sig_c) ROUTE 2 1.528 R9C16A.Q0 to R10C7B.C0 fifo_empty_sig CTOF_DEL --- 0.449 R10C7B.C0 to R10C7B.F0 PIXEL_ADDR_DATA_FIFO_INST/SLICE_662 ROUTE 15 3.713 R10C7B.F0 to R9C15A.B1 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/rden_i C1TOFCO_DE --- 0.752 R9C15A.B1 to R9C15A.FCO SLICE_57 ROUTE 1 0.000 R9C15A.FCO to R9C15B.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/cmp_ci FCITOFCO_D --- 0.143 R9C15B.FCI to R9C15B.FCO SLICE_61 ROUTE 1 0.000 R9C15B.FCO to R9C15C.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/co0_3 FCITOFCO_D --- 0.143 R9C15C.FCI to R9C15C.FCO SLICE_60 ROUTE 1 0.000 R9C15C.FCO to R9C15D.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/co1_3 FCITOFCO_D --- 0.143 R9C15D.FCI to R9C15D.FCO SLICE_59 ROUTE 1 0.000 R9C15D.FCO to R9C16A.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/empty_d_c FCITOF0_DE --- 0.495 R9C16A.FCI to R9C16A.F0 SLICE_58 ROUTE 1 0.000 R9C16A.F0 to R9C16A.DI0 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/empty_d (to sys_clk_sig_c) -------- 7.770 (32.5% logic, 67.5% route), 7 logic levels. Clock Skew Details: Source Clock: Delay Connection 1.479ns LPLL.CLKOP to R9C16A.CLK Destination Clock Path: Destination Clock: Delay Connection 1.479ns LPLL.CLKOP to R9C16A.CLK Error: The following path exceeds requirements by 0.198ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/FF_1 (from sys_clk_sig_c +) Destination: FF Data in PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/FF_1 (to sys_clk_sig_c +) Delay: 7.744ns (32.7% logic, 67.3% route), 7 logic levels. Constraint Details: 7.744ns physical path delay SLICE_58 to SLICE_58 exceeds 7.692ns delay constraint less 0.000ns skew and 0.146ns DIN_SET requirement (totaling 7.546ns) by 0.198ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R9C16A.CLK to R9C16A.Q0 SLICE_58 (from sys_clk_sig_c) ROUTE 2 1.528 R9C16A.Q0 to R10C7B.C0 fifo_empty_sig CTOF_DEL --- 0.449 R10C7B.C0 to R10C7B.F0 PIXEL_ADDR_DATA_FIFO_INST/SLICE_662 ROUTE 15 3.687 R10C7B.F0 to R9C15A.A1 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/rden_i C1TOFCO_DE --- 0.752 R9C15A.A1 to R9C15A.FCO SLICE_57 ROUTE 1 0.000 R9C15A.FCO to R9C15B.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/cmp_ci FCITOFCO_D --- 0.143 R9C15B.FCI to R9C15B.FCO SLICE_61 ROUTE 1 0.000 R9C15B.FCO to R9C15C.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/co0_3 FCITOFCO_D --- 0.143 R9C15C.FCI to R9C15C.FCO SLICE_60 ROUTE 1 0.000 R9C15C.FCO to R9C15D.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/co1_3 FCITOFCO_D --- 0.143 R9C15D.FCI to R9C15D.FCO SLICE_59 ROUTE 1 0.000 R9C15D.FCO to R9C16A.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/empty_d_c FCITOF0_DE --- 0.495 R9C16A.FCI to R9C16A.F0 SLICE_58 ROUTE 1 0.000 R9C16A.F0 to R9C16A.DI0 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/empty_d (to sys_clk_sig_c) -------- 7.744 (32.7% logic, 67.3% route), 7 logic levels. Clock Skew Details: Source Clock: Delay Connection 1.479ns LPLL.CLKOP to R9C16A.CLK Destination Clock Path: Destination Clock: Delay Connection 1.479ns LPLL.CLKOP to R9C16A.CLK Error: The following path exceeds requirements by 0.077ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SDRAM_CTRL_INST/sdram_fsm_st_4 (from sys_clk_sig_c +) Destination: FF Data in SDRAM_CTRL_INST_sdram_a_regio_0 (to sys_clk_sig_c +) Delay: 7.782ns (36.8% logic, 63.2% route), 6 logic levels. Constraint Details: 7.782ns physical path delay SDRAM_CTRL_INST/SLICE_208 to sdram_a_0_MGIOL exceeds 7.692ns delay constraint less -0.146ns skew and 0.133ns DO_SET requirement (totaling 7.705ns) by 0.077ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R4C18D.CLK to R4C18D.Q0 SDRAM_CTRL_INST/SLICE_208 (from sys_clk_sig_c) ROUTE 28 0.921 R4C18D.Q0 to R5C18D.B1 SDRAM_CTRL_INST/sdram_fsm_st_4 CTOF_DEL --- 0.449 R5C18D.B1 to R5C18D.F1 SLICE_205 ROUTE 2 0.274 R5C18D.F1 to R5C18C.D1 SDRAM_CTRL_INST/sdram_a_reg_9_sn_N_8 CTOOFX_DEL --- 0.661 R5C18C.D1 to R5C18C.OFX0 SDRAM_CTRL_INST/sdram_fsm_st_RNIU0CJ1_3/SLICE_578 ROUTE 1 0.859 R5C18C.OFX0 to R5C17A.A1 SDRAM_CTRL_INST/sdram_a_reg_9_sn_N_11 CTOF_DEL --- 0.449 R5C17A.A1 to R5C17A.F1 SLICE_607 ROUTE 11 0.865 R5C17A.F1 to R4C16C.D0 SDRAM_CTRL_INST/sdram_a_reg_9_sn_N_15 CTOF_DEL --- 0.449 R4C16C.D0 to R4C16C.F0 SLICE_595 ROUTE 4 0.905 R4C16C.F0 to R7C16D.D1 SDRAM_CTRL_INST/sdram_a_reg_9_sm0_i CTOF_DEL --- 0.449 R7C16D.D1 to R7C16D.F1 SLICE_611 ROUTE 1 1.097 R7C16D.F1 to IOL_R9D.OPOS SDRAM_CTRL_INST_SDRAM_FSM_PROC_sdram_a_reg_9_0_i_0 (to sys_clk_sig_c) -------- 7.782 (36.8% logic, 63.2% route), 6 logic levels. Clock Skew Details: Source Clock: Delay Connection 1.479ns LPLL.CLKOP to R4C18D.CLK Destination Clock Path: Destination Clock: Delay Connection 1.625ns LPLL.CLKOP to IOL_R9D.CLK Error: The following path exceeds requirements by 0.015ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SDRAM_CTRL_INST/sdram_fsm_st_4 (from sys_clk_sig_c +) Destination: FF Data in SDRAM_CTRL_INST_sdram_a_regio_1 (to sys_clk_sig_c +) Delay: 7.720ns (37.1% logic, 62.9% route), 6 logic levels. Constraint Details: 7.720ns physical path delay SDRAM_CTRL_INST/SLICE_208 to sdram_a_1_MGIOL exceeds 7.692ns delay constraint less -0.146ns skew and 0.133ns DO_SET requirement (totaling 7.705ns) by 0.015ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R4C18D.CLK to R4C18D.Q0 SDRAM_CTRL_INST/SLICE_208 (from sys_clk_sig_c) ROUTE 28 0.921 R4C18D.Q0 to R5C18D.B1 SDRAM_CTRL_INST/sdram_fsm_st_4 CTOF_DEL --- 0.449 R5C18D.B1 to R5C18D.F1 SLICE_205 ROUTE 2 0.274 R5C18D.F1 to R5C18C.D1 SDRAM_CTRL_INST/sdram_a_reg_9_sn_N_8 CTOOFX_DEL --- 0.661 R5C18C.D1 to R5C18C.OFX0 SDRAM_CTRL_INST/sdram_fsm_st_RNIU0CJ1_3/SLICE_578 ROUTE 1 0.859 R5C18C.OFX0 to R5C17A.A1 SDRAM_CTRL_INST/sdram_a_reg_9_sn_N_11 CTOF_DEL --- 0.449 R5C17A.A1 to R5C17A.F1 SLICE_607 ROUTE 11 0.865 R5C17A.F1 to R4C16C.D0 SDRAM_CTRL_INST/sdram_a_reg_9_sn_N_15 CTOF_DEL --- 0.449 R4C16C.D0 to R4C16C.F0 SLICE_595 ROUTE 4 0.408 R4C16C.F0 to R4C16C.C1 SDRAM_CTRL_INST/sdram_a_reg_9_sm0_i CTOF_DEL --- 0.449 R4C16C.C1 to R4C16C.F1 SLICE_595 ROUTE 1 1.532 R4C16C.F1 to IOL_R9C.OPOS SDRAM_CTRL_INST_SDRAM_FSM_PROC_sdram_a_reg_9_0_i_1 (to sys_clk_sig_c) -------- 7.720 (37.1% logic, 62.9% route), 6 logic levels. Clock Skew Details: Source Clock: Delay Connection 1.479ns LPLL.CLKOP to R4C18D.CLK Destination Clock Path: Destination Clock: Delay Connection 1.625ns LPLL.CLKOP to IOL_R9C.CLK Passed: The following path meets requirements by 0.036ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MONSTER_MANAGER_INST/fifo_rd_req (from sys_clk_sig_c +) Destination: FF Data in PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/FF_1 (to sys_clk_sig_c +) Delay: 7.510ns (33.7% logic, 66.3% route), 7 logic levels. Constraint Details: 7.510ns physical path delay MONSTER_MANAGER_INST/SLICE_341 to SLICE_58 meets 7.692ns delay constraint less 0.000ns skew and 0.146ns DIN_SET requirement (totaling 7.546ns) by 0.036ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R9C9A.CLK to R9C9A.Q0 MONSTER_MANAGER_INST/SLICE_341 (from sys_clk_sig_c) ROUTE 2 1.268 R9C9A.Q0 to R10C7B.B0 fifo_rd_req_sig CTOF_DEL --- 0.449 R10C7B.B0 to R10C7B.F0 PIXEL_ADDR_DATA_FIFO_INST/SLICE_662 ROUTE 15 3.713 R10C7B.F0 to R9C15A.B1 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/rden_i C1TOFCO_DE --- 0.752 R9C15A.B1 to R9C15A.FCO SLICE_57 ROUTE 1 0.000 R9C15A.FCO to R9C15B.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/cmp_ci FCITOFCO_D --- 0.143 R9C15B.FCI to R9C15B.FCO SLICE_61 ROUTE 1 0.000 R9C15B.FCO to R9C15C.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/co0_3 FCITOFCO_D --- 0.143 R9C15C.FCI to R9C15C.FCO SLICE_60 ROUTE 1 0.000 R9C15C.FCO to R9C15D.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/co1_3 FCITOFCO_D --- 0.143 R9C15D.FCI to R9C15D.FCO SLICE_59 ROUTE 1 0.000 R9C15D.FCO to R9C16A.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/empty_d_c FCITOF0_DE --- 0.495 R9C16A.FCI to R9C16A.F0 SLICE_58 ROUTE 1 0.000 R9C16A.F0 to R9C16A.DI0 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/empty_d (to sys_clk_sig_c) -------- 7.510 (33.7% logic, 66.3% route), 7 logic levels. Clock Skew Details: Source Clock: Delay Connection 1.479ns LPLL.CLKOP to R9C9A.CLK Destination Clock : Delay Connection 1.479ns LPLL.CLKOP to R9C16A.CLK Passed: The following path meets requirements by 0.036ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MONSTER_MANAGER_INST/fifo_rd_req (from sys_clk_sig_c +) Destination: FF Data in PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/FF_1 (to sys_clk_sig_c +) Delay: 7.510ns (33.7% logic, 66.3% route), 7 logic levels. Constraint Details: 7.510ns physical path delay MONSTER_MANAGER_INST/SLICE_341 to SLICE_72 meets 7.692ns delay constraint less 0.000ns skew and 0.146ns DIN_SET requirement (totaling 7.546ns) by 0.036ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R9C9A.CLK to R9C9A.Q0 MONSTER_MANAGER_INST/SLICE_341 (from sys_clk_sig_c) ROUTE 2 1.268 R9C9A.Q0 to R10C7B.B1 fifo_rd_req_sig CTOF_DEL --- 0.449 R10C7B.B1 to R10C7B.F1 PIXEL_ADDR_DATA_FIFO_INST/SLICE_662 ROUTE 18 3.713 R10C7B.F1 to R9C11A.B1 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/rden_i C1TOFCO_DE --- 0.752 R9C11A.B1 to R9C11A.FCO SLICE_71 ROUTE 1 0.000 R9C11A.FCO to R9C11B.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/cmp_ci FCITOFCO_D --- 0.143 R9C11B.FCI to R9C11B.FCO SLICE_63 ROUTE 1 0.000 R9C11B.FCO to R9C11C.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/co0_2 FCITOFCO_D --- 0.143 R9C11C.FCI to R9C11C.FCO SLICE_74 ROUTE 1 0.000 R9C11C.FCO to R9C11D.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/co1_2 FCITOFCO_D --- 0.143 R9C11D.FCI to R9C11D.FCO SLICE_73 ROUTE 1 0.000 R9C11D.FCO to R9C12A.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/empty_d_c FCITOF0_DE --- 0.495 R9C12A.FCI to R9C12A.F0 SLICE_72 ROUTE 1 0.000 R9C12A.F0 to R9C12A.DI0 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/empty_d (to sys_clk_sig_c) -------- 7.510 (33.7% logic, 66.3% route), 7 logic levels. Clock Skew Details: Source Clock: Delay Connection 1.479ns LPLL.CLKOP to R9C9A.CLK Destination Clock : Delay Connection 1.479ns LPLL.CLKOP to R9C12A.CLK Passed: The following path meets requirements by 0.062ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MONSTER_MANAGER_INST/fifo_rd_req (from sys_clk_sig_c +) Destination: FF Data in PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/FF_1 (to sys_clk_sig_c +) Delay: 7.484ns (33.8% logic, 66.2% route), 7 logic levels. Constraint Details: 7.484ns physical path delay MONSTER_MANAGER_INST/SLICE_341 to SLICE_58 meets 7.692ns delay constraint less 0.000ns skew and 0.146ns DIN_SET requirement (totaling 7.546ns) by 0.062ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R9C9A.CLK to R9C9A.Q0 MONSTER_MANAGER_INST/SLICE_341 (from sys_clk_sig_c) ROUTE 2 1.268 R9C9A.Q0 to R10C7B.B0 fifo_rd_req_sig CTOF_DEL --- 0.449 R10C7B.B0 to R10C7B.F0 PIXEL_ADDR_DATA_FIFO_INST/SLICE_662 ROUTE 15 3.687 R10C7B.F0 to R9C15A.A1 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/rden_i C1TOFCO_DE --- 0.752 R9C15A.A1 to R9C15A.FCO SLICE_57 ROUTE 1 0.000 R9C15A.FCO to R9C15B.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/cmp_ci FCITOFCO_D --- 0.143 R9C15B.FCI to R9C15B.FCO SLICE_61 ROUTE 1 0.000 R9C15B.FCO to R9C15C.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/co0_3 FCITOFCO_D --- 0.143 R9C15C.FCI to R9C15C.FCO SLICE_60 ROUTE 1 0.000 R9C15C.FCO to R9C15D.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/co1_3 FCITOFCO_D --- 0.143 R9C15D.FCI to R9C15D.FCO SLICE_59 ROUTE 1 0.000 R9C15D.FCO to R9C16A.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/empty_d_c FCITOF0_DE --- 0.495 R9C16A.FCI to R9C16A.F0 SLICE_58 ROUTE 1 0.000 R9C16A.F0 to R9C16A.DI0 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIFO_INST/empty_d (to sys_clk_sig_c) -------- 7.484 (33.8% logic, 66.2% route), 7 logic levels. Clock Skew Details: Source Clock: Delay Connection 1.479ns LPLL.CLKOP to R9C9A.CLK Destination Clock : Delay Connection 1.479ns LPLL.CLKOP to R9C16A.CLK Passed: The following path meets requirements by 0.062ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q MONSTER_MANAGER_INST/fifo_rd_req (from sys_clk_sig_c +) Destination: FF Data in PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/FF_1 (to sys_clk_sig_c +) Delay: 7.484ns (33.8% logic, 66.2% route), 7 logic levels. Constraint Details: 7.484ns physical path delay MONSTER_MANAGER_INST/SLICE_341 to SLICE_72 meets 7.692ns delay constraint less 0.000ns skew and 0.146ns DIN_SET requirement (totaling 7.546ns) by 0.062ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R9C9A.CLK to R9C9A.Q0 MONSTER_MANAGER_INST/SLICE_341 (from sys_clk_sig_c) ROUTE 2 1.268 R9C9A.Q0 to R10C7B.B1 fifo_rd_req_sig CTOF_DEL --- 0.449 R10C7B.B1 to R10C7B.F1 PIXEL_ADDR_DATA_FIFO_INST/SLICE_662 ROUTE 18 3.687 R10C7B.F1 to R9C11A.A1 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/rden_i C1TOFCO_DE --- 0.752 R9C11A.A1 to R9C11A.FCO SLICE_71 ROUTE 1 0.000 R9C11A.FCO to R9C11B.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/cmp_ci FCITOFCO_D --- 0.143 R9C11B.FCI to R9C11B.FCO SLICE_63 ROUTE 1 0.000 R9C11B.FCO to R9C11C.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/co0_2 FCITOFCO_D --- 0.143 R9C11C.FCI to R9C11C.FCO SLICE_74 ROUTE 1 0.000 R9C11C.FCO to R9C11D.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/co1_2 FCITOFCO_D --- 0.143 R9C11D.FCI to R9C11D.FCO SLICE_73 ROUTE 1 0.000 R9C11D.FCO to R9C12A.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/empty_d_c FCITOF0_DE --- 0.495 R9C12A.FCI to R9C12A.F0 SLICE_72 ROUTE 1 0.000 R9C12A.F0 to R9C12A.DI0 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/empty_d (to sys_clk_sig_c) -------- 7.484 (33.8% logic, 66.2% route), 7 logic levels. Clock Skew Details: Source Clock: Delay Connection 1.479ns LPLL.CLKOP to R9C9A.CLK Destination Clock : Delay Connection 1.479ns LPLL.CLKOP to R9C12A.CLK Passed: The following path meets requirements by 0.068ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/FF_1 (from sys_clk_sig_c +) Destination: FF Data in PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/FF_1 (to sys_clk_sig_c +) Delay: 7.478ns (33.8% logic, 66.2% route), 7 logic levels. Constraint Details: 7.478ns physical path delay SLICE_72 to SLICE_72 meets 7.692ns delay constraint less 0.000ns skew and 0.146ns DIN_SET requirement (totaling 7.546ns) by 0.068ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R9C12A.CLK to R9C12A.Q0 SLICE_72 (from sys_clk_sig_c) ROUTE 1 1.236 R9C12A.Q0 to R10C7B.D1 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/FF_1_Q CTOF_DEL --- 0.449 R10C7B.D1 to R10C7B.F1 PIXEL_ADDR_DATA_FIFO_INST/SLICE_662 ROUTE 18 3.713 R10C7B.F1 to R9C11A.B1 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/rden_i C1TOFCO_DE --- 0.752 R9C11A.B1 to R9C11A.FCO SLICE_71 ROUTE 1 0.000 R9C11A.FCO to R9C11B.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/cmp_ci FCITOFCO_D --- 0.143 R9C11B.FCI to R9C11B.FCO SLICE_63 ROUTE 1 0.000 R9C11B.FCO to R9C11C.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/co0_2 FCITOFCO_D --- 0.143 R9C11C.FCI to R9C11C.FCO SLICE_74 ROUTE 1 0.000 R9C11C.FCO to R9C11D.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/co1_2 FCITOFCO_D --- 0.143 R9C11D.FCI to R9C11D.FCO SLICE_73 ROUTE 1 0.000 R9C11D.FCO to R9C12A.FCI PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/empty_d_c FCITOF0_DE --- 0.495 R9C12A.FCI to R9C12A.F0 SLICE_72 ROUTE 1 0.000 R9C12A.F0 to R9C12A.DI0 PIXEL_ADDR_DATA_FIFO_INST/PIXEL_ADDR_FIFO_INST/empty_d (to sys_clk_sig_c) -------- 7.478 (33.8% logic, 66.2% route), 7 logic levels. Clock Skew Details: Source Clock: Delay Connection 1.479ns LPLL.CLKOP to R9C12A.CLK Destination Clock : Delay Connection 1.479ns LPLL.CLKOP to R9C12A.CLK Passed: The following path meets requirements by 0.087ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SDRAM_CTRL_INST/sdram_fsm_st_1 (from sys_clk_sig_c +) Destination: FF Data in SDRAM_CTRL_INST_sdram_a_regio_0 (to sys_clk_sig_c +) Delay: 7.618ns (37.6% logic, 62.4% route), 6 logic levels. Constraint Details: 7.618ns physical path delay SDRAM_CTRL_INST/SLICE_206 to sdram_a_0_MGIOL meets 7.692ns delay constraint less -0.146ns skew and 0.133ns DO_SET requirement (totaling 7.705ns) by 0.087ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R5C16A.CLK to R5C16A.Q0 SDRAM_CTRL_INST/SLICE_206 (from sys_clk_sig_c) ROUTE 44 0.757 R5C16A.Q0 to R5C18D.C1 SDRAM_CTRL_INST/sdram_fsm_st_1 CTOF_DEL --- 0.449 R5C18D.C1 to R5C18D.F1 SLICE_205 ROUTE 2 0.274 R5C18D.F1 to R5C18C.D1 SDRAM_CTRL_INST/sdram_a_reg_9_sn_N_8 CTOOFX_DEL --- 0.661 R5C18C.D1 to R5C18C.OFX0 SDRAM_CTRL_INST/sdram_fsm_st_RNIU0CJ1_3/SLICE_578 ROUTE 1 0.859 R5C18C.OFX0 to R5C17A.A1 SDRAM_CTRL_INST/sdram_a_reg_9_sn_N_11 CTOF_DEL --- 0.449 R5C17A.A1 to R5C17A.F1 SLICE_607 ROUTE 11 0.865 R5C17A.F1 to R4C16C.D0 SDRAM_CTRL_INST/sdram_a_reg_9_sn_N_15 CTOF_DEL --- 0.449 R4C16C.D0 to R4C16C.F0 SLICE_595 ROUTE 4 0.905 R4C16C.F0 to R7C16D.D1 SDRAM_CTRL_INST/sdram_a_reg_9_sm0_i CTOF_DEL --- 0.449 R7C16D.D1 to R7C16D.F1 SLICE_611 ROUTE 1 1.097 R7C16D.F1 to IOL_R9D.OPOS SDRAM_CTRL_INST_SDRAM_FSM_PROC_sdram_a_reg_9_0_i_0 (to sys_clk_sig_c) -------- 7.618 (37.6% logic, 62.4% route), 6 logic levels. Clock Skew Details: Source Clock: Delay Connection 1.479ns LPLL.CLKOP to R5C16A.CLK Destination Clock : Delay Connection 1.625ns LPLL.CLKOP to IOL_R9D.CLK Warning: 126.326MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY NET "TX_LVDS_71_INST/eclko" 130.000000 MHz ; 1 item scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 4.942ns The internal maximum frequency of the following component is 363.636 MHz Logical Details: Cell type Pin name Component name Destination: TIOLOGIC ECLK tft_data3_MGIOL Delay: 2.750ns -- based on Minimum Pulse Width Passed: The following path meets requirements by 6.317ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TX_LVDS_71_INST/Inst4_ODDRX71A3 (from TX_LVDS_71_INST/eclko +) Delay: 1.375ns (100.0% logic, 0.0% route), 1 logic levels. Constraint Details: 1.375ns physical path delay tft_data3_MGIOL to tft_data3_MGIOL meets 7.692ns delay constraint by 6.317ns Physical Path Details: Name Fanout Delay (ns) Site Resource COMP --- 1.375 IOL_T9A.ECLK to IOL_T9A.ECLK tft_data3_MGIOL (from TX_LVDS_71_INST/eclko) -------- 1.375 (100.0% logic, 0.0% route), 1 logic levels. Report: 363.636MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY NET "TX_LVDS_71_INST/sclk_sig" 38.000000 MHz ; 19 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 25.170ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_TIMING_CTRL_INST/tft_test_green_4 (from tft_clk_sig_c +) Destination: FF Data in TX_LVDS_71_INST/Inst4_ODDRX71A1 (to TX_LVDS_71_INST/sclk_sig +) Delay: 2.050ns (19.7% logic, 80.3% route), 1 logic levels. Constraint Details: 2.050ns physical path delay TFT_TIMING_CTRL_INST/SLICE_712 to tft_data1_MGIOL meets (delay constraint based on source clock period of 26.923ns and destination clock period of 26.315ns) 26.315ns delay constraint less -1.067ns skew and 0.000ns feedback compensation and 0.162ns DO_SET requirement (totaling 27.220ns) by 25.170ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R3C15C.CLK to R3C15C.Q1 TFT_TIMING_CTRL_INST/SLICE_712 (from tft_clk_sig_c) ROUTE 1 1.646 R3C15C.Q1 to IOL_T16A.TXD5 tft_green_sig_4 (to TX_LVDS_71_INST/sclk_sig) -------- 2.050 (19.7% logic, 80.3% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 1.479 LPLL.CLKOS3 to R3C15C.CLK tft_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.488 LPLL.CLKOP to *LKSYNC0.ECLKI sys_clk_sig_c C2OUT_DEL --- 0.000 *LKSYNC0.ECLKI to *LKSYNC0.ECLKO TX_LVDS_71_INST/Inst2_ECLKSYNCA ROUTE 6 0.000 *LKSYNC0.ECLKO to TCLKDIV0.CLKI TX_LVDS_71_INST/eclko CLKOUT_DEL --- 0.356 TCLKDIV0.CLKI to TCLKDIV0.CDIVX TX_LVDS_71_INST/Inst3_CLKDIVC ROUTE 5 1.702 TCLKDIV0.CDIVX to IOL_T16A.CLK TX_LVDS_71_INST/sclk_sig -------- 4.333 (34.3% logic, 65.7% route), 4 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 25.170ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_TIMING_CTRL_INST/tft_test_green_3 (from tft_clk_sig_c +) Destination: FF Data in TX_LVDS_71_INST/Inst4_ODDRX71A1 (to TX_LVDS_71_INST/sclk_sig +) Delay: 2.050ns (19.7% logic, 80.3% route), 1 logic levels. Constraint Details: 2.050ns physical path delay TFT_TIMING_CTRL_INST/SLICE_711 to tft_data1_MGIOL meets (delay constraint based on source clock period of 26.923ns and destination clock period of 26.315ns) 26.315ns delay constraint less -1.067ns skew and 0.000ns feedback compensation and 0.162ns DO_SET requirement (totaling 27.220ns) by 25.170ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R2C16D.CLK to R2C16D.Q0 TFT_TIMING_CTRL_INST/SLICE_711 (from tft_clk_sig_c) ROUTE 1 1.646 R2C16D.Q0 to IOL_T16A.TXD6 tft_green_sig_3 (to TX_LVDS_71_INST/sclk_sig) -------- 2.050 (19.7% logic, 80.3% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 1.479 LPLL.CLKOS3 to R2C16D.CLK tft_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.488 LPLL.CLKOP to *LKSYNC0.ECLKI sys_clk_sig_c C2OUT_DEL --- 0.000 *LKSYNC0.ECLKI to *LKSYNC0.ECLKO TX_LVDS_71_INST/Inst2_ECLKSYNCA ROUTE 6 0.000 *LKSYNC0.ECLKO to TCLKDIV0.CLKI TX_LVDS_71_INST/eclko CLKOUT_DEL --- 0.356 TCLKDIV0.CLKI to TCLKDIV0.CDIVX TX_LVDS_71_INST/Inst3_CLKDIVC ROUTE 5 1.702 TCLKDIV0.CDIVX to IOL_T16A.CLK TX_LVDS_71_INST/sclk_sig -------- 4.333 (34.3% logic, 65.7% route), 4 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 25.427ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_TIMING_CTRL_INST/tft_test_blue_0 (from tft_clk_sig_c +) Destination: FF Data in TX_LVDS_71_INST/Inst4_ODDRX71A1 (to TX_LVDS_71_INST/sclk_sig +) Delay: 1.793ns (22.5% logic, 77.5% route), 1 logic levels. Constraint Details: 1.793ns physical path delay TFT_TIMING_CTRL_INST/SLICE_395 to tft_data1_MGIOL meets (delay constraint based on source clock period of 26.923ns and destination clock period of 26.315ns) 26.315ns delay constraint less -1.067ns skew and 0.000ns feedback compensation and 0.162ns DO_SET requirement (totaling 27.220ns) by 25.427ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R2C17A.CLK to R2C17A.Q0 TFT_TIMING_CTRL_INST/SLICE_395 (from tft_clk_sig_c) ROUTE 2 1.389 R2C17A.Q0 to IOL_T16A.TXD1 tft_red_sig_1 (to TX_LVDS_71_INST/sclk_sig) -------- 1.793 (22.5% logic, 77.5% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 1.479 LPLL.CLKOS3 to R2C17A.CLK tft_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.488 LPLL.CLKOP to *LKSYNC0.ECLKI sys_clk_sig_c C2OUT_DEL --- 0.000 *LKSYNC0.ECLKI to *LKSYNC0.ECLKO TX_LVDS_71_INST/Inst2_ECLKSYNCA ROUTE 6 0.000 *LKSYNC0.ECLKO to TCLKDIV0.CLKI TX_LVDS_71_INST/eclko CLKOUT_DEL --- 0.356 TCLKDIV0.CLKI to TCLKDIV0.CDIVX TX_LVDS_71_INST/Inst3_CLKDIVC ROUTE 5 1.702 TCLKDIV0.CDIVX to IOL_T16A.CLK TX_LVDS_71_INST/sclk_sig -------- 4.333 (34.3% logic, 65.7% route), 4 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 25.434ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_TIMING_CTRL_INST/tft_test_green_6 (from tft_clk_sig_c +) Destination: FF Data in TX_LVDS_71_INST/Inst4_ODDRX71A1 (to TX_LVDS_71_INST/sclk_sig +) Delay: 1.786ns (22.6% logic, 77.4% route), 1 logic levels. Constraint Details: 1.786ns physical path delay TFT_TIMING_CTRL_INST/SLICE_713 to tft_data1_MGIOL meets (delay constraint based on source clock period of 26.923ns and destination clock period of 26.315ns) 26.315ns delay constraint less -1.067ns skew and 0.000ns feedback compensation and 0.162ns DO_SET requirement (totaling 27.220ns) by 25.434ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R3C15B.CLK to R3C15B.Q1 TFT_TIMING_CTRL_INST/SLICE_713 (from tft_clk_sig_c) ROUTE 1 1.382 R3C15B.Q1 to IOL_T16A.TXD3 tft_green_sig_6 (to TX_LVDS_71_INST/sclk_sig) -------- 1.786 (22.6% logic, 77.4% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 1.479 LPLL.CLKOS3 to R3C15B.CLK tft_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.488 LPLL.CLKOP to *LKSYNC0.ECLKI sys_clk_sig_c C2OUT_DEL --- 0.000 *LKSYNC0.ECLKI to *LKSYNC0.ECLKO TX_LVDS_71_INST/Inst2_ECLKSYNCA ROUTE 6 0.000 *LKSYNC0.ECLKO to TCLKDIV0.CLKI TX_LVDS_71_INST/eclko CLKOUT_DEL --- 0.356 TCLKDIV0.CLKI to TCLKDIV0.CDIVX TX_LVDS_71_INST/Inst3_CLKDIVC ROUTE 5 1.702 TCLKDIV0.CDIVX to IOL_T16A.CLK TX_LVDS_71_INST/sclk_sig -------- 4.333 (34.3% logic, 65.7% route), 4 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 25.546ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_TIMING_CTRL_INST/tft_test_red_7 (from tft_clk_sig_c +) Destination: FF Data in TX_LVDS_71_INST/Inst4_ODDRX71A0 (to TX_LVDS_71_INST/sclk_sig +) Delay: 1.674ns (24.1% logic, 75.9% route), 1 logic levels. Constraint Details: 1.674ns physical path delay SLICE_555 to tft_data0_MGIOL meets (delay constraint based on source clock period of 26.923ns and destination clock period of 26.315ns) 26.315ns delay constraint less -1.067ns skew and 0.000ns feedback compensation and 0.162ns DO_SET requirement (totaling 27.220ns) by 25.546ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R2C16C.CLK to R2C16C.Q0 SLICE_555 (from tft_clk_sig_c) ROUTE 1 1.270 R2C16C.Q0 to IOL_T17A.TXD1 tft_red_sig_7 (to TX_LVDS_71_INST/sclk_sig) -------- 1.674 (24.1% logic, 75.9% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 1.479 LPLL.CLKOS3 to R2C16C.CLK tft_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.488 LPLL.CLKOP to *LKSYNC0.ECLKI sys_clk_sig_c C2OUT_DEL --- 0.000 *LKSYNC0.ECLKI to *LKSYNC0.ECLKO TX_LVDS_71_INST/Inst2_ECLKSYNCA ROUTE 6 0.000 *LKSYNC0.ECLKO to TCLKDIV0.CLKI TX_LVDS_71_INST/eclko CLKOUT_DEL --- 0.356 TCLKDIV0.CLKI to TCLKDIV0.CDIVX TX_LVDS_71_INST/Inst3_CLKDIVC ROUTE 5 1.702 TCLKDIV0.CDIVX to IOL_T17A.CLK TX_LVDS_71_INST/sclk_sig -------- 4.333 (34.3% logic, 65.7% route), 4 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 25.546ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_TIMING_CTRL_INST/tft_test_green_5 (from tft_clk_sig_c +) Destination: FF Data in TX_LVDS_71_INST/Inst4_ODDRX71A1 (to TX_LVDS_71_INST/sclk_sig +) Delay: 1.674ns (24.1% logic, 75.9% route), 1 logic levels. Constraint Details: 1.674ns physical path delay TFT_TIMING_CTRL_INST/SLICE_712 to tft_data1_MGIOL meets (delay constraint based on source clock period of 26.923ns and destination clock period of 26.315ns) 26.315ns delay constraint less -1.067ns skew and 0.000ns feedback compensation and 0.162ns DO_SET requirement (totaling 27.220ns) by 25.546ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R3C15C.CLK to R3C15C.Q0 TFT_TIMING_CTRL_INST/SLICE_712 (from tft_clk_sig_c) ROUTE 1 1.270 R3C15C.Q0 to IOL_T16A.TXD4 tft_green_sig_5 (to TX_LVDS_71_INST/sclk_sig) -------- 1.674 (24.1% logic, 75.9% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 1.479 LPLL.CLKOS3 to R3C15C.CLK tft_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.488 LPLL.CLKOP to *LKSYNC0.ECLKI sys_clk_sig_c C2OUT_DEL --- 0.000 *LKSYNC0.ECLKI to *LKSYNC0.ECLKO TX_LVDS_71_INST/Inst2_ECLKSYNCA ROUTE 6 0.000 *LKSYNC0.ECLKO to TCLKDIV0.CLKI TX_LVDS_71_INST/eclko CLKOUT_DEL --- 0.356 TCLKDIV0.CLKI to TCLKDIV0.CDIVX TX_LVDS_71_INST/Inst3_CLKDIVC ROUTE 5 1.702 TCLKDIV0.CDIVX to IOL_T16A.CLK TX_LVDS_71_INST/sclk_sig -------- 4.333 (34.3% logic, 65.7% route), 4 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 25.546ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_TIMING_CTRL_INST/tft_test_green_2 (from tft_clk_sig_c +) Destination: FF Data in TX_LVDS_71_INST/Inst4_ODDRX71A0 (to TX_LVDS_71_INST/sclk_sig +) Delay: 1.674ns (24.1% logic, 75.9% route), 1 logic levels. Constraint Details: 1.674ns physical path delay TFT_TIMING_CTRL_INST/SLICE_711 to tft_data0_MGIOL meets (delay constraint based on source clock period of 26.923ns and destination clock period of 26.315ns) 26.315ns delay constraint less -1.067ns skew and 0.000ns feedback compensation and 0.162ns DO_SET requirement (totaling 27.220ns) by 25.546ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R2C16D.CLK to R2C16D.Q1 TFT_TIMING_CTRL_INST/SLICE_711 (from tft_clk_sig_c) ROUTE 1 1.270 R2C16D.Q1 to IOL_T17A.TXD0 tft_green_sig_2 (to TX_LVDS_71_INST/sclk_sig) -------- 1.674 (24.1% logic, 75.9% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 1.479 LPLL.CLKOS3 to R2C16D.CLK tft_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.488 LPLL.CLKOP to *LKSYNC0.ECLKI sys_clk_sig_c C2OUT_DEL --- 0.000 *LKSYNC0.ECLKI to *LKSYNC0.ECLKO TX_LVDS_71_INST/Inst2_ECLKSYNCA ROUTE 6 0.000 *LKSYNC0.ECLKO to TCLKDIV0.CLKI TX_LVDS_71_INST/eclko CLKOUT_DEL --- 0.356 TCLKDIV0.CLKI to TCLKDIV0.CDIVX TX_LVDS_71_INST/Inst3_CLKDIVC ROUTE 5 1.702 TCLKDIV0.CDIVX to IOL_T17A.CLK TX_LVDS_71_INST/sclk_sig -------- 4.333 (34.3% logic, 65.7% route), 4 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 25.546ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_TIMING_CTRL_INST/tft_test_green_7 (from tft_clk_sig_c +) Destination: FF Data in TX_LVDS_71_INST/Inst4_ODDRX71A1 (to TX_LVDS_71_INST/sclk_sig +) Delay: 1.674ns (24.1% logic, 75.9% route), 1 logic levels. Constraint Details: 1.674ns physical path delay TFT_TIMING_CTRL_INST/SLICE_713 to tft_data1_MGIOL meets (delay constraint based on source clock period of 26.923ns and destination clock period of 26.315ns) 26.315ns delay constraint less -1.067ns skew and 0.000ns feedback compensation and 0.162ns DO_SET requirement (totaling 27.220ns) by 25.546ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R3C15B.CLK to R3C15B.Q0 TFT_TIMING_CTRL_INST/SLICE_713 (from tft_clk_sig_c) ROUTE 1 1.270 R3C15B.Q0 to IOL_T16A.TXD2 tft_green_sig_7 (to TX_LVDS_71_INST/sclk_sig) -------- 1.674 (24.1% logic, 75.9% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 1.479 LPLL.CLKOS3 to R3C15B.CLK tft_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.488 LPLL.CLKOP to *LKSYNC0.ECLKI sys_clk_sig_c C2OUT_DEL --- 0.000 *LKSYNC0.ECLKI to *LKSYNC0.ECLKO TX_LVDS_71_INST/Inst2_ECLKSYNCA ROUTE 6 0.000 *LKSYNC0.ECLKO to TCLKDIV0.CLKI TX_LVDS_71_INST/eclko CLKOUT_DEL --- 0.356 TCLKDIV0.CLKI to TCLKDIV0.CDIVX TX_LVDS_71_INST/Inst3_CLKDIVC ROUTE 5 1.702 TCLKDIV0.CDIVX to IOL_T16A.CLK TX_LVDS_71_INST/sclk_sig -------- 4.333 (34.3% logic, 65.7% route), 4 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 25.803ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_TIMING_CTRL_INST/tft_test_blue_0 (from tft_clk_sig_c +) Destination: FF Data in TX_LVDS_71_INST/Inst4_ODDRX71A0 (to TX_LVDS_71_INST/sclk_sig +) Delay: 1.417ns (28.5% logic, 71.5% route), 1 logic levels. Constraint Details: 1.417ns physical path delay TFT_TIMING_CTRL_INST/SLICE_395 to tft_data0_MGIOL meets (delay constraint based on source clock period of 26.923ns and destination clock period of 26.315ns) 26.315ns delay constraint less -1.067ns skew and 0.000ns feedback compensation and 0.162ns DO_SET requirement (totaling 27.220ns) by 25.803ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R2C17A.CLK to R2C17A.Q0 TFT_TIMING_CTRL_INST/SLICE_395 (from tft_clk_sig_c) ROUTE 2 1.013 R2C17A.Q0 to IOL_T17A.TXD6 tft_red_sig_1 (to TX_LVDS_71_INST/sclk_sig) -------- 1.417 (28.5% logic, 71.5% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 1.479 LPLL.CLKOS3 to R2C17A.CLK tft_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.488 LPLL.CLKOP to *LKSYNC0.ECLKI sys_clk_sig_c C2OUT_DEL --- 0.000 *LKSYNC0.ECLKI to *LKSYNC0.ECLKO TX_LVDS_71_INST/Inst2_ECLKSYNCA ROUTE 6 0.000 *LKSYNC0.ECLKO to TCLKDIV0.CLKI TX_LVDS_71_INST/eclko CLKOUT_DEL --- 0.356 TCLKDIV0.CLKI to TCLKDIV0.CDIVX TX_LVDS_71_INST/Inst3_CLKDIVC ROUTE 5 1.702 TCLKDIV0.CDIVX to IOL_T17A.CLK TX_LVDS_71_INST/sclk_sig -------- 4.333 (34.3% logic, 65.7% route), 4 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 25.810ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q TFT_TIMING_CTRL_INST/tft_test_red_3 (from tft_clk_sig_c +) Destination: FF Data in TX_LVDS_71_INST/Inst4_ODDRX71A0 (to TX_LVDS_71_INST/sclk_sig +) Delay: 1.410ns (28.7% logic, 71.3% route), 1 logic levels. Constraint Details: 1.410ns physical path delay TFT_TIMING_CTRL_INST/SLICE_395 to tft_data0_MGIOL meets (delay constraint based on source clock period of 26.923ns and destination clock period of 26.315ns) 26.315ns delay constraint less -1.067ns skew and 0.000ns feedback compensation and 0.162ns DO_SET requirement (totaling 27.220ns) by 25.810ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R2C17A.CLK to R2C17A.Q1 TFT_TIMING_CTRL_INST/SLICE_395 (from tft_clk_sig_c) ROUTE 1 1.006 R2C17A.Q1 to IOL_T17A.TXD5 tft_red_sig_3 (to TX_LVDS_71_INST/sclk_sig) -------- 1.410 (28.7% logic, 71.3% route), 1 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 1.479 LPLL.CLKOS3 to R2C17A.CLK tft_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 0.488 LPLL.CLKOP to *LKSYNC0.ECLKI sys_clk_sig_c C2OUT_DEL --- 0.000 *LKSYNC0.ECLKI to *LKSYNC0.ECLKO TX_LVDS_71_INST/Inst2_ECLKSYNCA ROUTE 6 0.000 *LKSYNC0.ECLKO to TCLKDIV0.CLKI TX_LVDS_71_INST/eclko CLKOUT_DEL --- 0.356 TCLKDIV0.CLKI to TCLKDIV0.CDIVX TX_LVDS_71_INST/Inst3_CLKDIVC ROUTE 5 1.702 TCLKDIV0.CDIVX to IOL_T17A.CLK TX_LVDS_71_INST/sclk_sig -------- 4.333 (34.3% logic, 65.7% route), 4 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Report: 873.362MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY NET "tft_clk_sig_c" 37.142857 MHz ; 30 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 0.061ns (weighted slack = 0.427ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SDRAM_CTRL_INST/sdram_ready_reg (from sys_clk_sig_c +) Destination: FF Data in SDRAM_TEST_GENERATOR_INST/row_cnt_8 (to tft_clk_sig_c +) FF SDRAM_TEST_GENERATOR_INST/row_cnt_7 Delay: 3.165ns (27.0% logic, 73.0% route), 2 logic levels. Constraint Details: 3.165ns physical path delay SLICE_387 to SDRAM_TEST_GENERATOR_INST/SLICE_86 meets (delay constraint based on source clock period of 7.692ns and destination clock period of 26.923ns) 3.846ns delay constraint less 0.000ns skew and 0.000ns feedback compensation and 0.620ns LSR_SET requirement (totaling 3.226ns) by 0.061ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R10C6C.CLK to R10C6C.Q0 SLICE_387 (from sys_clk_sig_c) ROUTE 5 0.542 R10C6C.Q0 to R10C6C.D1 sys_sdram_ready_sig CTOF_DEL --- 0.449 R10C6C.D1 to R10C6C.F1 SLICE_387 ROUTE 39 1.770 R10C6C.F1 to R5C9A.LSR SDRAM_TEST_GENERATOR_INST/cnt_rst_0_i (to tft_clk_sig_c) -------- 3.165 (27.0% logic, 73.0% route), 2 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.479 LPLL.CLKOP to R10C6C.CLK sys_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 1.479 LPLL.CLKOS3 to R5C9A.CLK tft_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 0.061ns (weighted slack = 0.427ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SDRAM_CTRL_INST/sdram_ready_reg (from sys_clk_sig_c +) Destination: FF Data in SDRAM_TEST_GENERATOR_INST/row_cnt_9 (to tft_clk_sig_c +) FF SDRAM_TEST_GENERATOR_INST/row_cnt_6 Delay: 3.165ns (27.0% logic, 73.0% route), 2 logic levels. Constraint Details: 3.165ns physical path delay SLICE_387 to SDRAM_TEST_GENERATOR_INST/SLICE_252 meets (delay constraint based on source clock period of 7.692ns and destination clock period of 26.923ns) 3.846ns delay constraint less 0.000ns skew and 0.000ns feedback compensation and 0.620ns LSR_SET requirement (totaling 3.226ns) by 0.061ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R10C6C.CLK to R10C6C.Q0 SLICE_387 (from sys_clk_sig_c) ROUTE 5 0.542 R10C6C.Q0 to R10C6C.D1 sys_sdram_ready_sig CTOF_DEL --- 0.449 R10C6C.D1 to R10C6C.F1 SLICE_387 ROUTE 39 1.770 R10C6C.F1 to R5C9C.LSR SDRAM_TEST_GENERATOR_INST/cnt_rst_0_i (to tft_clk_sig_c) -------- 3.165 (27.0% logic, 73.0% route), 2 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.479 LPLL.CLKOP to R10C6C.CLK sys_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 1.479 LPLL.CLKOS3 to R5C9C.CLK tft_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 0.061ns (weighted slack = 0.427ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SDRAM_CTRL_INST/sdram_ready_reg (from sys_clk_sig_c +) Destination: FF Data in SDRAM_TEST_GENERATOR_INST/sdram_fifo_wr_add_12 (to tft_clk_sig_c +) FF SDRAM_TEST_GENERATOR_INST/row_cnt_3 Delay: 3.165ns (27.0% logic, 73.0% route), 2 logic levels. Constraint Details: 3.165ns physical path delay SLICE_387 to SDRAM_TEST_GENERATOR_INST/SLICE_88 meets (delay constraint based on source clock period of 7.692ns and destination clock period of 26.923ns) 3.846ns delay constraint less 0.000ns skew and 0.000ns feedback compensation and 0.620ns LSR_SET requirement (totaling 3.226ns) by 0.061ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R10C6C.CLK to R10C6C.Q0 SLICE_387 (from sys_clk_sig_c) ROUTE 5 0.542 R10C6C.Q0 to R10C6C.D1 sys_sdram_ready_sig CTOF_DEL --- 0.449 R10C6C.D1 to R10C6C.F1 SLICE_387 ROUTE 39 1.770 R10C6C.F1 to R5C8C.LSR SDRAM_TEST_GENERATOR_INST/cnt_rst_0_i (to tft_clk_sig_c) -------- 3.165 (27.0% logic, 73.0% route), 2 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.479 LPLL.CLKOP to R10C6C.CLK sys_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 1.479 LPLL.CLKOS3 to R5C8C.CLK tft_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 0.061ns (weighted slack = 0.427ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SDRAM_CTRL_INST/sdram_ready_reg (from sys_clk_sig_c +) Destination: FF Data in SDRAM_TEST_GENERATOR_INST/sdram_fifo_wr_add_13 (to tft_clk_sig_c +) FF SDRAM_TEST_GENERATOR_INST/row_cnt_5 Delay: 3.165ns (27.0% logic, 73.0% route), 2 logic levels. Constraint Details: 3.165ns physical path delay SLICE_387 to SDRAM_TEST_GENERATOR_INST/SLICE_87 meets (delay constraint based on source clock period of 7.692ns and destination clock period of 26.923ns) 3.846ns delay constraint less 0.000ns skew and 0.000ns feedback compensation and 0.620ns LSR_SET requirement (totaling 3.226ns) by 0.061ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R10C6C.CLK to R10C6C.Q0 SLICE_387 (from sys_clk_sig_c) ROUTE 5 0.542 R10C6C.Q0 to R10C6C.D1 sys_sdram_ready_sig CTOF_DEL --- 0.449 R10C6C.D1 to R10C6C.F1 SLICE_387 ROUTE 39 1.770 R10C6C.F1 to R5C8D.LSR SDRAM_TEST_GENERATOR_INST/cnt_rst_0_i (to tft_clk_sig_c) -------- 3.165 (27.0% logic, 73.0% route), 2 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.479 LPLL.CLKOP to R10C6C.CLK sys_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 1.479 LPLL.CLKOS3 to R5C8D.CLK tft_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 0.139ns (weighted slack = 0.973ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SDRAM_CTRL_INST/sdram_ready_reg (from sys_clk_sig_c +) Destination: FF Data in SDRAM_TEST_GENERATOR_INST/sdram_fifo_wr_add_8 (to tft_clk_sig_c +) FF SDRAM_TEST_GENERATOR_INST/sdram_fifo_wr_add_7 Delay: 3.087ns (27.6% logic, 72.4% route), 2 logic levels. Constraint Details: 3.087ns physical path delay SLICE_387 to SLICE_659 meets (delay constraint based on source clock period of 7.692ns and destination clock period of 26.923ns) 3.846ns delay constraint less 0.000ns skew and 0.000ns feedback compensation and 0.620ns LSR_SET requirement (totaling 3.226ns) by 0.139ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R10C6C.CLK to R10C6C.Q0 SLICE_387 (from sys_clk_sig_c) ROUTE 5 0.542 R10C6C.Q0 to R10C6C.D1 sys_sdram_ready_sig CTOF_DEL --- 0.449 R10C6C.D1 to R10C6C.F1 SLICE_387 ROUTE 39 1.692 R10C6C.F1 to R8C12D.LSR SDRAM_TEST_GENERATOR_INST/cnt_rst_0_i (to tft_clk_sig_c) -------- 3.087 (27.6% logic, 72.4% route), 2 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.479 LPLL.CLKOP to R10C6C.CLK sys_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 1.479 LPLL.CLKOS3 to R8C12D.CLK tft_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 0.173ns (weighted slack = 1.211ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SDRAM_CTRL_INST/sdram_ready_reg (from sys_clk_sig_c +) Destination: FF Data in SDRAM_TEST_GENERATOR_INST/sdram_fifo_wr_add_10 (to tft_clk_sig_c +) FF SDRAM_TEST_GENERATOR_INST/column_cnt_0 Delay: 3.053ns (27.9% logic, 72.1% route), 2 logic levels. Constraint Details: 3.053ns physical path delay SLICE_387 to SDRAM_TEST_GENERATOR_INST/SLICE_241 meets (delay constraint based on source clock period of 7.692ns and destination clock period of 26.923ns) 3.846ns delay constraint less 0.000ns skew and 0.000ns feedback compensation and 0.620ns LSR_SET requirement (totaling 3.226ns) by 0.173ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R10C6C.CLK to R10C6C.Q0 SLICE_387 (from sys_clk_sig_c) ROUTE 5 0.542 R10C6C.Q0 to R10C6C.D1 sys_sdram_ready_sig CTOF_DEL --- 0.449 R10C6C.D1 to R10C6C.F1 SLICE_387 ROUTE 39 1.658 R10C6C.F1 to R8C9D.LSR SDRAM_TEST_GENERATOR_INST/cnt_rst_0_i (to tft_clk_sig_c) -------- 3.053 (27.9% logic, 72.1% route), 2 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.479 LPLL.CLKOP to R10C6C.CLK sys_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 1.479 LPLL.CLKOS3 to R8C9D.CLK tft_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 0.417ns (weighted slack = 2.919ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SDRAM_CTRL_INST/sdram_ready_reg (from sys_clk_sig_c +) Destination: FF Data in SDRAM_TEST_GENERATOR_INST/column_cnt_8 (to tft_clk_sig_c +) FF SDRAM_TEST_GENERATOR_INST/column_cnt_5 Delay: 2.809ns (30.4% logic, 69.6% route), 2 logic levels. Constraint Details: 2.809ns physical path delay SLICE_387 to SDRAM_TEST_GENERATOR_INST/SLICE_242 meets (delay constraint based on source clock period of 7.692ns and destination clock period of 26.923ns) 3.846ns delay constraint less 0.000ns skew and 0.000ns feedback compensation and 0.620ns LSR_SET requirement (totaling 3.226ns) by 0.417ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R10C6C.CLK to R10C6C.Q0 SLICE_387 (from sys_clk_sig_c) ROUTE 5 0.542 R10C6C.Q0 to R10C6C.D1 sys_sdram_ready_sig CTOF_DEL --- 0.449 R10C6C.D1 to R10C6C.F1 SLICE_387 ROUTE 39 1.414 R10C6C.F1 to R4C8C.LSR SDRAM_TEST_GENERATOR_INST/cnt_rst_0_i (to tft_clk_sig_c) -------- 2.809 (30.4% logic, 69.6% route), 2 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.479 LPLL.CLKOP to R10C6C.CLK sys_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 1.479 LPLL.CLKOS3 to R4C8C.CLK tft_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 0.417ns (weighted slack = 2.919ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SDRAM_CTRL_INST/sdram_ready_reg (from sys_clk_sig_c +) Destination: FF Data in SDRAM_TEST_GENERATOR_INST/column_cnt_9 (to tft_clk_sig_c +) Delay: 2.809ns (30.4% logic, 69.6% route), 2 logic levels. Constraint Details: 2.809ns physical path delay SLICE_387 to SDRAM_TEST_GENERATOR_INST/SLICE_243 meets (delay constraint based on source clock period of 7.692ns and destination clock period of 26.923ns) 3.846ns delay constraint less 0.000ns skew and 0.000ns feedback compensation and 0.620ns LSRREC_SET requirement (totaling 3.226ns) by 0.417ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R10C6C.CLK to R10C6C.Q0 SLICE_387 (from sys_clk_sig_c) ROUTE 5 0.542 R10C6C.Q0 to R10C6C.D1 sys_sdram_ready_sig CTOF_DEL --- 0.449 R10C6C.D1 to R10C6C.F1 SLICE_387 ROUTE 39 1.414 R10C6C.F1 to R4C8D.LSR SDRAM_TEST_GENERATOR_INST/cnt_rst_0_i (to tft_clk_sig_c) -------- 2.809 (30.4% logic, 69.6% route), 2 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.479 LPLL.CLKOP to R10C6C.CLK sys_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 1.479 LPLL.CLKOS3 to R4C8D.CLK tft_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 0.417ns (weighted slack = 2.919ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SDRAM_CTRL_INST/sdram_ready_reg (from sys_clk_sig_c +) Destination: FF Data in SDRAM_TEST_GENERATOR_INST/column_cnt_7 (to tft_clk_sig_c +) Delay: 2.809ns (30.4% logic, 69.6% route), 2 logic levels. Constraint Details: 2.809ns physical path delay SLICE_387 to SDRAM_TEST_GENERATOR_INST/SLICE_92 meets (delay constraint based on source clock period of 7.692ns and destination clock period of 26.923ns) 3.846ns delay constraint less 0.000ns skew and 0.000ns feedback compensation and 0.620ns LSRREC_SET requirement (totaling 3.226ns) by 0.417ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R10C6C.CLK to R10C6C.Q0 SLICE_387 (from sys_clk_sig_c) ROUTE 5 0.542 R10C6C.Q0 to R10C6C.D1 sys_sdram_ready_sig CTOF_DEL --- 0.449 R10C6C.D1 to R10C6C.F1 SLICE_387 ROUTE 39 1.414 R10C6C.F1 to R4C8A.LSR SDRAM_TEST_GENERATOR_INST/cnt_rst_0_i (to tft_clk_sig_c) -------- 2.809 (30.4% logic, 69.6% route), 2 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.479 LPLL.CLKOP to R10C6C.CLK sys_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 1.479 LPLL.CLKOS3 to R4C8A.CLK tft_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Passed: The following path meets requirements by 0.444ns (weighted slack = 3.108ns) Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q SDRAM_CTRL_INST/sdram_ready_reg (from sys_clk_sig_c +) Destination: FF Data in SDRAM_TEST_GENERATOR_INST/sdram_fifo_wr_add_14 (to tft_clk_sig_c +) FF SDRAM_TEST_GENERATOR_INST/scaler_cnt_0 Delay: 2.782ns (30.7% logic, 69.3% route), 2 logic levels. Constraint Details: 2.782ns physical path delay SLICE_387 to SDRAM_TEST_GENERATOR_INST/SLICE_253 meets (delay constraint based on source clock period of 7.692ns and destination clock period of 26.923ns) 3.846ns delay constraint less 0.000ns skew and 0.000ns feedback compensation and 0.620ns LSR_SET requirement (totaling 3.226ns) by 0.444ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R10C6C.CLK to R10C6C.Q0 SLICE_387 (from sys_clk_sig_c) ROUTE 5 0.542 R10C6C.Q0 to R10C6C.D1 sys_sdram_ready_sig CTOF_DEL --- 0.449 R10C6C.D1 to R10C6C.F1 SLICE_387 ROUTE 39 1.387 R10C6C.F1 to R10C7C.LSR SDRAM_TEST_GENERATOR_INST/cnt_rst_0_i (to tft_clk_sig_c) -------- 2.782 (30.7% logic, 69.3% route), 2 logic levels. Clock Skew Details: Source Clock Path:: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.479 LPLL.CLKOP to R10C6C.CLK sys_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Destination Clock Path: Name Fanout Delay (ns) Site Resource PADI_DEL --- 1.132 3.PAD to 3.PADDI ext_osc_clk ROUTE 1 0.655 3.PADDI to LPLL.CLKI ext_osc_clk_c CLKI2OS3_D --- 0.000 LPLL.CLKI to LPLL.CLKOS3 PLL_BLOCK_INST/PLLInst_0 ROUTE 175 1.479 LPLL.CLKOS3 to R10C7C.CLK tft_clk_sig_c -------- 3.266 (34.7% logic, 65.3% route), 2 logic levels. Source Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Destination Clock f/b: Name Fanout Delay (ns) Site Resource CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP PLL_BLOCK_INST/PLLInst_0 ROUTE 214 1.625 LPLL.CLKOP to LPLL.CLKFB sys_clk_sig_c -------- 1.625 (0.0% logic, 100.0% route), 1 logic levels. Report: 37.743MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY NET "osch_clk_sig_inferred_clock" 2.080000 MHz ; 30 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Passed: The following path meets requirements by 474.807ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q POWER_MANAGER_INST/timer_cnt_rst (from osch_clk_sig_inferred_clock +) Destination: FF Data in POWER_MANAGER_INST/timer_cnt_14 (to osch_clk_sig_inferred_clock +) Delay: 5.816ns (53.7% logic, 46.3% route), 10 logic levels. Constraint Details: 5.816ns physical path delay POWER_MANAGER_INST/SLICE_201 to POWER_MANAGER_INST/SLICE_98 meets 480.769ns delay constraint less 0.000ns skew and 0.146ns DIN_SET requirement (totaling 480.623ns) by 474.807ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R8C5C.CLK to R8C5C.Q0 POWER_MANAGER_INST/SLICE_201 (from osch_clk_sig_inferred_clock) ROUTE 1 1.356 R8C5C.Q0 to R7C9C.C1 POWER_MANAGER_INST/timer_cnt_rst CTOF_DEL --- 0.449 R7C9C.C1 to R7C9C.F1 SLICE_571 ROUTE 16 1.339 R7C9C.F1 to R7C4A.A0 POWER_MANAGER_INST/timer_cnt_rst_i C0TOFCO_DE --- 0.866 R7C4A.A0 to R7C4A.FCO POWER_MANAGER_INST/SLICE_97 ROUTE 1 0.000 R7C4A.FCO to R7C4B.FCI POWER_MANAGER_INST/timer_cnt_cry_0 FCITOFCO_D --- 0.143 R7C4B.FCI to R7C4B.FCO POWER_MANAGER_INST/SLICE_104 ROUTE 1 0.000 R7C4B.FCO to R7C4C.FCI POWER_MANAGER_INST/timer_cnt_cry_2 FCITOFCO_D --- 0.143 R7C4C.FCI to R7C4C.FCO POWER_MANAGER_INST/SLICE_103 ROUTE 1 0.000 R7C4C.FCO to R7C4D.FCI POWER_MANAGER_INST/timer_cnt_cry_4 FCITOFCO_D --- 0.143 R7C4D.FCI to R7C4D.FCO POWER_MANAGER_INST/SLICE_102 ROUTE 1 0.000 R7C4D.FCO to R7C5A.FCI POWER_MANAGER_INST/timer_cnt_cry_6 FCITOFCO_D --- 0.143 R7C5A.FCI to R7C5A.FCO POWER_MANAGER_INST/SLICE_101 ROUTE 1 0.000 R7C5A.FCO to R7C5B.FCI POWER_MANAGER_INST/timer_cnt_cry_8 FCITOFCO_D --- 0.143 R7C5B.FCI to R7C5B.FCO POWER_MANAGER_INST/SLICE_100 ROUTE 1 0.000 R7C5B.FCO to R7C5C.FCI POWER_MANAGER_INST/timer_cnt_cry_10 FCITOFCO_D --- 0.143 R7C5C.FCI to R7C5C.FCO POWER_MANAGER_INST/SLICE_99 ROUTE 1 0.000 R7C5C.FCO to R7C5D.FCI POWER_MANAGER_INST/timer_cnt_cry_12 FCITOF1_DE --- 0.544 R7C5D.FCI to R7C5D.F1 POWER_MANAGER_INST/SLICE_98 ROUTE 1 0.000 R7C5D.F1 to R7C5D.DI1 POWER_MANAGER_INST/timer_cnt_s_14 (to osch_clk_sig_inferred_clock) -------- 5.816 (53.7% logic, 46.3% route), 10 logic levels. Clock Skew Details: Source Clock: Delay Connection 4.310ns OSC.OSC to R8C5C.CLK Destination Clock : Delay Connection 4.310ns OSC.OSC to R7C5D.CLK Passed: The following path meets requirements by 474.856ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q POWER_MANAGER_INST/timer_cnt_rst (from osch_clk_sig_inferred_clock +) Destination: FF Data in POWER_MANAGER_INST/timer_cnt_13 (to osch_clk_sig_inferred_clock +) Delay: 5.767ns (53.3% logic, 46.7% route), 10 logic levels. Constraint Details: 5.767ns physical path delay POWER_MANAGER_INST/SLICE_201 to POWER_MANAGER_INST/SLICE_98 meets 480.769ns delay constraint less 0.000ns skew and 0.146ns DIN_SET requirement (totaling 480.623ns) by 474.856ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R8C5C.CLK to R8C5C.Q0 POWER_MANAGER_INST/SLICE_201 (from osch_clk_sig_inferred_clock) ROUTE 1 1.356 R8C5C.Q0 to R7C9C.C1 POWER_MANAGER_INST/timer_cnt_rst CTOF_DEL --- 0.449 R7C9C.C1 to R7C9C.F1 SLICE_571 ROUTE 16 1.339 R7C9C.F1 to R7C4A.A0 POWER_MANAGER_INST/timer_cnt_rst_i C0TOFCO_DE --- 0.866 R7C4A.A0 to R7C4A.FCO POWER_MANAGER_INST/SLICE_97 ROUTE 1 0.000 R7C4A.FCO to R7C4B.FCI POWER_MANAGER_INST/timer_cnt_cry_0 FCITOFCO_D --- 0.143 R7C4B.FCI to R7C4B.FCO POWER_MANAGER_INST/SLICE_104 ROUTE 1 0.000 R7C4B.FCO to R7C4C.FCI POWER_MANAGER_INST/timer_cnt_cry_2 FCITOFCO_D --- 0.143 R7C4C.FCI to R7C4C.FCO POWER_MANAGER_INST/SLICE_103 ROUTE 1 0.000 R7C4C.FCO to R7C4D.FCI POWER_MANAGER_INST/timer_cnt_cry_4 FCITOFCO_D --- 0.143 R7C4D.FCI to R7C4D.FCO POWER_MANAGER_INST/SLICE_102 ROUTE 1 0.000 R7C4D.FCO to R7C5A.FCI POWER_MANAGER_INST/timer_cnt_cry_6 FCITOFCO_D --- 0.143 R7C5A.FCI to R7C5A.FCO POWER_MANAGER_INST/SLICE_101 ROUTE 1 0.000 R7C5A.FCO to R7C5B.FCI POWER_MANAGER_INST/timer_cnt_cry_8 FCITOFCO_D --- 0.143 R7C5B.FCI to R7C5B.FCO POWER_MANAGER_INST/SLICE_100 ROUTE 1 0.000 R7C5B.FCO to R7C5C.FCI POWER_MANAGER_INST/timer_cnt_cry_10 FCITOFCO_D --- 0.143 R7C5C.FCI to R7C5C.FCO POWER_MANAGER_INST/SLICE_99 ROUTE 1 0.000 R7C5C.FCO to R7C5D.FCI POWER_MANAGER_INST/timer_cnt_cry_12 FCITOF0_DE --- 0.495 R7C5D.FCI to R7C5D.F0 POWER_MANAGER_INST/SLICE_98 ROUTE 1 0.000 R7C5D.F0 to R7C5D.DI0 POWER_MANAGER_INST/timer_cnt_s_13 (to osch_clk_sig_inferred_clock) -------- 5.767 (53.3% logic, 46.7% route), 10 logic levels. Clock Skew Details: Source Clock: Delay Connection 4.310ns OSC.OSC to R8C5C.CLK Destination Clock : Delay Connection 4.310ns OSC.OSC to R7C5D.CLK Passed: The following path meets requirements by 474.921ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q POWER_MANAGER_INST/timer_cnt_rst (from osch_clk_sig_inferred_clock +) Destination: FF Data in POWER_MANAGER_INST/timer_cnt_14 (to osch_clk_sig_inferred_clock +) Delay: 5.702ns (52.7% logic, 47.3% route), 10 logic levels. Constraint Details: 5.702ns physical path delay POWER_MANAGER_INST/SLICE_201 to POWER_MANAGER_INST/SLICE_98 meets 480.769ns delay constraint less 0.000ns skew and 0.146ns DIN_SET requirement (totaling 480.623ns) by 474.921ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R8C5C.CLK to R8C5C.Q0 POWER_MANAGER_INST/SLICE_201 (from osch_clk_sig_inferred_clock) ROUTE 1 1.356 R8C5C.Q0 to R7C9C.C1 POWER_MANAGER_INST/timer_cnt_rst CTOF_DEL --- 0.449 R7C9C.C1 to R7C9C.F1 SLICE_571 ROUTE 16 1.339 R7C9C.F1 to R7C4A.A1 POWER_MANAGER_INST/timer_cnt_rst_i C1TOFCO_DE --- 0.752 R7C4A.A1 to R7C4A.FCO POWER_MANAGER_INST/SLICE_97 ROUTE 1 0.000 R7C4A.FCO to R7C4B.FCI POWER_MANAGER_INST/timer_cnt_cry_0 FCITOFCO_D --- 0.143 R7C4B.FCI to R7C4B.FCO POWER_MANAGER_INST/SLICE_104 ROUTE 1 0.000 R7C4B.FCO to R7C4C.FCI POWER_MANAGER_INST/timer_cnt_cry_2 FCITOFCO_D --- 0.143 R7C4C.FCI to R7C4C.FCO POWER_MANAGER_INST/SLICE_103 ROUTE 1 0.000 R7C4C.FCO to R7C4D.FCI POWER_MANAGER_INST/timer_cnt_cry_4 FCITOFCO_D --- 0.143 R7C4D.FCI to R7C4D.FCO POWER_MANAGER_INST/SLICE_102 ROUTE 1 0.000 R7C4D.FCO to R7C5A.FCI POWER_MANAGER_INST/timer_cnt_cry_6 FCITOFCO_D --- 0.143 R7C5A.FCI to R7C5A.FCO POWER_MANAGER_INST/SLICE_101 ROUTE 1 0.000 R7C5A.FCO to R7C5B.FCI POWER_MANAGER_INST/timer_cnt_cry_8 FCITOFCO_D --- 0.143 R7C5B.FCI to R7C5B.FCO POWER_MANAGER_INST/SLICE_100 ROUTE 1 0.000 R7C5B.FCO to R7C5C.FCI POWER_MANAGER_INST/timer_cnt_cry_10 FCITOFCO_D --- 0.143 R7C5C.FCI to R7C5C.FCO POWER_MANAGER_INST/SLICE_99 ROUTE 1 0.000 R7C5C.FCO to R7C5D.FCI POWER_MANAGER_INST/timer_cnt_cry_12 FCITOF1_DE --- 0.544 R7C5D.FCI to R7C5D.F1 POWER_MANAGER_INST/SLICE_98 ROUTE 1 0.000 R7C5D.F1 to R7C5D.DI1 POWER_MANAGER_INST/timer_cnt_s_14 (to osch_clk_sig_inferred_clock) -------- 5.702 (52.7% logic, 47.3% route), 10 logic levels. Clock Skew Details: Source Clock: Delay Connection 4.310ns OSC.OSC to R8C5C.CLK Destination Clock : Delay Connection 4.310ns OSC.OSC to R7C5D.CLK Passed: The following path meets requirements by 474.950ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q POWER_MANAGER_INST/timer_cnt_rst (from osch_clk_sig_inferred_clock +) Destination: FF Data in POWER_MANAGER_INST/timer_cnt_14 (to osch_clk_sig_inferred_clock +) Delay: 5.673ns (52.5% logic, 47.5% route), 9 logic levels. Constraint Details: 5.673ns physical path delay POWER_MANAGER_INST/SLICE_201 to POWER_MANAGER_INST/SLICE_98 meets 480.769ns delay constraint less 0.000ns skew and 0.146ns DIN_SET requirement (totaling 480.623ns) by 474.950ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R8C5C.CLK to R8C5C.Q0 POWER_MANAGER_INST/SLICE_201 (from osch_clk_sig_inferred_clock) ROUTE 1 1.356 R8C5C.Q0 to R7C9C.C1 POWER_MANAGER_INST/timer_cnt_rst CTOF_DEL --- 0.449 R7C9C.C1 to R7C9C.F1 SLICE_571 ROUTE 16 1.339 R7C9C.F1 to R7C4B.A0 POWER_MANAGER_INST/timer_cnt_rst_i C0TOFCO_DE --- 0.866 R7C4B.A0 to R7C4B.FCO POWER_MANAGER_INST/SLICE_104 ROUTE 1 0.000 R7C4B.FCO to R7C4C.FCI POWER_MANAGER_INST/timer_cnt_cry_2 FCITOFCO_D --- 0.143 R7C4C.FCI to R7C4C.FCO POWER_MANAGER_INST/SLICE_103 ROUTE 1 0.000 R7C4C.FCO to R7C4D.FCI POWER_MANAGER_INST/timer_cnt_cry_4 FCITOFCO_D --- 0.143 R7C4D.FCI to R7C4D.FCO POWER_MANAGER_INST/SLICE_102 ROUTE 1 0.000 R7C4D.FCO to R7C5A.FCI POWER_MANAGER_INST/timer_cnt_cry_6 FCITOFCO_D --- 0.143 R7C5A.FCI to R7C5A.FCO POWER_MANAGER_INST/SLICE_101 ROUTE 1 0.000 R7C5A.FCO to R7C5B.FCI POWER_MANAGER_INST/timer_cnt_cry_8 FCITOFCO_D --- 0.143 R7C5B.FCI to R7C5B.FCO POWER_MANAGER_INST/SLICE_100 ROUTE 1 0.000 R7C5B.FCO to R7C5C.FCI POWER_MANAGER_INST/timer_cnt_cry_10 FCITOFCO_D --- 0.143 R7C5C.FCI to R7C5C.FCO POWER_MANAGER_INST/SLICE_99 ROUTE 1 0.000 R7C5C.FCO to R7C5D.FCI POWER_MANAGER_INST/timer_cnt_cry_12 FCITOF1_DE --- 0.544 R7C5D.FCI to R7C5D.F1 POWER_MANAGER_INST/SLICE_98 ROUTE 1 0.000 R7C5D.F1 to R7C5D.DI1 POWER_MANAGER_INST/timer_cnt_s_14 (to osch_clk_sig_inferred_clock) -------- 5.673 (52.5% logic, 47.5% route), 9 logic levels. Clock Skew Details: Source Clock: Delay Connection 4.310ns OSC.OSC to R8C5C.CLK Destination Clock : Delay Connection 4.310ns OSC.OSC to R7C5D.CLK Passed: The following path meets requirements by 474.950ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q POWER_MANAGER_INST/timer_cnt_rst (from osch_clk_sig_inferred_clock +) Destination: FF Data in POWER_MANAGER_INST/timer_cnt_12 (to osch_clk_sig_inferred_clock +) Delay: 5.673ns (52.5% logic, 47.5% route), 9 logic levels. Constraint Details: 5.673ns physical path delay POWER_MANAGER_INST/SLICE_201 to POWER_MANAGER_INST/SLICE_99 meets 480.769ns delay constraint less 0.000ns skew and 0.146ns DIN_SET requirement (totaling 480.623ns) by 474.950ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R8C5C.CLK to R8C5C.Q0 POWER_MANAGER_INST/SLICE_201 (from osch_clk_sig_inferred_clock) ROUTE 1 1.356 R8C5C.Q0 to R7C9C.C1 POWER_MANAGER_INST/timer_cnt_rst CTOF_DEL --- 0.449 R7C9C.C1 to R7C9C.F1 SLICE_571 ROUTE 16 1.339 R7C9C.F1 to R7C4A.A0 POWER_MANAGER_INST/timer_cnt_rst_i C0TOFCO_DE --- 0.866 R7C4A.A0 to R7C4A.FCO POWER_MANAGER_INST/SLICE_97 ROUTE 1 0.000 R7C4A.FCO to R7C4B.FCI POWER_MANAGER_INST/timer_cnt_cry_0 FCITOFCO_D --- 0.143 R7C4B.FCI to R7C4B.FCO POWER_MANAGER_INST/SLICE_104 ROUTE 1 0.000 R7C4B.FCO to R7C4C.FCI POWER_MANAGER_INST/timer_cnt_cry_2 FCITOFCO_D --- 0.143 R7C4C.FCI to R7C4C.FCO POWER_MANAGER_INST/SLICE_103 ROUTE 1 0.000 R7C4C.FCO to R7C4D.FCI POWER_MANAGER_INST/timer_cnt_cry_4 FCITOFCO_D --- 0.143 R7C4D.FCI to R7C4D.FCO POWER_MANAGER_INST/SLICE_102 ROUTE 1 0.000 R7C4D.FCO to R7C5A.FCI POWER_MANAGER_INST/timer_cnt_cry_6 FCITOFCO_D --- 0.143 R7C5A.FCI to R7C5A.FCO POWER_MANAGER_INST/SLICE_101 ROUTE 1 0.000 R7C5A.FCO to R7C5B.FCI POWER_MANAGER_INST/timer_cnt_cry_8 FCITOFCO_D --- 0.143 R7C5B.FCI to R7C5B.FCO POWER_MANAGER_INST/SLICE_100 ROUTE 1 0.000 R7C5B.FCO to R7C5C.FCI POWER_MANAGER_INST/timer_cnt_cry_10 FCITOF1_DE --- 0.544 R7C5C.FCI to R7C5C.F1 POWER_MANAGER_INST/SLICE_99 ROUTE 1 0.000 R7C5C.F1 to R7C5C.DI1 POWER_MANAGER_INST/timer_cnt_s_12 (to osch_clk_sig_inferred_clock) -------- 5.673 (52.5% logic, 47.5% route), 9 logic levels. Clock Skew Details: Source Clock: Delay Connection 4.310ns OSC.OSC to R8C5C.CLK Destination Clock : Delay Connection 4.310ns OSC.OSC to R7C5C.CLK Passed: The following path meets requirements by 474.970ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q POWER_MANAGER_INST/timer_cnt_rst (from osch_clk_sig_inferred_clock +) Destination: FF Data in POWER_MANAGER_INST/timer_cnt_13 (to osch_clk_sig_inferred_clock +) Delay: 5.653ns (52.3% logic, 47.7% route), 10 logic levels. Constraint Details: 5.653ns physical path delay POWER_MANAGER_INST/SLICE_201 to POWER_MANAGER_INST/SLICE_98 meets 480.769ns delay constraint less 0.000ns skew and 0.146ns DIN_SET requirement (totaling 480.623ns) by 474.970ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R8C5C.CLK to R8C5C.Q0 POWER_MANAGER_INST/SLICE_201 (from osch_clk_sig_inferred_clock) ROUTE 1 1.356 R8C5C.Q0 to R7C9C.C1 POWER_MANAGER_INST/timer_cnt_rst CTOF_DEL --- 0.449 R7C9C.C1 to R7C9C.F1 SLICE_571 ROUTE 16 1.339 R7C9C.F1 to R7C4A.A1 POWER_MANAGER_INST/timer_cnt_rst_i C1TOFCO_DE --- 0.752 R7C4A.A1 to R7C4A.FCO POWER_MANAGER_INST/SLICE_97 ROUTE 1 0.000 R7C4A.FCO to R7C4B.FCI POWER_MANAGER_INST/timer_cnt_cry_0 FCITOFCO_D --- 0.143 R7C4B.FCI to R7C4B.FCO POWER_MANAGER_INST/SLICE_104 ROUTE 1 0.000 R7C4B.FCO to R7C4C.FCI POWER_MANAGER_INST/timer_cnt_cry_2 FCITOFCO_D --- 0.143 R7C4C.FCI to R7C4C.FCO POWER_MANAGER_INST/SLICE_103 ROUTE 1 0.000 R7C4C.FCO to R7C4D.FCI POWER_MANAGER_INST/timer_cnt_cry_4 FCITOFCO_D --- 0.143 R7C4D.FCI to R7C4D.FCO POWER_MANAGER_INST/SLICE_102 ROUTE 1 0.000 R7C4D.FCO to R7C5A.FCI POWER_MANAGER_INST/timer_cnt_cry_6 FCITOFCO_D --- 0.143 R7C5A.FCI to R7C5A.FCO POWER_MANAGER_INST/SLICE_101 ROUTE 1 0.000 R7C5A.FCO to R7C5B.FCI POWER_MANAGER_INST/timer_cnt_cry_8 FCITOFCO_D --- 0.143 R7C5B.FCI to R7C5B.FCO POWER_MANAGER_INST/SLICE_100 ROUTE 1 0.000 R7C5B.FCO to R7C5C.FCI POWER_MANAGER_INST/timer_cnt_cry_10 FCITOFCO_D --- 0.143 R7C5C.FCI to R7C5C.FCO POWER_MANAGER_INST/SLICE_99 ROUTE 1 0.000 R7C5C.FCO to R7C5D.FCI POWER_MANAGER_INST/timer_cnt_cry_12 FCITOF0_DE --- 0.495 R7C5D.FCI to R7C5D.F0 POWER_MANAGER_INST/SLICE_98 ROUTE 1 0.000 R7C5D.F0 to R7C5D.DI0 POWER_MANAGER_INST/timer_cnt_s_13 (to osch_clk_sig_inferred_clock) -------- 5.653 (52.3% logic, 47.7% route), 10 logic levels. Clock Skew Details: Source Clock: Delay Connection 4.310ns OSC.OSC to R8C5C.CLK Destination Clock : Delay Connection 4.310ns OSC.OSC to R7C5D.CLK Passed: The following path meets requirements by 474.986ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q POWER_MANAGER_INST/timer_cnt_rst (from osch_clk_sig_inferred_clock +) Destination: FF Data in POWER_MANAGER_INST/timer_cnt_14 (to osch_clk_sig_inferred_clock +) Delay: 5.637ns (45.2% logic, 54.8% route), 6 logic levels. Constraint Details: 5.637ns physical path delay POWER_MANAGER_INST/SLICE_201 to POWER_MANAGER_INST/SLICE_98 meets 480.769ns delay constraint less 0.000ns skew and 0.146ns DIN_SET requirement (totaling 480.623ns) by 474.986ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R8C5C.CLK to R8C5C.Q0 POWER_MANAGER_INST/SLICE_201 (from osch_clk_sig_inferred_clock) ROUTE 1 1.356 R8C5C.Q0 to R7C9C.C1 POWER_MANAGER_INST/timer_cnt_rst CTOF_DEL --- 0.449 R7C9C.C1 to R7C9C.F1 SLICE_571 ROUTE 16 1.732 R7C9C.F1 to R7C5A.A0 POWER_MANAGER_INST/timer_cnt_rst_i C0TOFCO_DE --- 0.866 R7C5A.A0 to R7C5A.FCO POWER_MANAGER_INST/SLICE_101 ROUTE 1 0.000 R7C5A.FCO to R7C5B.FCI POWER_MANAGER_INST/timer_cnt_cry_8 FCITOFCO_D --- 0.143 R7C5B.FCI to R7C5B.FCO POWER_MANAGER_INST/SLICE_100 ROUTE 1 0.000 R7C5B.FCO to R7C5C.FCI POWER_MANAGER_INST/timer_cnt_cry_10 FCITOFCO_D --- 0.143 R7C5C.FCI to R7C5C.FCO POWER_MANAGER_INST/SLICE_99 ROUTE 1 0.000 R7C5C.FCO to R7C5D.FCI POWER_MANAGER_INST/timer_cnt_cry_12 FCITOF1_DE --- 0.544 R7C5D.FCI to R7C5D.F1 POWER_MANAGER_INST/SLICE_98 ROUTE 1 0.000 R7C5D.F1 to R7C5D.DI1 POWER_MANAGER_INST/timer_cnt_s_14 (to osch_clk_sig_inferred_clock) -------- 5.637 (45.2% logic, 54.8% route), 6 logic levels. Clock Skew Details: Source Clock: Delay Connection 4.310ns OSC.OSC to R8C5C.CLK Destination Clock : Delay Connection 4.310ns OSC.OSC to R7C5D.CLK Passed: The following path meets requirements by 474.999ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q POWER_MANAGER_INST/timer_cnt_rst (from osch_clk_sig_inferred_clock +) Destination: FF Data in POWER_MANAGER_INST/timer_cnt_11 (to osch_clk_sig_inferred_clock +) Delay: 5.624ns (52.1% logic, 47.9% route), 9 logic levels. Constraint Details: 5.624ns physical path delay POWER_MANAGER_INST/SLICE_201 to POWER_MANAGER_INST/SLICE_99 meets 480.769ns delay constraint less 0.000ns skew and 0.146ns DIN_SET requirement (totaling 480.623ns) by 474.999ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R8C5C.CLK to R8C5C.Q0 POWER_MANAGER_INST/SLICE_201 (from osch_clk_sig_inferred_clock) ROUTE 1 1.356 R8C5C.Q0 to R7C9C.C1 POWER_MANAGER_INST/timer_cnt_rst CTOF_DEL --- 0.449 R7C9C.C1 to R7C9C.F1 SLICE_571 ROUTE 16 1.339 R7C9C.F1 to R7C4A.A0 POWER_MANAGER_INST/timer_cnt_rst_i C0TOFCO_DE --- 0.866 R7C4A.A0 to R7C4A.FCO POWER_MANAGER_INST/SLICE_97 ROUTE 1 0.000 R7C4A.FCO to R7C4B.FCI POWER_MANAGER_INST/timer_cnt_cry_0 FCITOFCO_D --- 0.143 R7C4B.FCI to R7C4B.FCO POWER_MANAGER_INST/SLICE_104 ROUTE 1 0.000 R7C4B.FCO to R7C4C.FCI POWER_MANAGER_INST/timer_cnt_cry_2 FCITOFCO_D --- 0.143 R7C4C.FCI to R7C4C.FCO POWER_MANAGER_INST/SLICE_103 ROUTE 1 0.000 R7C4C.FCO to R7C4D.FCI POWER_MANAGER_INST/timer_cnt_cry_4 FCITOFCO_D --- 0.143 R7C4D.FCI to R7C4D.FCO POWER_MANAGER_INST/SLICE_102 ROUTE 1 0.000 R7C4D.FCO to R7C5A.FCI POWER_MANAGER_INST/timer_cnt_cry_6 FCITOFCO_D --- 0.143 R7C5A.FCI to R7C5A.FCO POWER_MANAGER_INST/SLICE_101 ROUTE 1 0.000 R7C5A.FCO to R7C5B.FCI POWER_MANAGER_INST/timer_cnt_cry_8 FCITOFCO_D --- 0.143 R7C5B.FCI to R7C5B.FCO POWER_MANAGER_INST/SLICE_100 ROUTE 1 0.000 R7C5B.FCO to R7C5C.FCI POWER_MANAGER_INST/timer_cnt_cry_10 FCITOF0_DE --- 0.495 R7C5C.FCI to R7C5C.F0 POWER_MANAGER_INST/SLICE_99 ROUTE 1 0.000 R7C5C.F0 to R7C5C.DI0 POWER_MANAGER_INST/timer_cnt_s_11 (to osch_clk_sig_inferred_clock) -------- 5.624 (52.1% logic, 47.9% route), 9 logic levels. Clock Skew Details: Source Clock: Delay Connection 4.310ns OSC.OSC to R8C5C.CLK Destination Clock : Delay Connection 4.310ns OSC.OSC to R7C5C.CLK Passed: The following path meets requirements by 474.999ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q POWER_MANAGER_INST/timer_cnt_rst (from osch_clk_sig_inferred_clock +) Destination: FF Data in POWER_MANAGER_INST/timer_cnt_13 (to osch_clk_sig_inferred_clock +) Delay: 5.624ns (52.1% logic, 47.9% route), 9 logic levels. Constraint Details: 5.624ns physical path delay POWER_MANAGER_INST/SLICE_201 to POWER_MANAGER_INST/SLICE_98 meets 480.769ns delay constraint less 0.000ns skew and 0.146ns DIN_SET requirement (totaling 480.623ns) by 474.999ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R8C5C.CLK to R8C5C.Q0 POWER_MANAGER_INST/SLICE_201 (from osch_clk_sig_inferred_clock) ROUTE 1 1.356 R8C5C.Q0 to R7C9C.C1 POWER_MANAGER_INST/timer_cnt_rst CTOF_DEL --- 0.449 R7C9C.C1 to R7C9C.F1 SLICE_571 ROUTE 16 1.339 R7C9C.F1 to R7C4B.A0 POWER_MANAGER_INST/timer_cnt_rst_i C0TOFCO_DE --- 0.866 R7C4B.A0 to R7C4B.FCO POWER_MANAGER_INST/SLICE_104 ROUTE 1 0.000 R7C4B.FCO to R7C4C.FCI POWER_MANAGER_INST/timer_cnt_cry_2 FCITOFCO_D --- 0.143 R7C4C.FCI to R7C4C.FCO POWER_MANAGER_INST/SLICE_103 ROUTE 1 0.000 R7C4C.FCO to R7C4D.FCI POWER_MANAGER_INST/timer_cnt_cry_4 FCITOFCO_D --- 0.143 R7C4D.FCI to R7C4D.FCO POWER_MANAGER_INST/SLICE_102 ROUTE 1 0.000 R7C4D.FCO to R7C5A.FCI POWER_MANAGER_INST/timer_cnt_cry_6 FCITOFCO_D --- 0.143 R7C5A.FCI to R7C5A.FCO POWER_MANAGER_INST/SLICE_101 ROUTE 1 0.000 R7C5A.FCO to R7C5B.FCI POWER_MANAGER_INST/timer_cnt_cry_8 FCITOFCO_D --- 0.143 R7C5B.FCI to R7C5B.FCO POWER_MANAGER_INST/SLICE_100 ROUTE 1 0.000 R7C5B.FCO to R7C5C.FCI POWER_MANAGER_INST/timer_cnt_cry_10 FCITOFCO_D --- 0.143 R7C5C.FCI to R7C5C.FCO POWER_MANAGER_INST/SLICE_99 ROUTE 1 0.000 R7C5C.FCO to R7C5D.FCI POWER_MANAGER_INST/timer_cnt_cry_12 FCITOF0_DE --- 0.495 R7C5D.FCI to R7C5D.F0 POWER_MANAGER_INST/SLICE_98 ROUTE 1 0.000 R7C5D.F0 to R7C5D.DI0 POWER_MANAGER_INST/timer_cnt_s_13 (to osch_clk_sig_inferred_clock) -------- 5.624 (52.1% logic, 47.9% route), 9 logic levels. Clock Skew Details: Source Clock: Delay Connection 4.310ns OSC.OSC to R8C5C.CLK Destination Clock : Delay Connection 4.310ns OSC.OSC to R7C5D.CLK Passed: The following path meets requirements by 475.035ns Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-) Source: FF Q POWER_MANAGER_INST/timer_cnt_rst (from osch_clk_sig_inferred_clock +) Destination: FF Data in POWER_MANAGER_INST/timer_cnt_13 (to osch_clk_sig_inferred_clock +) Delay: 5.588ns (44.7% logic, 55.3% route), 6 logic levels. Constraint Details: 5.588ns physical path delay POWER_MANAGER_INST/SLICE_201 to POWER_MANAGER_INST/SLICE_98 meets 480.769ns delay constraint less 0.000ns skew and 0.146ns DIN_SET requirement (totaling 480.623ns) by 475.035ns Physical Path Details: Name Fanout Delay (ns) Site Resource REG_DEL --- 0.404 R8C5C.CLK to R8C5C.Q0 POWER_MANAGER_INST/SLICE_201 (from osch_clk_sig_inferred_clock) ROUTE 1 1.356 R8C5C.Q0 to R7C9C.C1 POWER_MANAGER_INST/timer_cnt_rst CTOF_DEL --- 0.449 R7C9C.C1 to R7C9C.F1 SLICE_571 ROUTE 16 1.732 R7C9C.F1 to R7C5A.A0 POWER_MANAGER_INST/timer_cnt_rst_i C0TOFCO_DE --- 0.866 R7C5A.A0 to R7C5A.FCO POWER_MANAGER_INST/SLICE_101 ROUTE 1 0.000 R7C5A.FCO to R7C5B.FCI POWER_MANAGER_INST/timer_cnt_cry_8 FCITOFCO_D --- 0.143 R7C5B.FCI to R7C5B.FCO POWER_MANAGER_INST/SLICE_100 ROUTE 1 0.000 R7C5B.FCO to R7C5C.FCI POWER_MANAGER_INST/timer_cnt_cry_10 FCITOFCO_D --- 0.143 R7C5C.FCI to R7C5C.FCO POWER_MANAGER_INST/SLICE_99 ROUTE 1 0.000 R7C5C.FCO to R7C5D.FCI POWER_MANAGER_INST/timer_cnt_cry_12 FCITOF0_DE --- 0.495 R7C5D.FCI to R7C5D.F0 POWER_MANAGER_INST/SLICE_98 ROUTE 1 0.000 R7C5D.F0 to R7C5D.DI0 POWER_MANAGER_INST/timer_cnt_s_13 (to osch_clk_sig_inferred_clock) -------- 5.588 (44.7% logic, 55.3% route), 6 logic levels. Clock Skew Details: Source Clock: Delay Connection 4.310ns OSC.OSC to R8C5C.CLK Destination Clock : Delay Connection 4.310ns OSC.OSC to R7C5D.CLK Report: 167.729MHz is the maximum frequency for this preference. ================================================================================ Preference: FREQUENCY NET "ext_osc_clk_c" 40.000000 MHz ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- ================================================================================ Preference: FREQUENCY PORT "ext_osc_clk" 40.000000 MHz ; 0 items scored, 0 timing errors detected. -------------------------------------------------------------------------------- Report Summary -------------- ---------------------------------------------------------------------------- Preference | Constraint| Actual|Levels ---------------------------------------------------------------------------- | | | FREQUENCY NET "sys_clk_sig_c" | | | 130.000000 MHz ; | 130.000 MHz| 126.326 MHz| 7 * | | | FREQUENCY NET "TX_LVDS_71_INST/eclko" | | | 130.000000 MHz ; | 130.000 MHz| 363.636 MHz| 1 | | | FREQUENCY NET | | | "TX_LVDS_71_INST/sclk_sig" 38.000000 | | | MHz ; | 38.000 MHz| 873.362 MHz| 1 | | | FREQUENCY NET "tft_clk_sig_c" 37.142857 | | | MHz ; | 37.143 MHz| 37.743 MHz| 2 | | | FREQUENCY NET | | | "osch_clk_sig_inferred_clock" 2.080000 | | | MHz ; | 2.080 MHz| 167.729 MHz| 10 | | | FREQUENCY NET "ext_osc_clk_c" 40.000000 | | | MHz ; | -| -| 0 | | | FREQUENCY PORT "ext_osc_clk" 40.000000 | | | MHz ; | -| -| 0 | | | ---------------------------------------------------------------------------- 1 preference(marked by "*" above) not met. ---------------------------------------------------------------------------- Critical Nets | Loads| Errors| % of total ---------------------------------------------------------------------------- PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIF| | | O_INST/co0_3 | 1| 2| 50.00% | | | PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIF| | | O_INST/co1_3 | 1| 2| 50.00% | | | PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIF| | | O_INST/empty_d_c | 1| 2| 50.00% | | | PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIF| | | O_INST/cmp_ci | 1| 2| 50.00% | | | PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIF| | | O_INST/empty_d | 1| 2| 50.00% | | | PIXEL_ADDR_DATA_FIFO_INST/PIXEL_DATA_FIF| | | O_INST/rden_i | 15| 2| 50.00% | | | fifo_empty_sig | 2| 2| 50.00% | | | SDRAM_CTRL_INST/sdram_a_reg_9_sn_N_8 | 2| 2| 50.00% | | | SDRAM_CTRL_INST/sdram_a_reg_9_sm0_i | 4| 2| 50.00% | | | SDRAM_CTRL_INST/sdram_a_reg_9_sn_N_15 | 11| 2| 50.00% | | | SDRAM_CTRL_INST/sdram_a_reg_9_sn_N_11 | 1| 2| 50.00% | | | SDRAM_CTRL_INST/sdram_fsm_st_4 | 28| 2| 50.00% | | | SDRAM_CTRL_INST_SDRAM_FSM_PROC_sdram_a_r| | | eg_9_0_i_1 | 1| 1| 25.00% | | | SDRAM_CTRL_INST_SDRAM_FSM_PROC_sdram_a_r| | | eg_9_0_i_0 | 1| 1| 25.00% | | | ---------------------------------------------------------------------------- Clock Domains Analysis ------------------------ Found 6 clocks: Clock Domain: TX_LVDS_71_INST/sclk_sig Source: TX_LVDS_71_INST/Inst3_CLKDIVC.CDIVX Loads: 5 No transfer within this clock domain is found Data transfers from: Clock Domain: tft_clk_sig_c Source: PLL_BLOCK_INST/PLLInst_0.CLKOS3 Covered under: FREQUENCY NET "TX_LVDS_71_INST/sclk_sig" 38.000000 MHz ; Transfers: 18 Clock Domain: TX_LVDS_71_INST/eclko Source: TX_LVDS_71_INST/Inst2_ECLKSYNCA.ECLKO Loads: 6 No transfer within this clock domain is found Data transfers from: Clock Domain: TX_LVDS_71_INST/sclk_sig Source: TX_LVDS_71_INST/Inst3_CLKDIVC.CDIVX Covered under: Timing Rule Check Transfers: 4 Clock Domain: tft_clk_sig_c Source: PLL_BLOCK_INST/PLLInst_0.CLKOS3 Loads: 175 Covered under: FREQUENCY NET "tft_clk_sig_c" 37.142857 MHz ; Data transfers from: Clock Domain: sys_clk_sig_c Source: PLL_BLOCK_INST/PLLInst_0.CLKOP Covered under: FREQUENCY NET "tft_clk_sig_c" 37.142857 MHz ; Transfers: 23 Clock Domain: sys_clk_sig_c Source: PLL_BLOCK_INST/PLLInst_0.CLKOP Loads: 214 Covered under: FREQUENCY NET "sys_clk_sig_c" 130.000000 MHz ; Data transfers from: Clock Domain: tft_clk_sig_c Source: PLL_BLOCK_INST/PLLInst_0.CLKOS3 Covered under: FREQUENCY NET "sys_clk_sig_c" 130.000000 MHz ; Transfers: 71 Clock Domain: osch_clk_sig_inferred_clock Source: OSCH_INST.OSC Not reported because source and destination domains are unrelated. Clock Domain: osch_clk_sig_inferred_clock Source: OSCH_INST.OSC Loads: 16 Covered under: FREQUENCY NET "osch_clk_sig_inferred_clock" 2.080000 MHz ; Clock Domain: ext_osc_clk_c Source: ext_osc_clk.PAD Loads: 1 No transfer within this clock domain is found Timing summary (Setup): --------------- Timing errors: 4 Score: 514 Cumulative negative slack: 514 Constraints cover 4656 paths, 6 nets, and 3406 connections (96.0% coverage)