#Build: Synplify Pro G-2012.09L-SP1 , Build 029R, Mar 11 2013
#install: C:\lscc\diamond\2.2\synpbase
#OS: Windows XP 5.1
#Hostname: ITLFFERRARI

#Implementation: prj_diamond_ver0

$ Start of Compile
#Thu Jun 20 21:29:49 2013

Synopsys Verilog Compiler, version comp201209rcp1, Build 271R, built Mar 11 2013
@N: :  | Running in 32-bit mode 
Copyright (C) 1994-2012 Synopsys, Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc.

@N: :  | : Running Verilog Compiler in System Verilog mode 
@N: :  | : Running Verilog Compiler in Multiple File Compilation Unit mode 
@I::"C:\lscc\diamond\2.2\synpbase\lib\lucent\machxo2.v"
@I::"C:\lscc\diamond\2.2\synpbase\lib\lucent\pmi_def.v"
@I::"C:\lscc\diamond\2.2\synpbase\lib\vlog\umr_capim.v"
@I::"C:\lscc\diamond\2.2\synpbase\lib\vlog\scemi_objects.v"
@I::"C:\lscc\diamond\2.2\synpbase\lib\vlog\scemi_pipes.svh"
@I::"C:\lscc\diamond\2.2\synpbase\lib\vlog\hypermods.v"
@I::"C:\lscc\diamond\2.2\cae_library\synthesis\verilog\machxo2.v"
@I::"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\system_conf.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\pmi_def.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\er1.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\typeb.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\typea.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\jtag_cores.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\jtag_cores.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\jtag_lm32.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_jtag.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_addsub.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_adder.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v"
@W:CS141 : lm32_cpu.v(652) | Unrecognized synthesis directive attribute
@W:CS141 : lm32_cpu.v(653) | Unrecognized synthesis directive attribute
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_cpu.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_functions.v"
@N:CG334 : lm32_cpu.v(2773) | Read directive translate_off 
@N:CG333 : lm32_cpu.v(2786) | Read directive translate_on 
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_dcache.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_debug.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_decoder.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_icache.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_instruction_unit.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_interrupt.v"
@W:CS141 : lm32_interrupt.v(130) | Unrecognized synthesis directive attribute
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_load_store_unit.v"
@N:CG334 : lm32_load_store_unit.v(678) | Read directive translate_off 
@N:CG333 : lm32_load_store_unit.v(681) | Read directive translate_on 
@N:CG334 : lm32_load_store_unit.v(811) | Read directive translate_off 
@N:CG333 : lm32_load_store_unit.v(825) | Read directive translate_on 
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_logic_op.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_mc_arithmetic.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_multiplier.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_shifter.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_top.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_monitor_ram.v"
@N:CG334 : lm32_monitor_ram.v(597) | Read directive translate_off 
@N:CG333 : lm32_monitor_ram.v(640) | Read directive translate_on 
@N:CG334 : lm32_monitor_ram.v(717) | Read directive translate_off 
@N:CG333 : lm32_monitor_ram.v(760) | Read directive translate_on 
@N:CG334 : lm32_monitor_ram.v(932) | Read directive translate_off 
@N:CG333 : lm32_monitor_ram.v(1007) | Read directive translate_on 
@N:CG334 : lm32_monitor_ram.v(1117) | Read directive translate_off 
@N:CG333 : lm32_monitor_ram.v(1192) | Read directive translate_on 
@N:CG334 : lm32_monitor_ram.v(1461) | Read directive translate_off 
@N:CG333 : lm32_monitor_ram.v(1536) | Read directive translate_on 
@N:CG334 : lm32_monitor_ram.v(1645) | Read directive translate_off 
@N:CG333 : lm32_monitor_ram.v(1720) | Read directive translate_on 
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/lm32_top/rtl/verilog\lm32_trace.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\uart_core.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\uart_core.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\intface.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txcver_fifo.v"
@N:CG334 : intface.v(953) | Read directive translate_off 
@N:CG333 : intface.v(1017) | Read directive translate_on 
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\uart_core.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\rxcver_fifo.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\uart_core.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/uart_core/rtl/verilog\txmitt.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\platform_rev0.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdram_include_all.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdram_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\wb_sdr_ctrl.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\wb_sdr_ctrl.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_par.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdram_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\wb_fifo_intf.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdram_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_fifo_intf.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdram_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_ctrl.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdram_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_sig.v"
@I:"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdram_include_all.v":"C:\work\project\artekit_demos\forza4_rev0\diamond\..\msb\platform_rev0\soc\../components/wb_sdr_ctrl/rtl/verilog\sdr_data.v"
Verilog syntax check successful!
Selecting top level module platform_rev0
@N:CG364 : platform_rev0.v(48) | Synthesizing module arbiter2

	MAX_DAT_WIDTH=32'b00000000000000000000000000100000
	WBS_DAT_WIDTH=32'b00000000000000000000000000100000
	WBM0_DAT_WIDTH=32'b00000000000000000000000000100000
	WBM1_DAT_WIDTH=32'b00000000000000000000000000100000
   Generated name = arbiter2_32s_32s_32s_32s

@N:CG364 : lm32_instruction_unit.v(77) | Synthesizing module lm32_instruction_unit

	associativity=32'b00000000000000000000000000000001
	sets=32'b00000000000000000000001000000000
	bytes_per_line=32'b00000000000000000000000000010000
	base_address=32'b00000000000000000000000000000000
	limit=32'b00000000000000000000000000000000
	addr_offset_width=32'b00000000000000000000000000000010
	addr_offset_lsb=32'b00000000000000000000000000000010
	addr_offset_msb=32'b00000000000000000000000000000011
   Generated name = lm32_instruction_unit_1s_512s_16s_0s_0s_2s_2s_3s

@N:CG793 : lm32_instruction_unit.v(824) | Ignoring system task $display
@W:CL113 : lm32_instruction_unit.v(792) | Feedback mux created for signal i_lock_o.
@W:CL113 : lm32_instruction_unit.v(792) | Feedback mux created for signal i_cti_o[2:0].
@W:CL251 : lm32_instruction_unit.v(792) | All reachable assignments to i_cti_o[2:0] assign 1, register removed by optimization
@W:CL250 : lm32_instruction_unit.v(792) | All reachable assignments to i_lock_o assign 0, register removed by optimization
@W:CL190 : lm32_instruction_unit.v(792) | Optimizing register bit i_adr_o[0] to a constant 0
@W:CL190 : lm32_instruction_unit.v(792) | Optimizing register bit i_adr_o[1] to a constant 0
@W:CL279 : lm32_instruction_unit.v(792) | Pruning register bits 1 to 0 of i_adr_o[31:0] 

@N:CG364 : lm32_decoder.v(113) | Synthesizing module lm32_decoder

@N:CG364 : lm32_load_store_unit.v(69) | Synthesizing module lm32_load_store_unit

	associativity=32'b00000000000000000000000000000001
	sets=32'b00000000000000000000001000000000
	bytes_per_line=32'b00000000000000000000000000010000
	base_address=32'b00000000000000000000000000000000
	limit=32'b00000000000000000000000000000000
	addr_offset_width=32'b00000000000000000000000000000010
	addr_offset_lsb=32'b00000000000000000000000000000010
	addr_offset_msb=32'b00000000000000000000000000000011
   Generated name = lm32_load_store_unit_1s_512s_16s_0s_0s_2s_2s_3s

@W:CL190 : lm32_load_store_unit.v(623) | Optimizing register bit d_cti_o[0] to a constant 1
@W:CL190 : lm32_load_store_unit.v(623) | Optimizing register bit d_cti_o[1] to a constant 1
@W:CL190 : lm32_load_store_unit.v(623) | Optimizing register bit d_cti_o[2] to a constant 1
@W:CL190 : lm32_load_store_unit.v(623) | Optimizing register bit d_lock_o to a constant 0
@W:CL169 : lm32_load_store_unit.v(623) | Pruning register d_cti_o[2:0] 

@W:CL169 : lm32_load_store_unit.v(623) | Pruning register d_lock_o 

@N:CG364 : lm32_addsub.v(55) | Synthesizing module lm32_addsub

@N:CG364 : pmi_def.v(48) | Synthesizing module pmi_addsub

	pmi_data_width=32'b00000000000000000000000000100000
	pmi_result_width=32'b00000000000000000000000000100000
	pmi_sign=24'b011011110110011001100110
	pmi_family=56'b01001101011000010110001101101000010110000100111100110010
	module_type=80'b01110000011011010110100101011111011000010110010001100100011100110111010101100010
   Generated name = pmi_addsub_32s_32s_off_MachXO2_pmi_addsub

@N:CG364 : lm32_adder.v(56) | Synthesizing module lm32_adder

@N:CG364 : lm32_logic_op.v(56) | Synthesizing module lm32_logic_op

@N:CG364 : lm32_shifter.v(56) | Synthesizing module lm32_shifter

@N:CG364 : lm32_multiplier.v(56) | Synthesizing module lm32_multiplier

@N:CG364 : lm32_mc_arithmetic.v(64) | Synthesizing module lm32_mc_arithmetic

@N:CG364 : lm32_interrupt.v(56) | Synthesizing module lm32_interrupt

@N:CG364 : lm32_jtag.v(87) | Synthesizing module lm32_jtag

@W:CL169 : lm32_jtag.v(309) | Pruning register command[3:0] 

@W:CL113 : lm32_jtag.v(309) | Feedback mux created for signal state[3:0].
@W:CL250 : lm32_jtag.v(309) | All reachable assignments to state[3:0] assign 0, register removed by optimization
@N:CG364 : lm32_debug.v(69) | Synthesizing module lm32_debug

	breakpoints=32'b00000000000000000000000000000000
	watchpoints=32'b00000000000000000000000000000000
   Generated name = lm32_debug_0s_0

@W:CG133 : lm32_debug.v(164) | No assignment to bp_a_-1_
@W:CG133 : lm32_debug.v(164) | No assignment to bp_a_0_
@W:CG133 : lm32_debug.v(165) | No assignment to bp_e_-1_
@W:CG133 : lm32_debug.v(165) | No assignment to bp_e_0_
@W:CG360 : lm32_debug.v(166) | No assignment to wire bp_match_n

@W:CG133 : lm32_debug.v(168) | No assignment to wpc_c[0]
@W:CG133 : lm32_debug.v(168) | No assignment to wpc_c[-1]
@W:CG133 : lm32_debug.v(169) | No assignment to wp_-1_
@W:CG133 : lm32_debug.v(169) | No assignment to wp_0_
@W:CG360 : lm32_debug.v(170) | No assignment to wire wp_match_n

@N:CG364 : lm32_cpu.v(100) | Synthesizing module lm32_cpu

@W:CL169 : lm32_cpu.v(2303) | Pruning register x_result_sel_logic_x 

@W:CL169 : lm32_cpu.v(2303) | Pruning register eret_m 

@W:CL169 : lm32_cpu.v(2303) | Pruning register bret_m 

@N:CG364 : lm32_monitor_ram.v(53) | Synthesizing module lm32_monitor_ram

@N:CG364 : machxo2.v(1291) | Synthesizing module DP8KC

@N:CG364 : machxo2.v(1120) | Synthesizing module VHI

@N:CG364 : machxo2.v(1124) | Synthesizing module VLO

@N:CG364 : lm32_monitor.v(57) | Synthesizing module lm32_monitor

@A:CL282 : lm32_monitor.v(143) | Feedback mux created for signal write_data[31:0] -- possible set/reset assignment for signal missing. Specifying a reset value will improve timing and area.
@N:CG364 : jtag_cores.v(60) | Synthesizing module jtagconn16

@W:CG146 : jtag_cores.v(60) | Creating black box for empty module jtagconn16

@N:CG364 : typea.v(65) | Synthesizing module TYPEA

@N:CG364 : jtag_lm32.v(51) | Synthesizing module jtag_lm32

@N:CG364 : jtag_cores.v(75) | Synthesizing module jtag_cores

@W:CG781 : jtag_cores.v(146) | Undriven input CONTROL_DATAN on instance jtag_lm32_inst, tying to 0
@N:CG364 : lm32_top.v(58) | Synthesizing module lm32_top

@N:CG364 : intface.v(321) | Synthesizing module intface

	CLK_IN_MHZ=72'b001100100011010100101110001100000011000000110000001100000011000000110000
	UART_WB_ADR_WIDTH=32'b00000000000000000000000000000100
	UART_WB_DAT_WIDTH=32'b00000000000000000000000000001000
	BAUD_RATE=32'b00000000000000011100001000000000
	FIFO=32'b00000000000000000000000000000000
	LCR_DATA_BITS=32'b00000000000000000000000000001000
	LCR_STOP_BITS=32'b00000000000000000000000000000001
	LCR_PARITY_ENABLE=32'b00000000000000000000000000000000
	LCR_PARITY_ODD=32'b00000000000000000000000000000000
	LCR_PARITY_STICK=32'b00000000000000000000000000000000
	LCR_SET_BREAK=32'b00000000000000000000000000000000
	STDOUT_SIM=32'b00000000000000000000000000000000
	STDOUT_SIMFAST=32'b00000000000000000000000000000000
	A_RBR=4'b0000
	A_THR=4'b0000
	A_IER=4'b0001
	A_IIR=4'b0010
	A_LCR=4'b0011
	A_LSR=4'b0101
	A_DIV=3'b100
	idle=3'b000
	int0=3'b001
	int1=3'b010
	int2=3'b011
	int3=3'b100
   Generated name = intface_Z1

@W:CG813 : intface.v(501) | Rounding real from 217.013889 to 217 (simulation mismatch possible)
@W:CG360 : intface.v(382) | No assignment to wire fifo_empty_thr

@W:CG360 : intface.v(383) | No assignment to wire fifo_full_thr

@W:CG360 : intface.v(436) | No assignment to wire thr_fifo

@W:CG133 : intface.v(466) | No assignment to iir_rd_strobe_delay
@W:CG133 : intface.v(469) | No assignment to lsr2_r
@W:CG133 : intface.v(469) | No assignment to lsr3_r
@W:CG133 : intface.v(469) | No assignment to lsr4_r
@W:CG360 : intface.v(491) | No assignment to wire fifo_almost_full_thr

@W:CG360 : intface.v(492) | No assignment to wire fifo_almost_empty_thr

@W:CG360 : intface.v(493) | No assignment to wire fifo_din_thr

@W:CG133 : intface.v(494) | No assignment to fifo_wr_thr
@W:CG133 : intface.v(495) | No assignment to fifo_wr_q_thr
@W:CG360 : intface.v(496) | No assignment to wire fifo_wr_pulse_thr

@N:CG364 : rxcver.v(94) | Synthesizing module rxcver

	UART_WB_DAT_WIDTH=32'b00000000000000000000000000001000
	FIFO=32'b00000000000000000000000000000000
	idle=3'b000
	shift=3'b001
	parity=3'b010
	stop=3'b011
	idle1=3'b100
	lat_family=56'b01001101011000010110001101101000010110000100111100110010
   Generated name = rxcver_8s_0s_0_1_2_3_4_MachXO2

@W:CG360 : rxcver.v(134) | No assignment to wire rbr_fifo

@W:CG360 : rxcver.v(141) | No assignment to wire fifo_empty

@W:CG360 : rxcver.v(142) | No assignment to wire fifo_almost_full

@W:CG133 : rxcver.v(151) | No assignment to count
@W:CG133 : rxcver.v(163) | No assignment to rxclk_en
@W:CG360 : rxcver.v(166) | No assignment to wire rbr_fifo_error

@W:CG360 : rxcver.v(181) | No assignment to wire fifo_full

@W:CG360 : rxcver.v(184) | No assignment to wire fifo_almost_empty

@W:CG133 : rxcver.v(185) | No assignment to fifo_din
@W:CG133 : rxcver.v(186) | No assignment to fifo_wr
@W:CG133 : rxcver.v(187) | No assignment to fifo_wr_q
@W:CG360 : rxcver.v(188) | No assignment to wire fifo_wr_pulse

@N:CL177 : rxcver.v(472) | Sharing sequential element sin_d0_delay.
@N:CG364 : txmitt.v(103) | Synthesizing module txmitt

	UART_WB_DAT_WIDTH=32'b00000000000000000000000000001000
	FIFO=32'b00000000000000000000000000000000
	start=3'b000
	shift=3'b001
	parity=3'b010
	stop_1bit=3'b011
	stop_2bit=3'b100
	stop_halfbit=3'b101
	start1=3'b110
   Generated name = txmitt_8s_0s_0_1_2_3_4_5_6

@W:CG133 : txmitt.v(150) | No assignment to tx_in_start_s
@W:CG133 : txmitt.v(155) | No assignment to txclk_ena
@W:CG133 : txmitt.v(156) | No assignment to txclk_enb
@W:CG133 : txmitt.v(158) | No assignment to count_v
@W:CG133 : txmitt.v(159) | No assignment to thr_rd_int
@W:CG133 : txmitt.v(160) | No assignment to thr_rd_delay
@W:CG133 : txmitt.v(161) | No assignment to last_word
@N:CG364 : uart_core.v(131) | Synthesizing module uart_core

	CLK_IN_MHZ=72'b001100100011010100101110001100000011000000110000001100000011000000110000
	UART_WB_ADR_WIDTH=32'b00000000000000000000000000000100
	UART_WB_DAT_WIDTH=32'b00000000000000000000000000001000
	BAUD_RATE=32'b00000000000000011100001000000000
	FIFO=32'b00000000000000000000000000000000
	LCR_DATA_BITS=32'b00000000000000000000000000001000
	LCR_STOP_BITS=32'b00000000000000000000000000000001
	LCR_PARITY_ENABLE=32'b00000000000000000000000000000000
	LCR_PARITY_ODD=32'b00000000000000000000000000000000
	LCR_PARITY_STICK=32'b00000000000000000000000000000000
	LCR_SET_BREAK=32'b00000000000000000000000000000000
	STDOUT_SIM=32'b00000000000000000000000000000000
	STDOUT_SIMFAST=32'b00000000000000000000000000000000
   Generated name = uart_core_Z2

@N:CG364 : pmi_def.v(210) | Synthesizing module pmi_pll_fp

@N:CG364 : pmi_def.v(154) | Synthesizing module pmi_fifo_dc

	pmi_data_width_w=32'b00000000000000000000000001000101
	pmi_data_width_r=32'b00000000000000000000000001000101
	pmi_data_depth_w=32'b00000000000000000000000000010000
	pmi_data_depth_r=32'b00000000000000000000000000010000
	pmi_full_flag=32'b00000000000000000000000000010000
	pmi_empty_flag=32'b00000000000000000000000000000000
	pmi_almost_full_flag=32'b00000000000000000000000000001111
	pmi_almost_empty_flag=32'b00000000000000000000000000000001
	pmi_regmode=40'b0110111001101111011100100110010101100111
	pmi_resetmode=40'b0110000101110011011110010110111001100011
	pmi_family=56'b01001101011000010110001101101000010110000100111100110010
	module_type=88'b0111000001101101011010010101111101100110011010010110011001101111010111110110010001100011
	pmi_implementation=24'b010011000101010101010100
   Generated name = pmi_fifo_dc_Z3

@N:CG364 : pmi_def.v(154) | Synthesizing module pmi_fifo_dc

	pmi_data_width_w=32'b00000000000000000000000000100000
	pmi_data_width_r=32'b00000000000000000000000000100000
	pmi_data_depth_w=32'b00000000000000000000000000010000
	pmi_data_depth_r=32'b00000000000000000000000000010000
	pmi_full_flag=32'b00000000000000000000000000010000
	pmi_empty_flag=32'b00000000000000000000000000000000
	pmi_almost_full_flag=32'b00000000000000000000000000001011
	pmi_almost_empty_flag=32'b00000000000000000000000000000001
	pmi_regmode=40'b0110111001101111011100100110010101100111
	pmi_resetmode=40'b0110000101110011011110010110111001100011
	pmi_family=56'b01001101011000010110001101101000010110000100111100110010
	module_type=88'b0111000001101101011010010101111101100110011010010110011001101111010111110110010001100011
	pmi_implementation=24'b010011000101010101010100
   Generated name = pmi_fifo_dc_Z4

@N:CG364 : wb_fifo_intf.v(54) | Synthesizing module wb_fifo_intf

@N:CG364 : sdr_ctrl.v(54) | Synthesizing module sdr_ctrl

@N:CG364 : sdr_sig.v(56) | Synthesizing module sdr_sig

@W:CL271 : sdr_sig.v(147) | Pruning bits 31 to 23 of sys_A[31:0] -- not in use ...

@N:CG364 : sdr_data.v(56) | Synthesizing module sdr_data

@N:CG364 : machxo2.v(82) | Synthesizing module BB

@W:CL271 : sdr_data.v(127) | Pruning bits 10 to 1 of rd_dat_cnt[10:0] -- not in use ...

@N:CG364 : sdr_fifo_intf.v(56) | Synthesizing module sdr_fifo_intf

@N:CG364 : wb_sdr_ctrl.v(57) | Synthesizing module wb_sdr_ctrl

	SYS_FREQ=32'b00110010001101010010111000110000
	SDRAM_FREQ=24'b001100010011000000110000
	LATTICE_FAMILY=56'b01001101011000010110001101101000010110000100111100110010
	LATTICE_DEVICE=24'b010000010110110001101100
	NUM_CLK_WAIT=32'b00000000000000000000000000000001
	NUM_CLK_CL=3'b011
	NUM_CLK_READ=32'b00000000000000000000000000000010
	NUM_CLK_WRITE=32'b00000000000000000000000000000010
	i_NOP=4'b0000
	i_PRE=4'b0001
	i_tRP=4'b0010
	i_AR1=4'b0011
	i_tRFC1=4'b0100
	i_AR2=4'b0101
	i_tRFC2=4'b0110
	i_MRS=4'b0111
	i_tMRD=4'b1000
	i_ready=4'b1001
	c_idle=4'b0000
	c_tRCD=4'b0001
	c_cl=4'b0010
	c_rdata=4'b0011
	c_wdata=4'b0100
	c_tRFC=4'b0101
	c_tDAL=4'b0110
	c_ACTIVE=4'b1000
	c_READA=4'b1111
	c_WRITEA=4'b1110
	c_AR=4'b1011
	c_ReWait=4'b1100
	c_PRECH=4'b1001
	c_tRP=4'b1010
	INHIBIT=4'b1111
	NOP=4'b0111
	ACTIVE=4'b0011
	READ=4'b0101
	WRITE=4'b0100
	BURST_TERMINATE=4'b0110
	PRECHARGE=4'b0010
	AUTO_REFRESH=4'b0001
	LOAD_MODE_REGISTER=4'b0000
	tDLY=32'b00000000000000000000000000000010
	READ_FIFO_DEPTH=32'b00000000000000000000000000010000
	READ_FIFO_ALMOST_FULL=32'b00000000000000000000000000001011
	WRITE_FIFO_DEPTH=32'b00000000000000000000000000010000
	WRITE_FIFO_ALMOST_EMPTY=32'b00000000000000000000000000000001
   Generated name = wb_sdr_ctrl_Z5

@N:CG179 : wb_sdr_ctrl.v(308) | Removing redundant assignment
@N:CG364 : platform_rev0.v(332) | Synthesizing module platform_rev0

@W:CG133 : platform_rev0.v(348) | No assignment to i
@W:CG360 : platform_rev0.v(364) | No assignment to wire SHAREDBUS_en

@W:CL157 : wb_sdr_ctrl.v(121) | *Output sdr_CLK has undriven bits -- simulation mismatch possible.
@W:CL247 : sdr_data.v(77) | Input port bit 68 of wb2sdr_q[68:0] is unused

@W:CL246 : sdr_data.v(77) | Input port bits 31 to 0 of wb2sdr_q[68:0] are unused

@W:CL159 : sdr_data.v(78) | Input sdr2wb_full is unused
@W:CL279 : sdr_sig.v(147) | Pruning register bits 1 to 0 of sys_A[22:0] 

@W:CL246 : sdr_sig.v(102) | Input port bits 68 to 23 of wb2sdr_q[68:0] are unused

@W:CL246 : sdr_sig.v(102) | Input port bits 1 to 0 of wb2sdr_q[68:0] are unused

@N:CL201 : sdr_ctrl.v(244) | Trying to extract state machine for register cState
Extracted state machine for register cState
State machine has 14 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   1000
   1001
   1010
   1011
   1100
   1110
   1111
@N:CL201 : sdr_ctrl.v(162) | Trying to extract state machine for register iState
Extracted state machine for register iState
State machine has 10 reachable states with original encodings of:
   0000
   0001
   0010
   0011
   0100
   0101
   0110
   0111
   1000
   1001
@W:CL246 : sdr_ctrl.v(82) | Input port bits 67 to 0 of wb2sdr_q[68:0] are unused

@N:CL201 : wb_fifo_intf.v(135) | Trying to extract state machine for register wb_status
Extracted state machine for register wb_status
State machine has 4 reachable states with original encodings of:
   00
   01
   10
   11
@W:CL159 : wb_fifo_intf.v(92) | Input S_BTE_I is unused
@W:CL159 : wb_fifo_intf.v(93) | Input S_LOCK_I is unused
@W:CL159 : wb_fifo_intf.v(103) | Input wb2sdr_empty is unused
@W:CL159 : uart_core.v(155) | Input UART_LOCK_I is unused
@W:CL159 : uart_core.v(160) | Input UART_SEL_I is unused
@N:CL201 : txmitt.v(333) | Trying to extract state machine for register genblk2.genblk1.tx_state
Extracted state machine for register genblk2.genblk1.tx_state
State machine has 7 reachable states with original encodings of:
   000
   001
   010
   011
   100
   101
   110
@W:CL159 : txmitt.v(135) | Input fifo_empty_thr is unused
@W:CL159 : txmitt.v(136) | Input fifo_full_thr is unused
@N:CL201 : rxcver.v(315) | Trying to extract state machine for register cs_state
Extracted state machine for register cs_state
State machine has 5 reachable states with original encodings of:
   000
   001
   010
   011
   100
@W:CL157 : rxcver.v(134) | *Output rbr_fifo has undriven bits -- simulation mismatch possible.
@W:CL157 : rxcver.v(141) | *Output fifo_empty has undriven bits -- simulation mismatch possible.
@W:CL157 : rxcver.v(142) | *Output fifo_almost_full has undriven bits -- simulation mismatch possible.
@N:CL201 : intface.v(874) | Trying to extract state machine for register genblk22.cs_state
Extracted state machine for register genblk22.cs_state
State machine has 4 reachable states with original encodings of:
   000
   001
   010
   011
@W:CL157 : intface.v(382) | *Output fifo_empty_thr has undriven bits -- simulation mismatch possible.
@W:CL157 : intface.v(383) | *Output fifo_full_thr has undriven bits -- simulation mismatch possible.
@W:CL159 : intface.v(344) | Input cti_i is unused
@W:CL159 : intface.v(345) | Input bte_i is unused
@W:CL159 : intface.v(355) | Input rbr_fifo is unused
@W:CL159 : intface.v(381) | Input fifo_empty is unused
@W:CL159 : intface.v(384) | Input thr_rd is unused
@W:CL159 : intface.v(385) | Input fifo_almost_full is unused
@W:CL246 : lm32_top.v(168) | Input port bits 31 to 14 of DEBUG_ADR_I[31:0] are unused

@W:CL246 : lm32_top.v(168) | Input port bits 12 to 11 of DEBUG_ADR_I[31:0] are unused

@W:CL246 : lm32_top.v(168) | Input port bits 1 to 0 of DEBUG_ADR_I[31:0] are unused

@W:CL159 : lm32_top.v(172) | Input DEBUG_CTI_I is unused
@W:CL159 : lm32_top.v(173) | Input DEBUG_BTE_I is unused
@W:CL159 : lm32_top.v(174) | Input DEBUG_LOCK_I is unused
@W:CL159 : jtag_lm32.v(60) | Input CONTROL_DATAN is unused
@N:CL201 : lm32_monitor.v(143) | Trying to extract state machine for register state
Extracted state machine for register state
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@N:CL134 : lm32_cpu.v(2664) | Found RAM registers, depth=32, width=32
@N:CL134 : lm32_cpu.v(2664) | Found RAM registers, depth=32, width=32
@W:CL159 : lm32_cpu.v(279) | Input I_RTY_I is unused
@W:CL246 : lm32_debug.v(123) | Input port bits 31 to 2 of csr_write_data[31:0] are unused

@W:CL247 : lm32_debug.v(123) | Input port bit 0 of csr_write_data[31:0] is unused

@W:CL159 : lm32_debug.v(118) | Input pc_x is unused
@W:CL159 : lm32_debug.v(119) | Input load_x is unused
@W:CL159 : lm32_debug.v(120) | Input store_x is unused
@W:CL159 : lm32_debug.v(121) | Input load_store_address_x is unused
@W:CL246 : lm32_jtag.v(151) | Input port bits 31 to 8 of csr_write_data[31:0] are unused

@W:CL159 : lm32_jtag.v(139) | Input jtag_clk is unused
@N:CL201 : lm32_mc_arithmetic.v(169) | Trying to extract state machine for register state
Extracted state machine for register state
State machine has 3 reachable states with original encodings of:
   000
   010
   011
@W:CL246 : lm32_shifter.v(79) | Input port bits 31 to 5 of operand_1_x[31:0] are unused

@W:CL246 : lm32_load_store_unit.v(159) | Input port bits 31 to 2 of load_store_address_x[31:0] are unused

@W:CL159 : lm32_load_store_unit.v(152) | Input stall_a is unused
@W:CL159 : lm32_load_store_unit.v(162) | Input load_x is unused
@W:CL159 : lm32_load_store_unit.v(163) | Input store_x is unused
@W:CL159 : lm32_load_store_unit.v(165) | Input store_q_x is unused
@W:CL159 : lm32_load_store_unit.v(182) | Input d_rty_i is unused
@W:CL159 : lm32_instruction_unit.v(204) | Input valid_f is unused
@W:CL159 : lm32_instruction_unit.v(206) | Input kill_f is unused
@N:CL201 : platform_rev0.v(246) | Trying to extract state machine for register selected
Extracted state machine for register selected
State machine has 3 reachable states with original encodings of:
   00
   01
   10
@END
Process took 0h:00m:04s realtime, 0h:00m:04s cputime
# Thu Jun 20 21:29:54 2013

###########################################################]

Premap Report Synopsys Lattice Technology Pre-mapping, Version maplat, Build 618R, Built Mar 14 2013 09:19:55 Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. Product Version G-2012.09L-SP1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) Linked File: prj_diamond_ver0_scck.rpt Printing clock summary report in "C:\work\project\artekit_demos\forza4_rev0\diamond\prj_diamond_ver0\prj_diamond_ver0_scck.rpt" file @N:MF249 : | Running in 32-bit mode. @N:MF666 : | Clock conversion enabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 53MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 52MB peak: 53MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 62MB peak: 62MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 62MB peak: 64MB) @W:BN132 : lm32_instruction_unit.v(792) | Removing sequential instance LM32.cpu.instruction_unit.i_stb_o, because it is equivalent to instance LM32.cpu.instruction_unit.i_cyc_o @W:BN132 : lm32_load_store_unit.v(623) | Removing sequential instance LM32.cpu.load_store_unit.d_stb_o, because it is equivalent to instance LM32.cpu.load_store_unit.d_cyc_o @W:BN132 : txmitt.v(528) | Removing sequential instance uart.u_txmitt.genblk5.thr_ready, because it is equivalent to instance uart.u_txmitt.genblk4.thr_empty @W:MT462 : jtag_lm32.v(3081) | Net LM32.jtag_cores.reg_update appears to be an unidentified clock source. Assuming default frequency. Clock Summary ************** Start Requested Requested Clock Clock Clock Frequency Period Type Group ----------------------------------------------------------------------------------------------------------- platform_rev0|clk_i 92.6 MHz 10.801 inferred Autoconstr_clkgroup_0 wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock 181.4 MHz 5.512 inferred Autoconstr_clkgroup_1 jtag_cores|jtck 1000.0 MHz 1.000 inferred Autoconstr_clkgroup_2 =========================================================================================================== @W:MT531 : lm32_jtag.v(274) | Found signal identified as System clock which controls 1 sequential elements including LM32.cpu.jtag.rx_toggle. Using this clock, which has no specified timing constraint, can prevent conversion of gated or generated clocks and can adversely impact design performance. @W:MT529 : platform_rev0.v(246) | Found inferred clock platform_rev0|clk_i which controls 1496 sequential elements including arbiter.locked. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. @W:MT529 : sdr_ctrl.v(244) | Found inferred clock wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock which controls 216 sequential elements including sdram.sdr_fifo_intf_uut.U1.cState_1[13:0]. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. @W:MT529 : typea.v(94) | Found inferred clock jtag_cores|jtck which controls 22 sequential elements including LM32.jtag_cores.jtag_lm32_inst.DATA_BIT0.DATA_OUT. This clock has no specified timing constraint which may prevent conversion of gated or generated clocks and may adversely impact design performance. syn_allowed_resources : blockrams=26 set on top level netlist platform_rev0 Finished Pre Mapping Phase.Pre-mapping successful! At Mapper Exit (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:00s; Memory used current: 46MB peak: 80MB) Process took 0h:00m:01s realtime, 0h:00m:01s cputime # Thu Jun 20 21:29:57 2013 ###########################################################] Map & Optimize Report Synopsys Lattice Technology Mapper, Version maplat, Build 618R, Built Mar 14 2013 09:19:55 Copyright (C) 1994-2012, Synopsys Inc. This software the associated documentation are confidential and proprietary to Synopsys, Inc. Your use or disclosure of this software subject to the terms and conditions of a written license agreement between you, or your company, and Synopsys, Inc. Product Version G-2012.09L-SP1 Mapper Startup Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) @N:MF249 : | Running in 32-bit mode. @N:MF666 : | Clock conversion enabled Design Input Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) Mapper Initialization Complete (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 48MB peak: 49MB) Start loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 58MB) Finished loading timing files (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 58MB peak: 60MB) Starting Optimization and Mapping (Real Time elapsed 0h:00m:00s; CPU Time elapsed 0h:00m:00s; Memory used current: 77MB peak: 79MB) @W:MO111 : intface.v(383) | Tristate driver fifo_full_thr on net fifo_full_thr has its enable tied to GND (module intface_Z1) @W:MO111 : intface.v(382) | Tristate driver fifo_empty_thr on net fifo_empty_thr has its enable tied to GND (module intface_Z1) @W:MO111 : rxcver.v(142) | Tristate driver fifo_almost_full on net fifo_almost_full has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_MachXO2) @W:MO111 : rxcver.v(141) | Tristate driver fifo_empty on net fifo_empty has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_MachXO2) @W:MO111 : rxcver.v(134) | Tristate driver rbr_fifo_1 on net rbr_fifo_1 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_MachXO2) @W:MO111 : rxcver.v(134) | Tristate driver rbr_fifo_2 on net rbr_fifo_2 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_MachXO2) @W:MO111 : rxcver.v(134) | Tristate driver rbr_fifo_3 on net rbr_fifo_3 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_MachXO2) @W:MO111 : rxcver.v(134) | Tristate driver rbr_fifo_4 on net rbr_fifo_4 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_MachXO2) @W:MO111 : rxcver.v(134) | Tristate driver rbr_fifo_5 on net rbr_fifo_5 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_MachXO2) @W:MO111 : rxcver.v(134) | Tristate driver rbr_fifo_6 on net rbr_fifo_6 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_MachXO2) @W:MO111 : rxcver.v(134) | Tristate driver rbr_fifo_7 on net rbr_fifo_7 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_MachXO2) @W:MO111 : rxcver.v(134) | Tristate driver rbr_fifo_8 on net rbr_fifo_8 has its enable tied to GND (module rxcver_8s_0s_0_1_2_3_4_MachXO2) @W:MO111 : | Tristate driver fifo_empty_thr_t on net fifo_empty_thr has its enable tied to GND (module uart_core_Z2) @W:MO111 : | Tristate driver fifo_full_thr_t on net fifo_full_thr has its enable tied to GND (module uart_core_Z2) @W:MO111 : | Tristate driver RBR_FIFO_t[0] on net RBR_FIFO[0] has its enable tied to GND (module uart_core_Z2) @W:MO111 : | Tristate driver RBR_FIFO_t[1] on net RBR_FIFO[1] has its enable tied to GND (module uart_core_Z2) @W:MO111 : | Tristate driver RBR_FIFO_t[2] on net RBR_FIFO[2] has its enable tied to GND (module uart_core_Z2) @W:MO111 : | Tristate driver RBR_FIFO_t[3] on net RBR_FIFO[3] has its enable tied to GND (module uart_core_Z2) @W:MO111 : | Tristate driver RBR_FIFO_t[4] on net RBR_FIFO[4] has its enable tied to GND (module uart_core_Z2) @W:MO111 : | Tristate driver RBR_FIFO_t[5] on net RBR_FIFO[5] has its enable tied to GND (module uart_core_Z2) @W:MO111 : | Tristate driver RBR_FIFO_t[6] on net RBR_FIFO[6] has its enable tied to GND (module uart_core_Z2) @W:MO111 : | Tristate driver RBR_FIFO_t[7] on net RBR_FIFO[7] has its enable tied to GND (module uart_core_Z2) @W:MO111 : | Tristate driver fifo_empty_t on net fifo_empty has its enable tied to GND (module uart_core_Z2) @W:MO111 : | Tristate driver fifo_almost_full_t on net fifo_almost_full has its enable tied to GND (module uart_core_Z2) @W:MO111 : wb_sdr_ctrl.v(121) | Tristate driver sdr_CLK on net sdr_CLK has its enable tied to GND (module wb_sdr_ctrl_Z5) @W:MO111 : | Tristate driver sdramsdr_CLK_t on net sdramsdr_CLK has its enable tied to GND (module platform_rev0) @N:BN362 : lm32_instruction_unit.v(583) | Removing sequential instance instruction_unit.pc_w[31:2] of view:PrimLib.dffr(prim) in hierarchy view:work.lm32_cpu(verilog) because there are no references to its outputs @W:BN132 : lm32_multiplier.v(98) | Removing sequential instance LM32.cpu.multiplier.multiplier[31:0], because it is equivalent to instance LM32.cpu.operand_1_x[31:0] @W:BN132 : lm32_multiplier.v(98) | Removing sequential instance LM32.cpu.multiplier.muliplicand[31:0], because it is equivalent to instance LM32.cpu.operand_0_x[31:0] Available hyper_sources - for debug and ip models None Found @W:MT462 : jtag_lm32.v(3081) | Net LM32.jtag_cores.reg_update appears to be an unidentified clock source. Assuming default frequency. @N:MT206 : | Auto Constrain mode is enabled Finished RTL optimizations (Real Time elapsed 0h:00m:01s; CPU Time elapsed 0h:00m:01s; Memory used current: 78MB peak: 79MB) Encoding state machine selected[2:0] (view:work.arbiter2_32s_32s_32s_32s(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @N:MF135 : lm32_cpu.v(2664) | Found RAM 'registers_1[31:0]', 32 words by 32 bits @N:MF135 : lm32_cpu.v(2664) | Found RAM 'registers[31:0]', 32 words by 32 bits @N:MF179 : lm32_cpu.v(1585) | Found 32 bit by 32 bit '==' comparator, 'cmp_zero' @N:MF179 : lm32_cpu.v(1485) | Found 5 bit by 5 bit '==' comparator, 'un1_raw_x_0' @N:MF179 : lm32_cpu.v(1486) | Found 5 bit by 5 bit '==' comparator, 'un1_raw_m_0' @N:MF179 : lm32_cpu.v(1487) | Found 5 bit by 5 bit '==' comparator, 'un1_raw_w_0' @N:MF179 : lm32_cpu.v(1488) | Found 5 bit by 5 bit '==' comparator, 'un1_raw_x_1' @N:MF179 : lm32_cpu.v(1489) | Found 5 bit by 5 bit '==' comparator, 'un1_raw_m_1' @N:MF179 : lm32_cpu.v(1490) | Found 5 bit by 5 bit '==' comparator, 'un1_raw_w_1' @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_26, because it is equivalent to instance LM32.cpu.registers_1rff_26 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_27, because it is equivalent to instance LM32.cpu.registers_1rff_27 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_28, because it is equivalent to instance LM32.cpu.registers_1rff_28 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_29, because it is equivalent to instance LM32.cpu.registers_1rff_29 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_30, because it is equivalent to instance LM32.cpu.registers_1rff_30 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_31, because it is equivalent to instance LM32.cpu.registers_1rff_31 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_0, because it is equivalent to instance LM32.cpu.registers_1rff_0 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_1, because it is equivalent to instance LM32.cpu.registers_1rff_1 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_2, because it is equivalent to instance LM32.cpu.registers_1rff_2 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_3, because it is equivalent to instance LM32.cpu.registers_1rff_3 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_4, because it is equivalent to instance LM32.cpu.registers_1rff_4 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_5, because it is equivalent to instance LM32.cpu.registers_1rff_5 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_6, because it is equivalent to instance LM32.cpu.registers_1rff_6 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_7, because it is equivalent to instance LM32.cpu.registers_1rff_7 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_8, because it is equivalent to instance LM32.cpu.registers_1rff_8 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_9, because it is equivalent to instance LM32.cpu.registers_1rff_9 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_10, because it is equivalent to instance LM32.cpu.registers_1rff_10 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_11, because it is equivalent to instance LM32.cpu.registers_1rff_11 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_12, because it is equivalent to instance LM32.cpu.registers_1rff_12 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_13, because it is equivalent to instance LM32.cpu.registers_1rff_13 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_14, because it is equivalent to instance LM32.cpu.registers_1rff_14 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_15, because it is equivalent to instance LM32.cpu.registers_1rff_15 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_16, because it is equivalent to instance LM32.cpu.registers_1rff_16 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_17, because it is equivalent to instance LM32.cpu.registers_1rff_17 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_18, because it is equivalent to instance LM32.cpu.registers_1rff_18 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_19, because it is equivalent to instance LM32.cpu.registers_1rff_19 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_20, because it is equivalent to instance LM32.cpu.registers_1rff_20 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_21, because it is equivalent to instance LM32.cpu.registers_1rff_21 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_22, because it is equivalent to instance LM32.cpu.registers_1rff_22 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_23, because it is equivalent to instance LM32.cpu.registers_1rff_23 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_24, because it is equivalent to instance LM32.cpu.registers_1rff_24 @W:BN132 : lm32_cpu.v(2664) | Removing instance LM32.cpu.registersrff_25, because it is equivalent to instance LM32.cpu.registers_1rff_25 Encoding state machine state[2:0] (view:work.lm32_mc_arithmetic(verilog)) original code -> new code 000 -> 00 010 -> 01 011 -> 10 @N: : lm32_mc_arithmetic.v(169) | Found counter in view:work.lm32_mc_arithmetic(verilog) inst cycles[5:0] Encoding state machine state[2:0] (view:work.lm32_monitor(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 @W:BN132 : lm32_monitor.v(143) | Removing instance LM32.debug_rom.MON_ACK_O, because it is equivalent to instance LM32.debug_rom.state[1] Encoding state machine genblk22\.cs_state[3:0] (view:work.intface_Z1(verilog)) original code -> new code 000 -> 00 001 -> 01 010 -> 10 011 -> 11 Encoding state machine cs_state[4:0] (view:work.rxcver_8s_0s_0_1_2_3_4_MachXO2(verilog)) original code -> new code 000 -> 00001 001 -> 00010 010 -> 00100 011 -> 01000 100 -> 10000 @N: : rxcver.v(315) | Found counter in view:work.rxcver_8s_0s_0_1_2_3_4_MachXO2(verilog) inst databit_recved_num[3:0] @N:MF179 : rxcver.v(332) | Found 16 bit by 16 bit '==' comparator, 'cs_state12' Encoding state machine genblk2\.genblk1\.tx_state[6:0] (view:work.txmitt_8s_0s_0_1_2_3_4_5_6(verilog)) original code -> new code 000 -> 0000001 001 -> 0000010 010 -> 0000100 011 -> 0001000 100 -> 0010000 101 -> 0100000 110 -> 1000000 @N: : txmitt.v(333) | Found counter in view:work.txmitt_8s_0s_0_1_2_3_4_5_6(verilog) inst genblk2\.genblk1\.counter[15:0] Encoding state machine wb_status[3:0] (view:work.wb_fifo_intf(verilog)) original code -> new code 00 -> 00 01 -> 01 10 -> 10 11 -> 11 Encoding state machine cState_1[13:0] (view:work.sdr_ctrl(verilog)) original code -> new code 0000 -> 00000000000001 0001 -> 00000000000010 0010 -> 00000000000100 0011 -> 00000000001000 0100 -> 00000000010000 0101 -> 00000000100000 0110 -> 00000001000000 1000 -> 00000010000000 1001 -> 00000100000000 1010 -> 00001000000000 1011 -> 00010000000000 1100 -> 00100000000000 1110 -> 01000000000000 1111 -> 10000000000000 Encoding state machine iState_1[9:0] (view:work.sdr_ctrl(verilog)) original code -> new code 0000 -> 0000000001 0001 -> 0000000010 0010 -> 0000000100 0011 -> 0000001000 0100 -> 0000010000 0101 -> 0000100000 0110 -> 0001000000 0111 -> 0010000000 1000 -> 0100000000 1001 -> 1000000000 @N: : sdr_ctrl.v(206) | Found counter in view:work.sdr_ctrl(verilog) inst rd_cmd_cnt[10:0] @N:MF179 : sdr_sig.v(162) | Found 14 bit by 14 bit '==' comparator, 'un6_cross_page' @W:BN132 : sdr_sig.v(147) | Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[13], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[22] @W:BN132 : sdr_sig.v(147) | Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[2], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[11] @W:BN132 : sdr_sig.v(147) | Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[5], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[14] @W:BN132 : sdr_sig.v(147) | Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[9], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[18] @W:BN132 : sdr_sig.v(147) | Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[12], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[21] @W:BN132 : sdr_sig.v(147) | Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[0], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[9] @W:BN132 : sdr_sig.v(147) | Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[1], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[10] @W:BN132 : sdr_sig.v(147) | Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[3], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[12] @W:BN132 : sdr_sig.v(147) | Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[4], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[13] @W:BN132 : sdr_sig.v(147) | Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[6], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[15] @W:BN132 : sdr_sig.v(147) | Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[7], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[16] @W:BN132 : sdr_sig.v(147) | Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[8], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[17] @W:BN132 : sdr_sig.v(147) | Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[10], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[19] @W:BN132 : sdr_sig.v(147) | Removing instance sdram.sdr_fifo_intf_uut.U2.row_addr[11], because it is equivalent to instance sdram.sdr_fifo_intf_uut.U2.sys_A[20] @W:BN132 : lm32_cpu.v(2303) | Removing instance LM32.cpu.condition_x[2], because it is equivalent to instance LM32.cpu.logic_op_x[2] @W:BN132 : lm32_cpu.v(2303) | Removing instance LM32.cpu.sign_extend_x, because it is equivalent to instance LM32.cpu.logic_op_x[2] @W:BN132 : lm32_cpu.v(2303) | Removing instance LM32.cpu.w_result_sel_load_x, because it is equivalent to instance LM32.cpu.load_x @W:BN132 : lm32_cpu.v(2303) | Removing instance LM32.cpu.condition_x[1], because it is equivalent to instance LM32.cpu.logic_op_x[1] @W:BN132 : lm32_cpu.v(2303) | Removing instance LM32.cpu.size_x[1], because it is equivalent to instance LM32.cpu.logic_op_x[1] @W:BN132 : lm32_cpu.v(2303) | Removing instance LM32.cpu.condition_x[0], because it is equivalent to instance LM32.cpu.logic_op_x[0] @W:BN132 : lm32_cpu.v(2303) | Removing instance LM32.cpu.size_x[0], because it is equivalent to instance LM32.cpu.logic_op_x[0] @W:BN132 : lm32_cpu.v(2303) | Removing instance LM32.cpu.logic_op_x[3], because it is equivalent to instance LM32.cpu.direction_x @W:BN132 : lm32_instruction_unit.v(792) | Removing instance LM32.cpu.instruction_unit.i_adr_o_1[27], because it is equivalent to instance LM32.cpu.instruction_unit.pc_f[27] @W:BN132 : lm32_instruction_unit.v(792) | Removing instance LM32.cpu.instruction_unit.i_adr_o_1[28], because it is equivalent to instance LM32.cpu.instruction_unit.pc_f[28] @W:BN132 : lm32_instruction_unit.v(792) | Removing instance LM32.cpu.instruction_unit.i_adr_o_1[29], because it is equivalent to instance LM32.cpu.instruction_unit.pc_f[29] @W:BN132 : lm32_instruction_unit.v(792) | Removing instance LM32.cpu.instruction_unit.i_adr_o_1[30], because it is equivalent to instance LM32.cpu.instruction_unit.pc_f[30] @W:BN132 : lm32_instruction_unit.v(792) | Removing instance LM32.cpu.instruction_unit.i_adr_o_1[31], because it is equivalent to instance LM32.cpu.instruction_unit.pc_f[31] @W:BN132 : lm32_instruction_unit.v(792) | Removing instance LM32.cpu.instruction_unit.i_adr_o_1[25], because it is equivalent to instance LM32.cpu.instruction_unit.pc_f[25] @W:BN132 : lm32_instruction_unit.v(792) | Removing instance LM32.cpu.instruction_unit.i_adr_o_1[26], because it is equivalent to instance LM32.cpu.instruction_unit.pc_f[26] Finished factoring (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 95MB peak: 96MB) Finished gated-clock and generated-clock conversion (Real Time elapsed 0h:00m:06s; CPU Time elapsed 0h:00m:05s; Memory used current: 90MB peak: 97MB) Finished generic timing optimizations - Pass 1 (Real Time elapsed 0h:00m:07s; CPU Time elapsed 0h:00m:06s; Memory used current: 89MB peak: 97MB) @N:FA113 : sdr_sig.v(145) | Pipelining module next_adr[22:2] @N:MF169 : sdr_sig.v(147) | Register sys_A[22:2] pushed in. @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[5] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[4] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[3] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[2] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[1] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[20] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[19] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[18] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[17] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[16] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[15] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[14] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[13] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[12] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[11] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[10] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[9] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[8] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[7] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[6] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[31] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[30] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[29] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[28] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[27] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[26] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[25] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[24] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[23] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[22] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:BN362 : lm32_interrupt.v(219) | Removing sequential instance LM32.cpu.interrupt.genblk2\.ip[21] in hierarchy view:work.platform_rev0(verilog) because there are no references to its outputs @N:FA113 : lm32_multiplier.v(115) | Pipelining module product_2[31:0] @N:MF169 : lm32_multiplier.v(98) | Register product[31:0] pushed in. @N:FX404 : lm32_instruction_unit.v(511) | Found addmux in view:work.platform_rev0(verilog) inst LM32.cpu.instruction_unit.pc_a_19_1267_i_m4_0[29:0] from LM32.cpu.instruction_unit.un7_pc_a[29:0] @N:FX404 : rxcver.v(324) | Found addmux in view:work.platform_rev0(verilog) inst uart.u_rxcver.counter_11_i_m2[15:0] from uart.u_rxcver.un1_counter_2[15:0] Starting Early Timing Optimization (Real Time elapsed 0h:00m:11s; CPU Time elapsed 0h:00m:10s; Memory used current: 91MB peak: 97MB) Finished Early Timing Optimization (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:15s; Memory used current: 94MB peak: 97MB) Finished generic timing optimizations - Pass 2 (Real Time elapsed 0h:00m:16s; CPU Time elapsed 0h:00m:15s; Memory used current: 93MB peak: 97MB) Finished preparing to map (Real Time elapsed 0h:00m:18s; CPU Time elapsed 0h:00m:17s; Memory used current: 94MB peak: 97MB) Finished technology mapping (Real Time elapsed 0h:00m:22s; CPU Time elapsed 0h:00m:21s; Memory used current: 131MB peak: 139MB) Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:21s -4.05ns 2460 / 1673 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:24s -4.05ns 2478 / 1673 ------------------------------------------------------------ Pass CPU time Worst Slack Luts / Registers ------------------------------------------------------------ 1 0h:00m:25s -4.05ns 2482 / 1673 2 0h:00m:25s -4.05ns 2483 / 1673 3 0h:00m:25s -4.05ns 2483 / 1673 ------------------------------------------------------------ Finished technology timing optimizations and critical path resynthesis (Real Time elapsed 0h:00m:27s; CPU Time elapsed 0h:00m:25s; Memory used current: 101MB peak: 139MB) @N:FX164 : | The option to pack flops in the IOB has not been specified @W:MO111 : platform_rev0.v(422) | Tristate driver sdramsdr_CLK_obuft.un1[0] on net sdramsdr_CLK has its enable tied to GND (module platform_rev0) @N:FO126 : lm32_cpu.v(2664) | Generating RAM LM32.cpu.registers_1[31:0] @N:FO126 : lm32_cpu.v(2664) | Generating RAM LM32.cpu.registers[31:0] Finished restoring hierarchy (Real Time elapsed 0h:00m:30s; CPU Time elapsed 0h:00m:28s; Memory used current: 103MB peak: 139MB) #### START OF CLOCK OPTIMIZATION REPORT #####[ 1 non-gated/non-generated clock tree(s) driving 1467 clock pin(s) of sequential element(s) 3 gated/generated clock tree(s) driving 246 clock pin(s) of sequential element(s) 0 instances converted, 246 sequential instances remain driven by gated/generated clocks =========================== Non-Gated/Non-Generated Clocks ============================ Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance --------------------------------------------------------------------------------------- ClockId0004 clk_i port 1467 counter[0] ======================================================================================= ============================================================================================================================== Gated/Generated Clocks ============================================================================================================================== Clock Tree ID Driving Element Drive Element Type Fanout Sample Instance Explanation ------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------ ClockId0001 sdram.U1_pmi_pll pmi_pll_fp 223 sdram.sys_dly_cnt[15] Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements ClockId0002 LM32.jtag_cores.jtagconn16_lm32_inst jtagconn16 22 LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT2.tdoInt Gating structure creates improper gating logic. See the Gated Clocks description in the user guide for conversion requirements ClockId0003 LM32.jtag_cores.jtag_lm32_inst.REG_UPDATE ORCALUT4 1 LM32.cpu.jtag.rx_toggle No clocks found on inputs ==================================================================================================================================================================================================================================================================================== ##### END OF CLOCK OPTIMIZATION REPORT ######] Writing Analyst data base C:\work\project\artekit_demos\forza4_rev0\diamond\prj_diamond_ver0\prj_diamond_ver0.srm Finished Writing Netlist Databases (Real Time elapsed 0h:00m:32s; CPU Time elapsed 0h:00m:30s; Memory used current: 104MB peak: 139MB) Writing EDIF Netlist and constraint files G-2012.09L-SP1 @N:BW106 : | Synplicity Constraint File capacitance units using default value of 1pF @W: : | Block-path constraint from CLKNET "jtag_cores|jtck" to PORT "platform_rev0|clk_i" not forward annotated in -lpf file. @W: : | Block-path constraint from CLKNET "wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock" to PORT "platform_rev0|clk_i" not forward annotated in -lpf file. @W: : | Block-path constraint from PORT "platform_rev0|clk_i" to CLKNET "jtag_cores|jtck" not forward annotated in -lpf file. @W: : | Block-path constraint from PORT "platform_rev0|clk_i" to CLKNET "wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock" not forward annotated in -lpf file. Finished Writing EDIF Netlist and constraint files (Real Time elapsed 0h:00m:33s; CPU Time elapsed 0h:00m:31s; Memory used current: 108MB peak: 139MB) @W:MT246 : wb_sdr_ctrl.v(361) | Blackbox pmi_fifo_dc_Z4 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : wb_sdr_ctrl.v(333) | Blackbox pmi_fifo_dc_Z3 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : wb_sdr_ctrl.v(155) | Blackbox pmi_pll_fp is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : lm32_addsub.v(102) | Blackbox pmi_addsub_32s_32s_off_MachXO2_pmi_addsub is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT246 : jtag_cores.v(126) | Blackbox jtagconn16 is missing a user supplied timing model. This may have a negative effect on timing analysis and optimizations (Quality of Results) @W:MT420 : | Found inferred clock platform_rev0|clk_i with period 10.32ns. Please declare a user-defined clock on object "p:clk_i" @W:MT420 : | Found inferred clock wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock with period 6.96ns. Please declare a user-defined clock on object "n:sdram.sdr_clk_c" @W:MT420 : | Found inferred clock jtag_cores|jtck with period 1.34ns. Please declare a user-defined clock on object "n:LM32.jtag_cores.jtck" ##### START OF TIMING REPORT #####[ # Timing Report written on Thu Jun 20 21:30:32 2013 # Top view: platform_rev0 Requested Frequency: 96.9 MHz Wire load mode: top Paths requested: 5 Constraint File(s): @N:MT320 : | Timing report estimates place and route data. Please look at the place and route timing report for final timing. @N:MT322 : | Clock constraints cover only FF-to-FF paths associated with the clock. Performance Summary ******************* Worst slack in design: -1.822 Requested Estimated Requested Estimated Clock Clock Starting Clock Frequency Frequency Period Period Slack Type Group ------------------------------------------------------------------------------------------------------------------------------------------------- jtag_cores|jtck 748.5 MHz 636.2 MHz 1.336 1.572 -0.236 inferred Autoconstr_clkgroup_2 platform_rev0|clk_i 96.9 MHz 82.3 MHz 10.323 12.145 -1.822 inferred Autoconstr_clkgroup_0 wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock 143.7 MHz 122.1 MHz 6.960 8.188 -1.228 inferred Autoconstr_clkgroup_1 System 364.6 MHz 376.2 MHz 2.743 2.658 0.084 system system_clkgroup ================================================================================================================================================= Clock Relationships ******************* Clocks | rise to rise | fall to fall | rise to fall | fall to rise -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- Starting Ending | constraint slack | constraint slack | constraint slack | constraint slack -------------------------------------------------------------------------------------------------------------------------------------------------------------------------- System System | 2.743 0.084 | No paths - | No paths - | No paths - System platform_rev0|clk_i | 10.323 4.711 | No paths - | No paths - | No paths - System wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock | 6.960 0.370 | No paths - | No paths - | No paths - System jtag_cores|jtck | No paths - | No paths - | 1.336 0.416 | No paths - platform_rev0|clk_i System | 10.323 3.559 | No paths - | No paths - | No paths - platform_rev0|clk_i platform_rev0|clk_i | 10.323 -1.822 | No paths - | No paths - | No paths - platform_rev0|clk_i wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock | Diff grp - | No paths - | No paths - | No paths - platform_rev0|clk_i jtag_cores|jtck | No paths - | No paths - | Diff grp - | No paths - wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock System | 6.960 0.632 | No paths - | No paths - | No paths - wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock platform_rev0|clk_i | Diff grp - | No paths - | No paths - | No paths - wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock | 6.960 -1.228 | No paths - | No paths - | No paths - jtag_cores|jtck System | No paths - | No paths - | No paths - | 1.336 0.292 jtag_cores|jtck platform_rev0|clk_i | No paths - | No paths - | No paths - | Diff grp - jtag_cores|jtck jtag_cores|jtck | No paths - | 1.336 -0.236 | No paths - | No paths - ========================================================================================================================================================================== Note: 'No paths' indicates there are no paths in the design for that pair of clock edges. 'Diff grp' indicates that paths exist but the starting clock and ending clock are in different clock groups. Interface Information ********************* No IO constraint found ==================================== Detailed Report for Clock: jtag_cores|jtck ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ---------------------------------------------------------------------------------------------------------------------------- LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT1.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[9] 1.044 -0.236 LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT0.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[8] 1.044 -0.236 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT7.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[7] 1.044 -0.236 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT6.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[6] 1.044 -0.236 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT5.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[5] 1.044 -0.236 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT4.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[4] 1.044 -0.236 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT3.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[3] 1.044 -0.236 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT2.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[2] 1.044 -0.236 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT1.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[1] 1.044 -0.236 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT0.tdoInt jtag_cores|jtck FD1P3DX Q tdibus[0] 1.044 -0.236 ============================================================================================================================ Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock -------------------------------------------------------------------------------------------------------------------------------- LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT2.tdoInt jtag_cores|jtck FD1P3DX D N_37_i 1.425 -0.236 LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT1.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_8 1.425 -0.236 LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT0.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_7 1.425 -0.236 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT7.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_6 1.425 -0.236 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT6.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_5 1.425 -0.236 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT5.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_4 1.425 -0.236 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT4.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_3 1.425 -0.236 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT3.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_2 1.425 -0.236 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT2.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_1 1.425 -0.236 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT1.tdoInt jtag_cores|jtck FD1P3DX D tdoInt_RNO_0 1.425 -0.236 ================================================================================================================================ Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 1.336 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) = Required time: 1.425 - Propagation time: 1.661 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.236 Number of logic level(s): 1 Starting point: LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT1.tdoInt / Q Ending point: LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT2.tdoInt / D The start point is clocked by jtag_cores|jtck [falling] on pin CK The end point is clocked by jtag_cores|jtck [falling] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT1.tdoInt FD1P3DX Q Out 1.044 1.044 - tdibus[9] Net - - - - 2 LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT2.tdoInt_RNO ORCALUT4 B In 0.000 1.044 - LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT2.tdoInt_RNO ORCALUT4 Z Out 0.617 1.661 - N_37_i Net - - - - 1 LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT2.tdoInt FD1P3DX D In 0.000 1.661 - ====================================================================================================================== Path information for path number 2: Requested Period: 1.336 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) = Required time: 1.425 - Propagation time: 1.661 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.236 Number of logic level(s): 1 Starting point: LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT0.tdoInt / Q Ending point: LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT1.tdoInt / D The start point is clocked by jtag_cores|jtck [falling] on pin CK The end point is clocked by jtag_cores|jtck [falling] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT0.tdoInt FD1P3DX Q Out 1.044 1.044 - tdibus[8] Net - - - - 2 LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT1.tdoInt_RNO ORCALUT4 B In 0.000 1.044 - LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT1.tdoInt_RNO ORCALUT4 Z Out 0.617 1.661 - tdoInt_RNO_8 Net - - - - 1 LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT1.tdoInt FD1P3DX D In 0.000 1.661 - ====================================================================================================================== Path information for path number 3: Requested Period: 1.336 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) = Required time: 1.425 - Propagation time: 1.661 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.236 Number of logic level(s): 1 Starting point: LM32.jtag_cores.jtag_lm32_inst.DATA_BIT7.tdoInt / Q Ending point: LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT0.tdoInt / D The start point is clocked by jtag_cores|jtck [falling] on pin CK The end point is clocked by jtag_cores|jtck [falling] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- LM32.jtag_cores.jtag_lm32_inst.DATA_BIT7.tdoInt FD1P3DX Q Out 1.044 1.044 - tdibus[7] Net - - - - 2 LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT0.tdoInt_RNO ORCALUT4 B In 0.000 1.044 - LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT0.tdoInt_RNO ORCALUT4 Z Out 0.617 1.661 - tdoInt_RNO_7 Net - - - - 1 LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT0.tdoInt FD1P3DX D In 0.000 1.661 - ====================================================================================================================== Path information for path number 4: Requested Period: 1.336 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) = Required time: 1.425 - Propagation time: 1.661 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.236 Number of logic level(s): 1 Starting point: LM32.jtag_cores.jtag_lm32_inst.DATA_BIT6.tdoInt / Q Ending point: LM32.jtag_cores.jtag_lm32_inst.DATA_BIT7.tdoInt / D The start point is clocked by jtag_cores|jtck [falling] on pin CK The end point is clocked by jtag_cores|jtck [falling] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- LM32.jtag_cores.jtag_lm32_inst.DATA_BIT6.tdoInt FD1P3DX Q Out 1.044 1.044 - tdibus[6] Net - - - - 2 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT7.tdoInt_RNO ORCALUT4 B In 0.000 1.044 - LM32.jtag_cores.jtag_lm32_inst.DATA_BIT7.tdoInt_RNO ORCALUT4 Z Out 0.617 1.661 - tdoInt_RNO_6 Net - - - - 1 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT7.tdoInt FD1P3DX D In 0.000 1.661 - ====================================================================================================================== Path information for path number 5: Requested Period: 1.336 - Setup time: -0.089 + Clock delay at ending point: 0.000 (ideal) = Required time: 1.425 - Propagation time: 1.661 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -0.236 Number of logic level(s): 1 Starting point: LM32.jtag_cores.jtag_lm32_inst.DATA_BIT5.tdoInt / Q Ending point: LM32.jtag_cores.jtag_lm32_inst.DATA_BIT6.tdoInt / D The start point is clocked by jtag_cores|jtck [falling] on pin CK The end point is clocked by jtag_cores|jtck [falling] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ---------------------------------------------------------------------------------------------------------------------- LM32.jtag_cores.jtag_lm32_inst.DATA_BIT5.tdoInt FD1P3DX Q Out 1.044 1.044 - tdibus[5] Net - - - - 2 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT6.tdoInt_RNO ORCALUT4 B In 0.000 1.044 - LM32.jtag_cores.jtag_lm32_inst.DATA_BIT6.tdoInt_RNO ORCALUT4 Z Out 0.617 1.661 - tdoInt_RNO_5 Net - - - - 1 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT6.tdoInt FD1P3DX D In 0.000 1.661 - ====================================================================================================================== ==================================== Detailed Report for Clock: platform_rev0|clk_i ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------- LM32.cpu.multiplier.product_pipe_16 platform_rev0|clk_i FD1P3DX Q product_2_madd_24 1.044 -1.822 LM32.cpu.multiplier.product_pipe_131 platform_rev0|clk_i FD1P3DX Q product_2_madd_17f[4] 1.044 -1.822 LM32.cpu.multiplier.product_pipe_104 platform_rev0|clk_i FD1P3DX Q product_2_madd_16f[5] 0.972 -1.607 LM32.cpu.multiplier.product_pipe_105 platform_rev0|clk_i FD1P3DX Q product_2_madd_16f[6] 0.972 -1.607 LM32.cpu.multiplier.product_pipe_132 platform_rev0|clk_i FD1P3DX Q product_2_madd_17f[5] 0.972 -1.607 LM32.cpu.multiplier.product_pipe_133 platform_rev0|clk_i FD1P3DX Q product_2_madd_17f[6] 0.972 -1.607 LM32.cpu.multiplier.product_pipe_106 platform_rev0|clk_i FD1P3DX Q product_2_madd_16f[7] 0.972 -1.392 LM32.cpu.multiplier.product_pipe_107 platform_rev0|clk_i FD1P3DX Q product_2_madd_16f[8] 0.972 -1.392 LM32.cpu.multiplier.product_pipe_134 platform_rev0|clk_i FD1P3DX Q product_2_madd_17f[7] 0.972 -1.392 LM32.cpu.multiplier.product_pipe_135 platform_rev0|clk_i FD1P3DX Q product_2_madd_18f[8] 0.972 -1.392 ================================================================================================================================= Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ------------------------------------------------------------------------------------------------------------------ LM32.cpu.multiplier.result[31] platform_rev0|clk_i FD1S3DX D product[31] 10.217 -1.822 LM32.cpu.multiplier.result[29] platform_rev0|clk_i FD1S3DX D product[29] 10.217 -1.679 LM32.cpu.multiplier.result[30] platform_rev0|clk_i FD1S3DX D product[30] 10.217 -1.679 LM32.cpu.multiplier.result[27] platform_rev0|clk_i FD1S3DX D product[27] 10.217 -1.536 LM32.cpu.multiplier.result[28] platform_rev0|clk_i FD1S3DX D product[28] 10.217 -1.536 LM32.cpu.multiplier.result[25] platform_rev0|clk_i FD1S3DX D product[25] 10.217 -1.393 LM32.cpu.multiplier.result[26] platform_rev0|clk_i FD1S3DX D product[26] 10.217 -1.393 LM32.cpu.multiplier.result[23] platform_rev0|clk_i FD1S3DX D product[23] 10.217 -1.250 LM32.cpu.multiplier.result[24] platform_rev0|clk_i FD1S3DX D product[24] 10.217 -1.250 LM32.cpu.multiplier.result[21] platform_rev0|clk_i FD1S3DX D product[21] 10.217 -1.108 ================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 10.323 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.217 - Propagation time: 12.039 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.822 Number of logic level(s): 17 Starting point: LM32.cpu.multiplier.product_pipe_16 / Q Ending point: LM32.cpu.multiplier.result[31] / D The start point is clocked by platform_rev0|clk_i [rising] on pin CK The end point is clocked by platform_rev0|clk_i [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------- LM32.cpu.multiplier.product_pipe_16 FD1P3DX Q Out 1.044 1.044 - product_2_madd_24 Net - - - - 2 LM32.cpu.multiplier.product_2_madd_24_cry_0_0 CCU2D A1 In 0.000 1.044 - LM32.cpu.multiplier.product_2_madd_24_cry_0_0 CCU2D COUT Out 1.545 2.588 - product_2_madd_24_cry_0 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_24_cry_1_0 CCU2D CIN In 0.000 2.588 - LM32.cpu.multiplier.product_2_madd_24_cry_1_0 CCU2D COUT Out 0.143 2.731 - product_2_madd_24_cry_2 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_24_cry_3_0 CCU2D CIN In 0.000 2.731 - LM32.cpu.multiplier.product_2_madd_24_cry_3_0 CCU2D S1 Out 1.621 4.352 - product_2_madd_24[8] Net - - - - 2 LM32.cpu.multiplier.product_2_madd_28_cry_0_0 CCU2D B1 In 0.000 4.352 - LM32.cpu.multiplier.product_2_madd_28_cry_0_0 CCU2D COUT Out 1.545 5.897 - product_2_madd_28_cry_0 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_28_cry_1_0 CCU2D CIN In 0.000 5.897 - LM32.cpu.multiplier.product_2_madd_28_cry_1_0 CCU2D COUT Out 0.143 6.039 - product_2_madd_28_cry_2 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_28_cry_3_0 CCU2D CIN In 0.000 6.039 - LM32.cpu.multiplier.product_2_madd_28_cry_3_0 CCU2D COUT Out 0.143 6.182 - product_2_madd_28_cry_4 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_28_cry_5_0 CCU2D CIN In 0.000 6.182 - LM32.cpu.multiplier.product_2_madd_28_cry_5_0 CCU2D COUT Out 0.143 6.325 - product_2_madd_28_cry_6 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_28_cry_7_0 CCU2D CIN In 0.000 6.325 - LM32.cpu.multiplier.product_2_madd_28_cry_7_0 CCU2D S1 Out 1.621 7.946 - product_2_madd Net - - - - 2 LM32.cpu.multiplier.product_2_madd_cry_0_0 CCU2D A1 In 0.000 7.946 - LM32.cpu.multiplier.product_2_madd_cry_0_0 CCU2D COUT Out 1.545 9.491 - product_2_madd_cry_0 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_1_0 CCU2D CIN In 0.000 9.491 - LM32.cpu.multiplier.product_2_madd_cry_1_0 CCU2D COUT Out 0.143 9.633 - product_2_madd_cry_2 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_3_0 CCU2D CIN In 0.000 9.633 - LM32.cpu.multiplier.product_2_madd_cry_3_0 CCU2D COUT Out 0.143 9.776 - product_2_madd_cry_4 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_5_0 CCU2D CIN In 0.000 9.776 - LM32.cpu.multiplier.product_2_madd_cry_5_0 CCU2D COUT Out 0.143 9.919 - product_2_madd_cry_6 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_7_0 CCU2D CIN In 0.000 9.919 - LM32.cpu.multiplier.product_2_madd_cry_7_0 CCU2D COUT Out 0.143 10.062 - product_2_madd_cry_8 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_9_0 CCU2D CIN In 0.000 10.062 - LM32.cpu.multiplier.product_2_madd_cry_9_0 CCU2D COUT Out 0.143 10.204 - product_2_madd_cry_10 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_11_0 CCU2D CIN In 0.000 10.204 - LM32.cpu.multiplier.product_2_madd_cry_11_0 CCU2D COUT Out 0.143 10.347 - product_2_madd_cry_12 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_13_0 CCU2D CIN In 0.000 10.347 - LM32.cpu.multiplier.product_2_madd_cry_13_0 CCU2D COUT Out 0.143 10.490 - product_2_madd_cry_14 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_s_15_0 CCU2D CIN In 0.000 10.490 - LM32.cpu.multiplier.product_2_madd_s_15_0 CCU2D S0 Out 1.549 12.039 - product[31] Net - - - - 1 LM32.cpu.multiplier.result[31] FD1S3DX D In 0.000 12.039 - =============================================================================================================== Path information for path number 2: Requested Period: 10.323 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.217 - Propagation time: 12.039 - Clock delay at starting point: 0.000 (ideal) = Slack (critical) : -1.822 Number of logic level(s): 17 Starting point: LM32.cpu.multiplier.product_pipe_131 / Q Ending point: LM32.cpu.multiplier.result[31] / D The start point is clocked by platform_rev0|clk_i [rising] on pin CK The end point is clocked by platform_rev0|clk_i [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------- LM32.cpu.multiplier.product_pipe_131 FD1P3DX Q Out 1.044 1.044 - product_2_madd_17f[4] Net - - - - 2 LM32.cpu.multiplier.product_2_madd_24_cry_0_0 CCU2D B1 In 0.000 1.044 - LM32.cpu.multiplier.product_2_madd_24_cry_0_0 CCU2D COUT Out 1.545 2.588 - product_2_madd_24_cry_0 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_24_cry_1_0 CCU2D CIN In 0.000 2.588 - LM32.cpu.multiplier.product_2_madd_24_cry_1_0 CCU2D COUT Out 0.143 2.731 - product_2_madd_24_cry_2 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_24_cry_3_0 CCU2D CIN In 0.000 2.731 - LM32.cpu.multiplier.product_2_madd_24_cry_3_0 CCU2D S1 Out 1.621 4.352 - product_2_madd_24[8] Net - - - - 2 LM32.cpu.multiplier.product_2_madd_28_cry_0_0 CCU2D B1 In 0.000 4.352 - LM32.cpu.multiplier.product_2_madd_28_cry_0_0 CCU2D COUT Out 1.545 5.897 - product_2_madd_28_cry_0 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_28_cry_1_0 CCU2D CIN In 0.000 5.897 - LM32.cpu.multiplier.product_2_madd_28_cry_1_0 CCU2D COUT Out 0.143 6.039 - product_2_madd_28_cry_2 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_28_cry_3_0 CCU2D CIN In 0.000 6.039 - LM32.cpu.multiplier.product_2_madd_28_cry_3_0 CCU2D COUT Out 0.143 6.182 - product_2_madd_28_cry_4 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_28_cry_5_0 CCU2D CIN In 0.000 6.182 - LM32.cpu.multiplier.product_2_madd_28_cry_5_0 CCU2D COUT Out 0.143 6.325 - product_2_madd_28_cry_6 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_28_cry_7_0 CCU2D CIN In 0.000 6.325 - LM32.cpu.multiplier.product_2_madd_28_cry_7_0 CCU2D S1 Out 1.621 7.946 - product_2_madd Net - - - - 2 LM32.cpu.multiplier.product_2_madd_cry_0_0 CCU2D A1 In 0.000 7.946 - LM32.cpu.multiplier.product_2_madd_cry_0_0 CCU2D COUT Out 1.545 9.491 - product_2_madd_cry_0 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_1_0 CCU2D CIN In 0.000 9.491 - LM32.cpu.multiplier.product_2_madd_cry_1_0 CCU2D COUT Out 0.143 9.633 - product_2_madd_cry_2 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_3_0 CCU2D CIN In 0.000 9.633 - LM32.cpu.multiplier.product_2_madd_cry_3_0 CCU2D COUT Out 0.143 9.776 - product_2_madd_cry_4 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_5_0 CCU2D CIN In 0.000 9.776 - LM32.cpu.multiplier.product_2_madd_cry_5_0 CCU2D COUT Out 0.143 9.919 - product_2_madd_cry_6 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_7_0 CCU2D CIN In 0.000 9.919 - LM32.cpu.multiplier.product_2_madd_cry_7_0 CCU2D COUT Out 0.143 10.062 - product_2_madd_cry_8 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_9_0 CCU2D CIN In 0.000 10.062 - LM32.cpu.multiplier.product_2_madd_cry_9_0 CCU2D COUT Out 0.143 10.204 - product_2_madd_cry_10 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_11_0 CCU2D CIN In 0.000 10.204 - LM32.cpu.multiplier.product_2_madd_cry_11_0 CCU2D COUT Out 0.143 10.347 - product_2_madd_cry_12 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_13_0 CCU2D CIN In 0.000 10.347 - LM32.cpu.multiplier.product_2_madd_cry_13_0 CCU2D COUT Out 0.143 10.490 - product_2_madd_cry_14 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_s_15_0 CCU2D CIN In 0.000 10.490 - LM32.cpu.multiplier.product_2_madd_s_15_0 CCU2D S0 Out 1.549 12.039 - product[31] Net - - - - 1 LM32.cpu.multiplier.result[31] FD1S3DX D In 0.000 12.039 - =============================================================================================================== Path information for path number 3: Requested Period: 10.323 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.217 - Propagation time: 11.967 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.750 Number of logic level(s): 17 Starting point: LM32.cpu.multiplier.product_pipe_16 / Q Ending point: LM32.cpu.multiplier.result[31] / D The start point is clocked by platform_rev0|clk_i [rising] on pin CK The end point is clocked by platform_rev0|clk_i [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------- LM32.cpu.multiplier.product_pipe_16 FD1P3DX Q Out 1.044 1.044 - product_2_madd_24 Net - - - - 2 LM32.cpu.multiplier.product_2_madd_24_cry_0_0 CCU2D A1 In 0.000 1.044 - LM32.cpu.multiplier.product_2_madd_24_cry_0_0 CCU2D COUT Out 1.545 2.588 - product_2_madd_24_cry_0 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_24_cry_1_0 CCU2D CIN In 0.000 2.588 - LM32.cpu.multiplier.product_2_madd_24_cry_1_0 CCU2D COUT Out 0.143 2.731 - product_2_madd_24_cry_2 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_24_cry_3_0 CCU2D CIN In 0.000 2.731 - LM32.cpu.multiplier.product_2_madd_24_cry_3_0 CCU2D COUT Out 0.143 2.874 - product_2_madd_24_cry_4 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_24_cry_5_0 CCU2D CIN In 0.000 2.874 - LM32.cpu.multiplier.product_2_madd_24_cry_5_0 CCU2D S1 Out 1.549 4.423 - product_2_madd_24[10] Net - - - - 1 LM32.cpu.multiplier.product_2_madd_28_cry_1_0 CCU2D B1 In 0.000 4.423 - LM32.cpu.multiplier.product_2_madd_28_cry_1_0 CCU2D COUT Out 1.545 5.967 - product_2_madd_28_cry_2 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_28_cry_3_0 CCU2D CIN In 0.000 5.967 - LM32.cpu.multiplier.product_2_madd_28_cry_3_0 CCU2D COUT Out 0.143 6.110 - product_2_madd_28_cry_4 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_28_cry_5_0 CCU2D CIN In 0.000 6.110 - LM32.cpu.multiplier.product_2_madd_28_cry_5_0 CCU2D COUT Out 0.143 6.253 - product_2_madd_28_cry_6 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_28_cry_7_0 CCU2D CIN In 0.000 6.253 - LM32.cpu.multiplier.product_2_madd_28_cry_7_0 CCU2D S1 Out 1.621 7.874 - product_2_madd Net - - - - 2 LM32.cpu.multiplier.product_2_madd_cry_0_0 CCU2D A1 In 0.000 7.874 - LM32.cpu.multiplier.product_2_madd_cry_0_0 CCU2D COUT Out 1.545 9.418 - product_2_madd_cry_0 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_1_0 CCU2D CIN In 0.000 9.418 - LM32.cpu.multiplier.product_2_madd_cry_1_0 CCU2D COUT Out 0.143 9.561 - product_2_madd_cry_2 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_3_0 CCU2D CIN In 0.000 9.561 - LM32.cpu.multiplier.product_2_madd_cry_3_0 CCU2D COUT Out 0.143 9.704 - product_2_madd_cry_4 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_5_0 CCU2D CIN In 0.000 9.704 - LM32.cpu.multiplier.product_2_madd_cry_5_0 CCU2D COUT Out 0.143 9.847 - product_2_madd_cry_6 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_7_0 CCU2D CIN In 0.000 9.847 - LM32.cpu.multiplier.product_2_madd_cry_7_0 CCU2D COUT Out 0.143 9.990 - product_2_madd_cry_8 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_9_0 CCU2D CIN In 0.000 9.990 - LM32.cpu.multiplier.product_2_madd_cry_9_0 CCU2D COUT Out 0.143 10.133 - product_2_madd_cry_10 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_11_0 CCU2D CIN In 0.000 10.133 - LM32.cpu.multiplier.product_2_madd_cry_11_0 CCU2D COUT Out 0.143 10.275 - product_2_madd_cry_12 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_13_0 CCU2D CIN In 0.000 10.275 - LM32.cpu.multiplier.product_2_madd_cry_13_0 CCU2D COUT Out 0.143 10.418 - product_2_madd_cry_14 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_s_15_0 CCU2D CIN In 0.000 10.418 - LM32.cpu.multiplier.product_2_madd_s_15_0 CCU2D S0 Out 1.549 11.967 - product[31] Net - - - - 1 LM32.cpu.multiplier.result[31] FD1S3DX D In 0.000 11.967 - =============================================================================================================== Path information for path number 4: Requested Period: 10.323 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.217 - Propagation time: 11.967 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.750 Number of logic level(s): 17 Starting point: LM32.cpu.multiplier.product_pipe_16 / Q Ending point: LM32.cpu.multiplier.result[31] / D The start point is clocked by platform_rev0|clk_i [rising] on pin CK The end point is clocked by platform_rev0|clk_i [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------- LM32.cpu.multiplier.product_pipe_16 FD1P3DX Q Out 1.044 1.044 - product_2_madd_24 Net - - - - 2 LM32.cpu.multiplier.product_2_madd_24_cry_0_0 CCU2D A1 In 0.000 1.044 - LM32.cpu.multiplier.product_2_madd_24_cry_0_0 CCU2D COUT Out 1.545 2.588 - product_2_madd_24_cry_0 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_24_cry_1_0 CCU2D CIN In 0.000 2.588 - LM32.cpu.multiplier.product_2_madd_24_cry_1_0 CCU2D COUT Out 0.143 2.731 - product_2_madd_24_cry_2 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_24_cry_3_0 CCU2D CIN In 0.000 2.731 - LM32.cpu.multiplier.product_2_madd_24_cry_3_0 CCU2D S1 Out 1.621 4.352 - product_2_madd_24[8] Net - - - - 2 LM32.cpu.multiplier.product_2_madd_28_cry_0_0 CCU2D B1 In 0.000 4.352 - LM32.cpu.multiplier.product_2_madd_28_cry_0_0 CCU2D COUT Out 1.545 5.897 - product_2_madd_28_cry_0 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_28_cry_1_0 CCU2D CIN In 0.000 5.897 - LM32.cpu.multiplier.product_2_madd_28_cry_1_0 CCU2D COUT Out 0.143 6.039 - product_2_madd_28_cry_2 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_28_cry_3_0 CCU2D CIN In 0.000 6.039 - LM32.cpu.multiplier.product_2_madd_28_cry_3_0 CCU2D COUT Out 0.143 6.182 - product_2_madd_28_cry_4 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_28_cry_5_0 CCU2D CIN In 0.000 6.182 - LM32.cpu.multiplier.product_2_madd_28_cry_5_0 CCU2D COUT Out 0.143 6.325 - product_2_madd_28_cry_6 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_28_cry_7_0 CCU2D CIN In 0.000 6.325 - LM32.cpu.multiplier.product_2_madd_28_cry_7_0 CCU2D COUT Out 0.143 6.468 - product_2_madd_28_cry_8 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_28_cry_9_0 CCU2D CIN In 0.000 6.468 - LM32.cpu.multiplier.product_2_madd_28_cry_9_0 CCU2D S1 Out 1.549 8.017 - product_2_madd_28[18] Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_1_0 CCU2D A1 In 0.000 8.017 - LM32.cpu.multiplier.product_2_madd_cry_1_0 CCU2D COUT Out 1.545 9.561 - product_2_madd_cry_2 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_3_0 CCU2D CIN In 0.000 9.561 - LM32.cpu.multiplier.product_2_madd_cry_3_0 CCU2D COUT Out 0.143 9.704 - product_2_madd_cry_4 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_5_0 CCU2D CIN In 0.000 9.704 - LM32.cpu.multiplier.product_2_madd_cry_5_0 CCU2D COUT Out 0.143 9.847 - product_2_madd_cry_6 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_7_0 CCU2D CIN In 0.000 9.847 - LM32.cpu.multiplier.product_2_madd_cry_7_0 CCU2D COUT Out 0.143 9.990 - product_2_madd_cry_8 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_9_0 CCU2D CIN In 0.000 9.990 - LM32.cpu.multiplier.product_2_madd_cry_9_0 CCU2D COUT Out 0.143 10.133 - product_2_madd_cry_10 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_11_0 CCU2D CIN In 0.000 10.133 - LM32.cpu.multiplier.product_2_madd_cry_11_0 CCU2D COUT Out 0.143 10.275 - product_2_madd_cry_12 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_13_0 CCU2D CIN In 0.000 10.275 - LM32.cpu.multiplier.product_2_madd_cry_13_0 CCU2D COUT Out 0.143 10.418 - product_2_madd_cry_14 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_s_15_0 CCU2D CIN In 0.000 10.418 - LM32.cpu.multiplier.product_2_madd_s_15_0 CCU2D S0 Out 1.549 11.967 - product[31] Net - - - - 1 LM32.cpu.multiplier.result[31] FD1S3DX D In 0.000 11.967 - =============================================================================================================== Path information for path number 5: Requested Period: 10.323 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 10.217 - Propagation time: 11.967 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.750 Number of logic level(s): 17 Starting point: LM32.cpu.multiplier.product_pipe_131 / Q Ending point: LM32.cpu.multiplier.result[31] / D The start point is clocked by platform_rev0|clk_i [rising] on pin CK The end point is clocked by platform_rev0|clk_i [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) --------------------------------------------------------------------------------------------------------------- LM32.cpu.multiplier.product_pipe_131 FD1P3DX Q Out 1.044 1.044 - product_2_madd_17f[4] Net - - - - 2 LM32.cpu.multiplier.product_2_madd_24_cry_0_0 CCU2D B1 In 0.000 1.044 - LM32.cpu.multiplier.product_2_madd_24_cry_0_0 CCU2D COUT Out 1.545 2.588 - product_2_madd_24_cry_0 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_24_cry_1_0 CCU2D CIN In 0.000 2.588 - LM32.cpu.multiplier.product_2_madd_24_cry_1_0 CCU2D COUT Out 0.143 2.731 - product_2_madd_24_cry_2 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_24_cry_3_0 CCU2D CIN In 0.000 2.731 - LM32.cpu.multiplier.product_2_madd_24_cry_3_0 CCU2D COUT Out 0.143 2.874 - product_2_madd_24_cry_4 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_24_cry_5_0 CCU2D CIN In 0.000 2.874 - LM32.cpu.multiplier.product_2_madd_24_cry_5_0 CCU2D S1 Out 1.549 4.423 - product_2_madd_24[10] Net - - - - 1 LM32.cpu.multiplier.product_2_madd_28_cry_1_0 CCU2D B1 In 0.000 4.423 - LM32.cpu.multiplier.product_2_madd_28_cry_1_0 CCU2D COUT Out 1.545 5.967 - product_2_madd_28_cry_2 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_28_cry_3_0 CCU2D CIN In 0.000 5.967 - LM32.cpu.multiplier.product_2_madd_28_cry_3_0 CCU2D COUT Out 0.143 6.110 - product_2_madd_28_cry_4 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_28_cry_5_0 CCU2D CIN In 0.000 6.110 - LM32.cpu.multiplier.product_2_madd_28_cry_5_0 CCU2D COUT Out 0.143 6.253 - product_2_madd_28_cry_6 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_28_cry_7_0 CCU2D CIN In 0.000 6.253 - LM32.cpu.multiplier.product_2_madd_28_cry_7_0 CCU2D S1 Out 1.621 7.874 - product_2_madd Net - - - - 2 LM32.cpu.multiplier.product_2_madd_cry_0_0 CCU2D A1 In 0.000 7.874 - LM32.cpu.multiplier.product_2_madd_cry_0_0 CCU2D COUT Out 1.545 9.418 - product_2_madd_cry_0 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_1_0 CCU2D CIN In 0.000 9.418 - LM32.cpu.multiplier.product_2_madd_cry_1_0 CCU2D COUT Out 0.143 9.561 - product_2_madd_cry_2 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_3_0 CCU2D CIN In 0.000 9.561 - LM32.cpu.multiplier.product_2_madd_cry_3_0 CCU2D COUT Out 0.143 9.704 - product_2_madd_cry_4 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_5_0 CCU2D CIN In 0.000 9.704 - LM32.cpu.multiplier.product_2_madd_cry_5_0 CCU2D COUT Out 0.143 9.847 - product_2_madd_cry_6 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_7_0 CCU2D CIN In 0.000 9.847 - LM32.cpu.multiplier.product_2_madd_cry_7_0 CCU2D COUT Out 0.143 9.990 - product_2_madd_cry_8 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_9_0 CCU2D CIN In 0.000 9.990 - LM32.cpu.multiplier.product_2_madd_cry_9_0 CCU2D COUT Out 0.143 10.133 - product_2_madd_cry_10 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_11_0 CCU2D CIN In 0.000 10.133 - LM32.cpu.multiplier.product_2_madd_cry_11_0 CCU2D COUT Out 0.143 10.275 - product_2_madd_cry_12 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_cry_13_0 CCU2D CIN In 0.000 10.275 - LM32.cpu.multiplier.product_2_madd_cry_13_0 CCU2D COUT Out 0.143 10.418 - product_2_madd_cry_14 Net - - - - 1 LM32.cpu.multiplier.product_2_madd_s_15_0 CCU2D CIN In 0.000 10.418 - LM32.cpu.multiplier.product_2_madd_s_15_0 CCU2D S0 Out 1.549 11.967 - product[31] Net - - - - 1 LM32.cpu.multiplier.result[31] FD1S3DX D In 0.000 11.967 - =============================================================================================================== ==================================== Detailed Report for Clock: wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------------------- sdram.sdr_fifo_intf_uut.U1.cState_1[6] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX Q cState_1[6] 1.244 -1.228 sdram.sdr_fifo_intf_uut.U1.cState_1[9] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX Q cState_1[9] 1.244 -1.228 sdram.sdr_fifo_intf_uut.U1.cState_1[10] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX Q cState_1[10] 1.244 -1.228 sdram.sdr_fifo_intf_uut.U1.cState_1[13] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX Q cState_1[13] 1.236 -1.220 sdram.sdr_fifo_intf_uut.U1.cState_1[12] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX Q cState_1[12] 1.252 -1.018 sdram.sdr_fifo_intf_uut.U1.cState_1[3] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX Q cState_1[3] 1.280 -1.015 sdram.sdr_fifo_intf_uut.U1.cState_1[2] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX Q cState_1[2] 1.244 -1.010 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1P3BX Q next_adr[2] 1.108 -0.738 sdram.sdr_fifo_intf_uut.U1.cState_1[5] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX Q cState_1[5] 1.204 -0.601 sdram.sdr_fifo_intf_uut.U1.cState_1[11] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1S3DX Q cState_1[11] 1.180 -0.577 =============================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock --------------------------------------------------------------------------------------------------------------------------------------------------- sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_19 wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1P3DX D next_adr_0[21] 6.854 -1.228 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_20 wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1P3DX D next_adr_0[22] 6.854 -1.228 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_17 wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1P3DX D next_adr_0[19] 6.854 -1.085 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_18 wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1P3DX D next_adr_0[20] 6.854 -1.085 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_15 wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1P3DX D next_adr_0[17] 6.854 -0.943 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_16 wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1P3DX D next_adr_0[18] 6.854 -0.943 sdram.sdr_fifo_intf_uut.U2.sys_A[2] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1P3DX SP un1_sys_A8_1_i 6.488 -0.641 sdram.sdr_fifo_intf_uut.U2.sys_A[3] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1P3DX SP un1_sys_A8_1_i 6.488 -0.641 sdram.sdr_fifo_intf_uut.U2.sys_A[4] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1P3DX SP un1_sys_A8_1_i 6.488 -0.641 sdram.sdr_fifo_intf_uut.U2.sys_A[5] wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock FD1P3DX SP un1_sys_A8_1_i 6.488 -0.641 =================================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 6.960 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.854 - Propagation time: 8.082 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.228 Number of logic level(s): 7 Starting point: sdram.sdr_fifo_intf_uut.U1.cState_1[6] / Q Ending point: sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_20 / D The start point is clocked by wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock [rising] on pin CK The end point is clocked by wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- sdram.sdr_fifo_intf_uut.U1.cState_1[6] FD1S3DX Q Out 1.244 1.244 - cState_1[6] Net - - - - 12 sdram.sdr_fifo_intf_uut.U2.g0_sx_3 ORCALUT4 A In 0.000 1.244 - sdram.sdr_fifo_intf_uut.U2.g0_sx_3 ORCALUT4 Z Out 1.017 2.261 - g0_sx_3 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.g0 ORCALUT4 D In 0.000 2.261 - sdram.sdr_fifo_intf_uut.U2.g0 ORCALUT4 Z Out 1.354 3.614 - N_280 Net - - - - 28 sdram.sdr_fifo_intf_uut.U2.row_addr_4_8_261_i_m2 ORCALUT4 A In 0.000 3.614 - sdram.sdr_fifo_intf_uut.U2.row_addr_4_8_261_i_m2 ORCALUT4 Z Out 1.089 4.703 - N_420 Net - - - - 2 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_13_0 CCU2D A0 In 0.000 4.703 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_13_0 CCU2D COUT Out 1.545 6.247 - next_adr_cry_14 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_15_0 CCU2D CIN In 0.000 6.247 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_15_0 CCU2D COUT Out 0.143 6.390 - next_adr_cry_16 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_17_0 CCU2D CIN In 0.000 6.390 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_17_0 CCU2D COUT Out 0.143 6.533 - next_adr_cry_18 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_19_0 CCU2D CIN In 0.000 6.533 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_19_0 CCU2D S1 Out 1.549 8.082 - next_adr_0[22] Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_20 FD1P3DX D In 0.000 8.082 - =================================================================================================================== Path information for path number 2: Requested Period: 6.960 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.854 - Propagation time: 8.082 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.228 Number of logic level(s): 7 Starting point: sdram.sdr_fifo_intf_uut.U1.cState_1[9] / Q Ending point: sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_20 / D The start point is clocked by wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock [rising] on pin CK The end point is clocked by wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- sdram.sdr_fifo_intf_uut.U1.cState_1[9] FD1S3DX Q Out 1.244 1.244 - cState_1[9] Net - - - - 12 sdram.sdr_fifo_intf_uut.U2.g0_sx_3 ORCALUT4 B In 0.000 1.244 - sdram.sdr_fifo_intf_uut.U2.g0_sx_3 ORCALUT4 Z Out 1.017 2.261 - g0_sx_3 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.g0 ORCALUT4 D In 0.000 2.261 - sdram.sdr_fifo_intf_uut.U2.g0 ORCALUT4 Z Out 1.354 3.614 - N_280 Net - - - - 28 sdram.sdr_fifo_intf_uut.U2.row_addr_4_8_261_i_m2 ORCALUT4 A In 0.000 3.614 - sdram.sdr_fifo_intf_uut.U2.row_addr_4_8_261_i_m2 ORCALUT4 Z Out 1.089 4.703 - N_420 Net - - - - 2 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_13_0 CCU2D A0 In 0.000 4.703 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_13_0 CCU2D COUT Out 1.545 6.247 - next_adr_cry_14 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_15_0 CCU2D CIN In 0.000 6.247 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_15_0 CCU2D COUT Out 0.143 6.390 - next_adr_cry_16 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_17_0 CCU2D CIN In 0.000 6.390 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_17_0 CCU2D COUT Out 0.143 6.533 - next_adr_cry_18 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_19_0 CCU2D CIN In 0.000 6.533 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_19_0 CCU2D S1 Out 1.549 8.082 - next_adr_0[22] Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_20 FD1P3DX D In 0.000 8.082 - =================================================================================================================== Path information for path number 3: Requested Period: 6.960 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.854 - Propagation time: 8.082 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.228 Number of logic level(s): 7 Starting point: sdram.sdr_fifo_intf_uut.U1.cState_1[10] / Q Ending point: sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_20 / D The start point is clocked by wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock [rising] on pin CK The end point is clocked by wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- sdram.sdr_fifo_intf_uut.U1.cState_1[10] FD1S3DX Q Out 1.244 1.244 - cState_1[10] Net - - - - 12 sdram.sdr_fifo_intf_uut.U2.g0_sx_3 ORCALUT4 C In 0.000 1.244 - sdram.sdr_fifo_intf_uut.U2.g0_sx_3 ORCALUT4 Z Out 1.017 2.261 - g0_sx_3 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.g0 ORCALUT4 D In 0.000 2.261 - sdram.sdr_fifo_intf_uut.U2.g0 ORCALUT4 Z Out 1.354 3.614 - N_280 Net - - - - 28 sdram.sdr_fifo_intf_uut.U2.row_addr_4_8_261_i_m2 ORCALUT4 A In 0.000 3.614 - sdram.sdr_fifo_intf_uut.U2.row_addr_4_8_261_i_m2 ORCALUT4 Z Out 1.089 4.703 - N_420 Net - - - - 2 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_13_0 CCU2D A0 In 0.000 4.703 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_13_0 CCU2D COUT Out 1.545 6.247 - next_adr_cry_14 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_15_0 CCU2D CIN In 0.000 6.247 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_15_0 CCU2D COUT Out 0.143 6.390 - next_adr_cry_16 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_17_0 CCU2D CIN In 0.000 6.390 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_17_0 CCU2D COUT Out 0.143 6.533 - next_adr_cry_18 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_19_0 CCU2D CIN In 0.000 6.533 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_19_0 CCU2D S1 Out 1.549 8.082 - next_adr_0[22] Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_20 FD1P3DX D In 0.000 8.082 - =================================================================================================================== Path information for path number 4: Requested Period: 6.960 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.854 - Propagation time: 8.082 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.228 Number of logic level(s): 7 Starting point: sdram.sdr_fifo_intf_uut.U1.cState_1[6] / Q Ending point: sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_20 / D The start point is clocked by wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock [rising] on pin CK The end point is clocked by wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- sdram.sdr_fifo_intf_uut.U1.cState_1[6] FD1S3DX Q Out 1.244 1.244 - cState_1[6] Net - - - - 12 sdram.sdr_fifo_intf_uut.U2.g0_sx_3 ORCALUT4 A In 0.000 1.244 - sdram.sdr_fifo_intf_uut.U2.g0_sx_3 ORCALUT4 Z Out 1.017 2.261 - g0_sx_3 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.g0 ORCALUT4 D In 0.000 2.261 - sdram.sdr_fifo_intf_uut.U2.g0 ORCALUT4 Z Out 1.354 3.614 - N_280 Net - - - - 28 sdram.sdr_fifo_intf_uut.U2.row_addr_4_9_244_i_m2 ORCALUT4 A In 0.000 3.614 - sdram.sdr_fifo_intf_uut.U2.row_addr_4_9_244_i_m2 ORCALUT4 Z Out 1.089 4.703 - N_404 Net - - - - 2 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_13_0 CCU2D A1 In 0.000 4.703 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_13_0 CCU2D COUT Out 1.545 6.247 - next_adr_cry_14 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_15_0 CCU2D CIN In 0.000 6.247 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_15_0 CCU2D COUT Out 0.143 6.390 - next_adr_cry_16 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_17_0 CCU2D CIN In 0.000 6.390 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_17_0 CCU2D COUT Out 0.143 6.533 - next_adr_cry_18 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_19_0 CCU2D CIN In 0.000 6.533 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_19_0 CCU2D S1 Out 1.549 8.082 - next_adr_0[22] Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_20 FD1P3DX D In 0.000 8.082 - =================================================================================================================== Path information for path number 5: Requested Period: 6.960 - Setup time: 0.106 + Clock delay at ending point: 0.000 (ideal) = Required time: 6.854 - Propagation time: 8.082 - Clock delay at starting point: 0.000 (ideal) = Slack (non-critical) : -1.228 Number of logic level(s): 7 Starting point: sdram.sdr_fifo_intf_uut.U1.cState_1[6] / Q Ending point: sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_19 / D The start point is clocked by wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock [rising] on pin CK The end point is clocked by wb_sdr_ctrl_Z5|sdr_clk_c_inferred_clock [rising] on pin CK Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------- sdram.sdr_fifo_intf_uut.U1.cState_1[6] FD1S3DX Q Out 1.244 1.244 - cState_1[6] Net - - - - 12 sdram.sdr_fifo_intf_uut.U2.g0_sx_3 ORCALUT4 A In 0.000 1.244 - sdram.sdr_fifo_intf_uut.U2.g0_sx_3 ORCALUT4 Z Out 1.017 2.261 - g0_sx_3 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.g0 ORCALUT4 D In 0.000 2.261 - sdram.sdr_fifo_intf_uut.U2.g0 ORCALUT4 Z Out 1.354 3.614 - N_280 Net - - - - 28 sdram.sdr_fifo_intf_uut.U2.row_addr_4_8_261_i_m2 ORCALUT4 A In 0.000 3.614 - sdram.sdr_fifo_intf_uut.U2.row_addr_4_8_261_i_m2 ORCALUT4 Z Out 1.089 4.703 - N_420 Net - - - - 2 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_13_0 CCU2D A0 In 0.000 4.703 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_13_0 CCU2D COUT Out 1.545 6.247 - next_adr_cry_14 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_15_0 CCU2D CIN In 0.000 6.247 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_15_0 CCU2D COUT Out 0.143 6.390 - next_adr_cry_16 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_17_0 CCU2D CIN In 0.000 6.390 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_17_0 CCU2D COUT Out 0.143 6.533 - next_adr_cry_18 Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.next_adr_cry_19_0 CCU2D CIN In 0.000 6.533 - sdram.sdr_fifo_intf_uut.U2.next_adr_cry_19_0 CCU2D S0 Out 1.549 8.082 - next_adr_0[21] Net - - - - 1 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_19 FD1P3DX D In 0.000 8.082 - =================================================================================================================== ==================================== Detailed Report for Clock: System ==================================== Starting Points with Worst Slack ******************************** Starting Arrival Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------- sdram.fifo_sdr2wb System pmi_fifo_dc_Z4 Empty sdr2wb_empty 0.000 0.084 sdram.fifo_wb2sdr System pmi_fifo_dc_Z3 AlmostEmpty wb2sdr_almost_empty 0.000 0.188 sdram.fifo_wb2sdr System pmi_fifo_dc_Z3 Empty wb2sdr_empty 0.000 0.188 sdram.fifo_wb2sdr System pmi_fifo_dc_Z3 Q[2] wb2sdr_q[2] 0.000 0.370 LM32.jtag_cores.jtagconn16_lm32_inst System jtagconn16 ip_enable ip_enable_0 0.000 0.416 LM32.jtag_cores.jtagconn16_lm32_inst System jtagconn16 jce2 jce2_0 0.000 0.416 LM32.jtag_cores.jtagconn16_lm32_inst System jtagconn16 jshift jshift_0 0.000 0.808 LM32.jtag_cores.jtagconn16_lm32_inst System jtagconn16 jtdi jtdi_0 0.000 0.808 LM32.jtag_cores.jtagconn16_lm32_inst System jtagconn16 jupdate jupdate_0 0.000 0.864 LM32.cpu.jtag.rx_toggle System FD1S3DX Q rx_toggle 1.044 1.025 =================================================================================================================================== Ending Points with Worst Slack ****************************** Starting Required Instance Reference Type Pin Net Time Slack Clock ----------------------------------------------------------------------------------------------------------------------------------- sdram.fifo_wb2sdr System pmi_fifo_dc_Z3 WrEn wb2sdr_we 2.743 0.084 sdram.fifo_wb2sdr System pmi_fifo_dc_Z3 RdEn wb2sdr_re 2.743 0.188 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_19 System FD1P3DX D next_adr_0[21] 6.854 0.370 sdram.sdr_fifo_intf_uut.U2.sys_A_pipe_20 System FD1P3DX D next_adr_0[22] 6.854 0.370 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT5.tdoInt System FD1P3DX SP clk_enable 0.864 0.416 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT6.tdoInt System FD1P3DX SP clk_enable 0.864 0.416 LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT2.tdoInt System FD1P3DX SP clk_enable 0.864 0.416 LM32.jtag_cores.jtag_lm32_inst.DATA_BIT1.tdoInt System FD1P3DX SP clk_enable 0.864 0.416 LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT0.tdoInt System FD1P3DX SP clk_enable 0.864 0.416 LM32.jtag_cores.jtag_lm32_inst.ADDR_BIT1.tdoInt System FD1P3DX SP clk_enable 0.864 0.416 =================================================================================================================================== Worst Path Information View Worst Path in Analyst *********************** Path information for path number 1: Requested Period: 2.743 - Setup time: 0.000 + Clock delay at ending point: 0.000 (ideal) + Estimated clock delay at ending point: 0.000 = Required time: 2.743 - Propagation time: 2.658 - Clock delay at starting point: 0.000 (ideal) - Estimated clock delay at start point: -0.000 = Slack (non-critical) : 0.084 Number of logic level(s): 3 Starting point: sdram.fifo_sdr2wb / Empty Ending point: sdram.fifo_wb2sdr / WrEn The start point is clocked by System [rising] The end point is clocked by System [rising] Instance / Net Pin Pin Arrival No. of Name Type Name Dir Delay Time Fan Out(s) ------------------------------------------------------------------------------------------------------------------------------ sdram.fifo_sdr2wb pmi_fifo_dc_Z4 Empty Out 0.000 0.000 - sdr2wb_empty Net - - - - 3 sdram.wb_fifo_intf_uut.wb_status_ns_1_0_.m4_0_a2_1_0 ORCALUT4 A In 0.000 0.000 - sdram.wb_fifo_intf_uut.wb_status_ns_1_0_.m4_0_a2_1_0 ORCALUT4 Z Out 1.017 1.017 - m4_0_a2_1_0 Net - - - - 1 sdram.wb_fifo_intf_uut.wb_status_ns_1_0_.m4_0_a2_1 ORCALUT4 C In 0.000 1.017 - sdram.wb_fifo_intf_uut.wb_status_ns_1_0_.m4_0_a2_1 ORCALUT4 Z Out 1.193 2.210 - N_353 Net - - - - 4 sdram.wb_fifo_intf_uut.wb2sdr_we_u_0 ORCALUT4 A In 0.000 2.210 - sdram.wb_fifo_intf_uut.wb2sdr_we_u_0 ORCALUT4 Z Out 0.449 2.658 - wb2sdr_we Net - - - - 1 sdram.fifo_wb2sdr pmi_fifo_dc_Z3 WrEn In 0.000 2.658 - ============================================================================================================================== ##### END OF TIMING REPORT #####] --------------------------------------- Resource Usage Report Part: lcmxo2_7000hc-6 Register bits: 1673 of 6864 (24%) PIC Latch: 0 I/O cells: 42 Block Rams : 4 of 26 (15%) Details: BB: 16 CCU2D: 391 DP8KC: 4 DPR16X4C: 32 FD1P3AX: 32 FD1P3BX: 46 FD1P3DX: 1240 FD1S3AX: 3 FD1S3BX: 17 FD1S3DX: 280 FD1S3IX: 1 GSR: 1 IB: 3 IFS1P3DX: 1 INV: 17 OB: 22 OBZ: 1 OFS1P3BX: 34 OFS1P3DX: 19 ORCALUT4: 2553 PFUMX: 212 PUR: 1 VHI: 33 VLO: 39 Mapper successful! At Mapper Exit (Real Time elapsed 0h:00m:34s; CPU Time elapsed 0h:00m:32s; Memory used current: 33MB peak: 139MB) Process took 0h:00m:34s realtime, 0h:00m:32s cputime # Thu Jun 20 21:30:33 2013 ###########################################################]