Map TRACE Report
Loading design for application trce from file prj_diamond_ver0_prj_diamond_ver0_map.ncd.
Design name: platform_rev0
NCD version: 3.2
Vendor: LATTICE
Device: LCMXO2-7000HC
Package: TQFP144
Performance: 6
Loading device for application trce from file 'xo2c7000.nph' in environment: C:/lscc/diamond/2.2/ispfpga.
Package Status: Final Version 1.36
Performance Hardware Data Status: Final) Version 23.4
Setup and Hold Report
--------------------------------------------------------------------------------
Lattice TRACE Report - Setup, Version Diamond Version 2.2.0.101
Thu Jun 20 22:12:03 2013
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o prj_diamond_ver0_prj_diamond_ver0.tw1 prj_diamond_ver0_prj_diamond_ver0_map.ncd prj_diamond_ver0_prj_diamond_ver0.prf
Design file: prj_diamond_ver0_prj_diamond_ver0_map.ncd
Preference file: prj_diamond_ver0_prj_diamond_ver0.prf
Device,speed: LCMXO2-7000HC,6
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "clk_i_c" 40.000000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
Report: 70.116MHz is the maximum frequency for this preference.
FREQUENCY NET "sdram.sdr_clk_c_c" 80.000000 MHz (8 errors)
4096 items scored, 8 timing errors detected.
Warning: 78.064MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "clk_i_c" 40.000000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 10.738ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q LM32/cpu/adder_op_x (from clk_i_c +)
Destination: FF Data in LM32/cpu/mc_arithmetic/a[8] (to clk_i_c +)
Delay: 14.129ns (40.4% logic, 59.6% route), 15 logic levels.
Constraint Details:
14.129ns physical path delay LM32/cpu/SLICE_695 to LM32/cpu/mc_arithmetic/SLICE_921 meets
25.000ns delay constraint less
0.133ns DIN_SET requirement (totaling 24.867ns) by 10.738ns
Physical Path Details:
Data path LM32/cpu/SLICE_695 to LM32/cpu/mc_arithmetic/SLICE_921:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 *SLICE_695.CLK to */SLICE_695.Q0 LM32/cpu/SLICE_695 (from clk_i_c)
ROUTE 2 e 0.896 */SLICE_695.Q0 to SLICE_1601.A0 LM32/cpu/adder_op_x
CTOF_DEL --- 0.408 SLICE_1601.A0 to SLICE_1601.F0 SLICE_1601
ROUTE 1 e 0.896 SLICE_1601.F0 to SLICE_445.B0 LM32/cpu/adder/addsub/genblk1.addsub/ci_k
C0TOFCO_DE --- 0.787 SLICE_445.B0 to SLICE_445.FCO SLICE_445
ROUTE 1 e 0.001 SLICE_445.FCO to SLICE_446.FCI LM32/cpu/adder/addsub/genblk1.addsub/co0
FCITOFCO_D --- 0.130 SLICE_446.FCI to SLICE_446.FCO SLICE_446
ROUTE 1 e 0.001 SLICE_446.FCO to *SLICE_447.FCI LM32/cpu/adder/addsub/genblk1.addsub/co1
FCITOFCO_D --- 0.130 *SLICE_447.FCI to *SLICE_447.FCO LM32/cpu/adder/addsub/genblk1.addsub/SLICE_447
ROUTE 1 e 0.001 *SLICE_447.FCO to *SLICE_448.FCI LM32/cpu/adder/addsub/genblk1.addsub/co2
FCITOFCO_D --- 0.130 *SLICE_448.FCI to *SLICE_448.FCO LM32/cpu/adder/addsub/genblk1.addsub/SLICE_448
ROUTE 1 e 0.001 *SLICE_448.FCO to *SLICE_449.FCI LM32/cpu/adder/addsub/genblk1.addsub/co3
FCITOF1_DE --- 0.495 *SLICE_449.FCI to */SLICE_449.F1 LM32/cpu/adder/addsub/genblk1.addsub/SLICE_449
ROUTE 1 e 0.896 */SLICE_449.F1 to *SLICE_1981.B1 LM32/cpu/adder_result_x[8]
CTOF_DEL --- 0.408 *SLICE_1981.B1 to *SLICE_1981.F1 LM32/cpu/logic_op/SLICE_1981
ROUTE 1 e 0.349 *SLICE_1981.F1 to *SLICE_1981.C0 LM32/cpu/logic_op/x_result_1_iv_0_0[8]
CTOF_DEL --- 0.408 *SLICE_1981.C0 to *SLICE_1981.F0 LM32/cpu/logic_op/SLICE_1981
ROUTE 1 e 0.896 *SLICE_1981.F0 to *SLICE_1965.D0 LM32/cpu/logic_op/x_result_1_iv_0_2[8]
CTOF_DEL --- 0.408 *SLICE_1965.D0 to *SLICE_1965.F0 LM32/cpu/logic_op/SLICE_1965
ROUTE 1 e 0.896 *SLICE_1965.F0 to *SLICE_1958.B0 LM32/cpu/logic_op/x_result_1_iv_0_5[8]
CTOF_DEL --- 0.408 *SLICE_1958.B0 to *SLICE_1958.F0 LM32/cpu/SLICE_1958
ROUTE 1 e 0.896 *SLICE_1958.F0 to *SLICE_1047.C0 LM32/cpu/logic_op/x_result_1_iv_0_7[8]
CTOF_DEL --- 0.408 *SLICE_1047.C0 to *SLICE_1047.F0 LM32/cpu/SLICE_1047
ROUTE 3 e 0.896 *SLICE_1047.F0 to *SLICE_2438.C1 LM32/cpu/x_result_1[8]
CTOF_DEL --- 0.408 *SLICE_2438.C1 to *SLICE_2438.F1 LM32/cpu/SLICE_2438
ROUTE 2 e 0.896 *SLICE_2438.F1 to *SLICE_1015.A0 LM32/cpu/bypass_data_0[8]
CTOF_DEL --- 0.408 *SLICE_1015.A0 to *SLICE_1015.F0 LM32/cpu/SLICE_1015
ROUTE 2 e 0.896 *SLICE_1015.F0 to */SLICE_921.B0 LM32/cpu/d_result_0[8]
CTOF_DEL --- 0.408 */SLICE_921.B0 to */SLICE_921.F0 LM32/cpu/mc_arithmetic/SLICE_921
ROUTE 1 e 0.001 */SLICE_921.F0 to *SLICE_921.DI0 LM32/cpu/mc_arithmetic/a_12[8] (to clk_i_c)
--------
14.129 (40.4% logic, 59.6% route), 15 logic levels.
Report: 70.116MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "sdram.sdr_clk_c_c" 80.000000 MHz ;
4096 items scored, 8 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 0.310ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram/sdr_fifo_intf_uut/U1/cState_1[4] (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_wb2sdr/FF_13 (to sdram.sdr_clk_c_c +)
Delay: 12.677ns (40.7% logic, 59.3% route), 14 logic levels.
Constraint Details:
12.677ns physical path delay sdram/sdr_fifo_intf_uut/U1/SLICE_1417 to sdram/fifo_wb2sdr/SLICE_76 exceeds
12.500ns delay constraint less
0.133ns DIN_SET requirement (totaling 12.367ns) by 0.310ns
Physical Path Details:
Data path sdram/sdr_fifo_intf_uut/U1/SLICE_1417 to sdram/fifo_wb2sdr/SLICE_76:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 *LICE_1417.CLK to *SLICE_1417.Q0 sdram/sdr_fifo_intf_uut/U1/SLICE_1417 (from sdram.sdr_clk_c_c)
ROUTE 6 e 0.896 *SLICE_1417.Q0 to *SLICE_1440.A1 sdram/sdr_fifo_intf_uut/U1/cState_1[4]
CTOF_DEL --- 0.408 *SLICE_1440.A1 to *SLICE_1440.F1 sdram/sdr_fifo_intf_uut/SLICE_1440
ROUTE 1 e 0.896 *SLICE_1440.F1 to *SLICE_1814.A1 sdram/sdr_fifo_intf_uut/U1/N_322
CTOF_DEL --- 0.408 *SLICE_1814.A1 to *SLICE_1814.F1 sdram/sdr_fifo_intf_uut/SLICE_1814
ROUTE 7 e 0.896 *SLICE_1814.F1 to *SLICE_2320.A0 sdram/sdr_fifo_intf_uut/N_281_3
CTOF_DEL --- 0.408 *SLICE_2320.A0 to *SLICE_2320.F0 sdram/sdr_fifo_intf_uut/U1/SLICE_2320
ROUTE 6 e 0.896 *SLICE_2320.F0 to *SLICE_1749.B0 sdram/sdr_fifo_intf_uut/N_281
CTOF_DEL --- 0.408 *SLICE_1749.B0 to *SLICE_1749.F0 sdram/sdr_fifo_intf_uut/U2/SLICE_1749
ROUTE 3 e 0.349 *SLICE_1749.F0 to *SLICE_1749.A1 sdram/sdr_fifo_intf_uut/U2/un2_cross_page
CTOF_DEL --- 0.408 *SLICE_1749.A1 to *SLICE_1749.F1 sdram/sdr_fifo_intf_uut/U2/SLICE_1749
ROUTE 2 e 0.896 *SLICE_1749.F1 to *SLICE_1428.A0 sdram/sdr_fifo_intf_uut/U2/cross_page_1
CTOF_DEL --- 0.408 *SLICE_1428.A0 to *SLICE_1428.F0 sdram/sdr_fifo_intf_uut/U2/SLICE_1428
ROUTE 4 e 0.896 *SLICE_1428.F0 to *SLICE_1801.C1 sdram/sdr_fifo_intf_uut/cross_page
CTOF_DEL --- 0.408 *SLICE_1801.C1 to *SLICE_1801.F1 sdram/sdr_fifo_intf_uut/SLICE_1801
ROUTE 2 e 0.896 *SLICE_1801.F1 to *SLICE_1765.B1 sdram/sdr_fifo_intf_uut/U1/N_306
CTOF_DEL --- 0.408 *SLICE_1765.B1 to *SLICE_1765.F1 sdram/SLICE_1765
ROUTE 43 e 0.896 *SLICE_1765.F1 to *r/SLICE_72.B1 sdram/fifo_wb2sdr/rden_i
C1TOFCO_DE --- 0.684 *r/SLICE_72.B1 to */SLICE_72.FCO sdram/fifo_wb2sdr/SLICE_72
ROUTE 1 e 0.001 */SLICE_72.FCO to */SLICE_73.FCI sdram/fifo_wb2sdr/cmp_ci
FCITOFCO_D --- 0.130 */SLICE_73.FCI to */SLICE_73.FCO sdram/fifo_wb2sdr/SLICE_73
ROUTE 1 e 0.001 */SLICE_73.FCO to */SLICE_74.FCI sdram/fifo_wb2sdr/co0_2
FCITOFCO_D --- 0.130 */SLICE_74.FCI to */SLICE_74.FCO sdram/fifo_wb2sdr/SLICE_74
ROUTE 1 e 0.001 */SLICE_74.FCO to */SLICE_75.FCI sdram/fifo_wb2sdr/co1_2
FCITOFCO_D --- 0.130 */SLICE_75.FCI to */SLICE_75.FCO sdram/fifo_wb2sdr/SLICE_75
ROUTE 1 e 0.001 */SLICE_75.FCO to */SLICE_76.FCI sdram/fifo_wb2sdr/empty_d_c
FCITOF0_DE --- 0.450 */SLICE_76.FCI to *r/SLICE_76.F0 sdram/fifo_wb2sdr/SLICE_76
ROUTE 1 e 0.001 *r/SLICE_76.F0 to */SLICE_76.DI0 sdram/fifo_wb2sdr/empty_d (to sdram.sdr_clk_c_c)
--------
12.677 (40.7% logic, 59.3% route), 14 logic levels.
Warning: 78.064MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_i_c" 40.000000 MHz ; | 40.000 MHz| 70.116 MHz| 15
| | |
FREQUENCY NET "sdram.sdr_clk_c_c" | | |
80.000000 MHz ; | 80.000 MHz| 78.064 MHz| 14 *
| | |
----------------------------------------------------------------------------
1 preference(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
sdram/fifo_wb2sdr/rden_i | 43| 8| 100.00%
| | |
sdram/sdr_fifo_intf_uut/U1/N_322 | 1| 8| 100.00%
| | |
sdram/sdr_fifo_intf_uut/U1/N_306 | 2| 8| 100.00%
| | |
sdram/sdr_fifo_intf_uut/U2/cross_page_1 | 2| 8| 100.00%
| | |
sdram/sdr_fifo_intf_uut/cross_page | 4| 8| 100.00%
| | |
sdram/sdr_fifo_intf_uut/U2/un2_cross_pag| | |
e | 3| 8| 100.00%
| | |
sdram/sdr_fifo_intf_uut/N_281_3 | 7| 8| 100.00%
| | |
sdram/sdr_fifo_intf_uut/N_281 | 6| 8| 100.00%
| | |
sdram/fifo_wb2sdr/ae_set_d_c | 1| 4| 50.00%
| | |
sdram/fifo_wb2sdr/co1_5 | 1| 4| 50.00%
| | |
sdram/fifo_wb2sdr/co0_5 | 1| 4| 50.00%
| | |
sdram/fifo_wb2sdr/cmp_ci_2 | 1| 4| 50.00%
| | |
sdram/fifo_wb2sdr/empty_d_c | 1| 4| 50.00%
| | |
sdram/fifo_wb2sdr/co1_2 | 1| 4| 50.00%
| | |
sdram/fifo_wb2sdr/co0_2 | 1| 4| 50.00%
| | |
sdram/fifo_wb2sdr/cmp_ci | 1| 4| 50.00%
| | |
sdram/fifo_wb2sdr/empty_d | 1| 4| 50.00%
| | |
sdram/fifo_wb2sdr/ae_set_d | 1| 4| 50.00%
| | |
sdram/sdr_fifo_intf_uut/U1/cState_1[12] | 6| 4| 50.00%
| | |
sdram/sdr_fifo_intf_uut/U1/cState_1[4] | 6| 4| 50.00%
| | |
----------------------------------------------------------------------------
Clock Domains Analysis
------------------------
Found 4 clocks:
Clock Domain: clk_i_c Source: clk_i.PAD Loads: 1013
Covered under: FREQUENCY NET "clk_i_c" 40.000000 MHz ;
Data transfers from:
Clock Domain: sdram.sdr_clk_c_c Source: sdram/U1_pmi_pll/PLLInst_0.CLKOP
Covered under: FREQUENCY NET "clk_i_c" 40.000000 MHz ; Transfers: 44
Clock Domain: LM32/jtag_update Source: SLICE_2443.F0
Not reported because source and destination domains are unrelated.
Clock Domain: jtaghub16_jtck Source: xo2chub/genblk0_genblk6_jtagf_u.JTCK
Not reported because source and destination domains are unrelated.
Clock Domain: sdram.sdr_clk_c_c Source: sdram/U1_pmi_pll/PLLInst_0.CLKOP Loads: 212
Covered under: FREQUENCY NET "sdram.sdr_clk_c_c" 80.000000 MHz ;
Data transfers from:
Clock Domain: clk_i_c Source: clk_i.PAD
Covered under: FREQUENCY NET "sdram.sdr_clk_c_c" 80.000000 MHz ; Transfers: 97
Clock Domain: LM32/jtag_update Source: SLICE_2443.F0 Loads: 1
No transfer within this clock domain is found
Clock Domain: jtaghub16_jtck Source: xo2chub/genblk0_genblk6_jtagf_u.JTCK Loads: 38
No transfer within this clock domain is found
Timing summary (Setup):
---------------
Timing errors: 8 Score: 2480
Cumulative negative slack: 2480
Constraints cover 441111 paths, 2 nets, and 17587 connections (94.1% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond Version 2.2.0.101
Thu Jun 20 22:12:04 2013
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 1 -gt -mapchkpnt 0 -sethld -o prj_diamond_ver0_prj_diamond_ver0.tw1 prj_diamond_ver0_prj_diamond_ver0_map.ncd prj_diamond_ver0_prj_diamond_ver0.prf
Design file: prj_diamond_ver0_prj_diamond_ver0_map.ncd
Preference file: prj_diamond_ver0_prj_diamond_ver0.prf
Device,speed: LCMXO2-7000HC,M
Report level: verbose report, limited to 1 item per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "clk_i_c" 40.000000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
FREQUENCY NET "sdram.sdr_clk_c_c" 80.000000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "clk_i_c" 40.000000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.285ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sdram/fifo_sdr2wb/fifo_pfu_0_7/RAM0 (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_sdr2wb/FF_65 (to clk_i_c +)
Delay: 0.272ns (99.6% logic, 0.4% route), 1 logic levels.
Constraint Details:
0.272ns physical path delay sdram/fifo_sdr2wb/fifo_pfu_0_7.14 to sdram/fifo_sdr2wb/fifo_pfu_0_7.14 meets
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.285ns
Physical Path Details:
Data path sdram/fifo_sdr2wb/fifo_pfu_0_7.14 to sdram/fifo_sdr2wb/fifo_pfu_0_7.14:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 *fu_0_7.14.WCK to *pfu_0_7.14.F0 sdram/fifo_sdr2wb/fifo_pfu_0_7.14 (from sdram.sdr_clk_c_c)
ROUTE 1 e 0.001 *pfu_0_7.14.F0 to *fu_0_7.14.DI0 sdram/fifo_sdr2wb/rdataout0 (to clk_i_c)
--------
0.272 (99.6% logic, 0.4% route), 1 logic levels.
================================================================================
Preference: FREQUENCY NET "sdram.sdr_clk_c_c" 80.000000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.285ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sdram/fifo_wb2sdr/fifo_pfu_0_17/RAM1 (from clk_i_c +)
Destination: FF Data in sdram/fifo_wb2sdr/FF_100 (to sdram.sdr_clk_c_c +)
Delay: 0.272ns (99.6% logic, 0.4% route), 1 logic levels.
Constraint Details:
0.272ns physical path delay sdram/fifo_wb2sdr/fifo_pfu_0_17 to sdram/fifo_wb2sdr/fifo_pfu_0_17 meets
-0.013ns DIN_HLD and
0.000ns delay constraint requirement (totaling -0.013ns) by 0.285ns
Physical Path Details:
Data path sdram/fifo_wb2sdr/fifo_pfu_0_17 to sdram/fifo_wb2sdr/fifo_pfu_0_17:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 *_pfu_0_17.WCK to *o_pfu_0_17.F0 sdram/fifo_wb2sdr/fifo_pfu_0_17 (from clk_i_c)
ROUTE 1 e 0.001 *o_pfu_0_17.F0 to *_pfu_0_17.DI0 sdram/fifo_wb2sdr/rdataout2 (to sdram.sdr_clk_c_c)
--------
0.272 (99.6% logic, 0.4% route), 1 logic levels.
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_i_c" 40.000000 MHz ; | -| -| 1
| | |
FREQUENCY NET "sdram.sdr_clk_c_c" | | |
80.000000 MHz ; | -| -| 1
| | |
----------------------------------------------------------------------------
All preferences were met.
Clock Domains Analysis
------------------------
Found 4 clocks:
Clock Domain: clk_i_c Source: clk_i.PAD Loads: 1013
Covered under: FREQUENCY NET "clk_i_c" 40.000000 MHz ;
Data transfers from:
Clock Domain: sdram.sdr_clk_c_c Source: sdram/U1_pmi_pll/PLLInst_0.CLKOP
Covered under: FREQUENCY NET "clk_i_c" 40.000000 MHz ; Transfers: 44
Clock Domain: LM32/jtag_update Source: SLICE_2443.F0
Not reported because source and destination domains are unrelated.
Clock Domain: jtaghub16_jtck Source: xo2chub/genblk0_genblk6_jtagf_u.JTCK
Not reported because source and destination domains are unrelated.
Clock Domain: sdram.sdr_clk_c_c Source: sdram/U1_pmi_pll/PLLInst_0.CLKOP Loads: 212
Covered under: FREQUENCY NET "sdram.sdr_clk_c_c" 80.000000 MHz ;
Data transfers from:
Clock Domain: clk_i_c Source: clk_i.PAD
Covered under: FREQUENCY NET "sdram.sdr_clk_c_c" 80.000000 MHz ; Transfers: 97
Clock Domain: LM32/jtag_update Source: SLICE_2443.F0 Loads: 1
No transfer within this clock domain is found
Clock Domain: jtaghub16_jtck Source: xo2chub/genblk0_genblk6_jtagf_u.JTCK Loads: 38
No transfer within this clock domain is found
Timing summary (Hold):
---------------
Timing errors: 0 Score: 0
Cumulative negative slack: 0
Constraints cover 441111 paths, 2 nets, and 18471 connections (98.8% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 8 (setup), 0 (hold)
Score: 2480 (setup), 0 (hold)
Cumulative negative slack: 2480 (2480+0)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------