Place & Route TRACE Report
Loading design for application trce from file prj_diamond_ver0_prj_diamond_ver0.ncd.
Design name: platform_rev0
NCD version: 3.2
Vendor: LATTICE
Device: LCMXO2-7000HC
Package: TQFP144
Performance: 6
Loading device for application trce from file 'xo2c7000.nph' in environment: C:/lscc/diamond/2.2/ispfpga.
Package Status: Final Version 1.36
Performance Hardware Data Status: Final) Version 23.4
Setup and Hold Report
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Lattice TRACE Report - Setup, Version Diamond Version 2.2.0.101
Fri Jun 21 15:18:16 2013
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
Report Information
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Command line: trce -v 10 -gt -sethld -sp 6 -sphld m -o prj_diamond_ver0_prj_diamond_ver0.twr prj_diamond_ver0_prj_diamond_ver0.ncd prj_diamond_ver0_prj_diamond_ver0.prf
Design file: prj_diamond_ver0_prj_diamond_ver0.ncd
Preference file: prj_diamond_ver0_prj_diamond_ver0.prf
Device,speed: LCMXO2-7000HC,6
Report level: verbose report, limited to 10 items per preference
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Preference Summary
FREQUENCY NET "clk_i_c" 25.000000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
Report: 47.624MHz is the maximum frequency for this preference.
FREQUENCY NET "sdram.sdr_clk_c_c" 100.000000 MHz (156 errors)
4096 items scored, 156 timing errors detected.
Warning: 90.794MHz is the maximum frequency for this preference.
FREQUENCY NET "sdram/sdr_clk_io" 100.000000 MHz (0 errors) 0 items scored, 0 timing errors detected.
Report: 150.015MHz is the maximum frequency for this preference.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
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================================================================================
Preference: FREQUENCY NET "clk_i_c" 25.000000 MHz ;
4096 items scored, 0 timing errors detected.
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Passed: The following path meets requirements by 19.002ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q LM32/cpu/load_x (from clk_i_c +)
Destination: FF Data in LM32/cpu/mc_arithmetic/b[11] (to clk_i_c +)
FF LM32/cpu/mc_arithmetic/b[10]
Delay: 20.815ns (19.4% logic, 80.6% route), 10 logic levels.
Constraint Details:
20.815ns physical path delay LM32/cpu/SLICE_925 to LM32/cpu/SLICE_953 meets
40.000ns delay constraint less
-0.034ns skew and
0.217ns CE_SET requirement (totaling 39.817ns) by 19.002ns
Physical Path Details:
Data path LM32/cpu/SLICE_925 to LM32/cpu/SLICE_953:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 R24C25A.CLK to R24C25A.Q0 LM32/cpu/SLICE_925 (from clk_i_c)
ROUTE 6 2.877 R24C25A.Q0 to R15C19D.C1 LM32/cpu/load_x
CTOF_DEL --- 0.408 R15C19D.C1 to R15C19D.F1 LM32/cpu/SLICE_1235
ROUTE 1 1.045 R15C19D.F1 to R16C18C.B1 LM32/cpu/decoder/stall_m_0_o2_1
CTOF_DEL --- 0.408 R16C18C.B1 to R16C18C.F1 LM32/cpu/SLICE_2173
ROUTE 8 0.501 R16C18C.F1 to R16C19B.D1 LM32/cpu/N_3786
CTOF_DEL --- 0.408 R16C19B.D1 to R16C19B.F1 LM32/cpu/SLICE_2172
ROUTE 6 0.774 R16C19B.F1 to R16C20D.A1 LM32/cpu/stall_m
CTOF_DEL --- 0.408 R16C20D.A1 to R16C20D.F1 LM32/cpu/SLICE_2037
ROUTE 11 2.229 R16C20D.F1 to R18C24C.C1 LM32/cpu/valid_m_2
CTOF_DEL --- 0.408 R18C24C.C1 to R18C24C.F1 LM32/cpu/SLICE_1224
ROUTE 41 2.291 R18C24C.F1 to R15C23C.B0 LM32/cpu/raw_x_1
CTOF_DEL --- 0.408 R15C23C.B0 to R15C23C.F0 LM32/cpu/SLICE_2185
ROUTE 1 2.079 R15C23C.F0 to R22C21C.C1 LM32/cpu/load_store_unit/un1_read_enable_0_d_3
CTOF_DEL --- 0.408 R22C21C.C1 to R22C21C.F1 LM32/cpu/SLICE_1234
ROUTE 3 0.624 R22C21C.F1 to R23C21C.C1 LM32/cpu/interlock4
CTOF_DEL --- 0.408 R23C21C.C1 to R23C21C.F1 LM32/cpu/SLICE_1897
ROUTE 8 1.531 R23C21C.F1 to R21C20A.B0 LM32/cpu/stall_d
CTOF_DEL --- 0.408 R21C20A.B0 to R21C20A.F0 LM32/cpu/mc_arithmetic/SLICE_2342
ROUTE 16 2.825 R21C20A.F0 to R17C32D.CE LM32/cpu/mc_arithmetic/b_0_sqmuxa (to clk_i_c)
--------
20.815 (19.4% logic, 80.6% route), 10 logic levels.
Clock Skew Details:
Source Clock Path clk_i to LM32/cpu/SLICE_925:
Name Fanout Delay (ns) Site Resource
ROUTE 999 3.487 3.PADDI to R24C25A.CLK clk_i_c
--------
3.487 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clk_i to LM32/cpu/SLICE_953:
Name Fanout Delay (ns) Site Resource
ROUTE 999 3.521 3.PADDI to R17C32D.CLK clk_i_c
--------
3.521 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 19.002ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q LM32/cpu/load_x (from clk_i_c +)
Destination: FF Data in LM32/cpu/mc_arithmetic/b[31] (to clk_i_c +)
FF LM32/cpu/mc_arithmetic/b[30]
Delay: 20.815ns (19.4% logic, 80.6% route), 10 logic levels.
Constraint Details:
20.815ns physical path delay LM32/cpu/SLICE_925 to LM32/cpu/SLICE_963 meets
40.000ns delay constraint less
-0.034ns skew and
0.217ns CE_SET requirement (totaling 39.817ns) by 19.002ns
Physical Path Details:
Data path LM32/cpu/SLICE_925 to LM32/cpu/SLICE_963:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 R24C25A.CLK to R24C25A.Q0 LM32/cpu/SLICE_925 (from clk_i_c)
ROUTE 6 2.877 R24C25A.Q0 to R15C19D.C1 LM32/cpu/load_x
CTOF_DEL --- 0.408 R15C19D.C1 to R15C19D.F1 LM32/cpu/SLICE_1235
ROUTE 1 1.045 R15C19D.F1 to R16C18C.B1 LM32/cpu/decoder/stall_m_0_o2_1
CTOF_DEL --- 0.408 R16C18C.B1 to R16C18C.F1 LM32/cpu/SLICE_2173
ROUTE 8 0.501 R16C18C.F1 to R16C19B.D1 LM32/cpu/N_3786
CTOF_DEL --- 0.408 R16C19B.D1 to R16C19B.F1 LM32/cpu/SLICE_2172
ROUTE 6 0.774 R16C19B.F1 to R16C20D.A1 LM32/cpu/stall_m
CTOF_DEL --- 0.408 R16C20D.A1 to R16C20D.F1 LM32/cpu/SLICE_2037
ROUTE 11 2.229 R16C20D.F1 to R18C24C.C1 LM32/cpu/valid_m_2
CTOF_DEL --- 0.408 R18C24C.C1 to R18C24C.F1 LM32/cpu/SLICE_1224
ROUTE 41 2.291 R18C24C.F1 to R15C23C.B0 LM32/cpu/raw_x_1
CTOF_DEL --- 0.408 R15C23C.B0 to R15C23C.F0 LM32/cpu/SLICE_2185
ROUTE 1 2.079 R15C23C.F0 to R22C21C.C1 LM32/cpu/load_store_unit/un1_read_enable_0_d_3
CTOF_DEL --- 0.408 R22C21C.C1 to R22C21C.F1 LM32/cpu/SLICE_1234
ROUTE 3 0.624 R22C21C.F1 to R23C21C.C1 LM32/cpu/interlock4
CTOF_DEL --- 0.408 R23C21C.C1 to R23C21C.F1 LM32/cpu/SLICE_1897
ROUTE 8 1.531 R23C21C.F1 to R21C20A.B0 LM32/cpu/stall_d
CTOF_DEL --- 0.408 R21C20A.B0 to R21C20A.F0 LM32/cpu/mc_arithmetic/SLICE_2342
ROUTE 16 2.825 R21C20A.F0 to R17C32A.CE LM32/cpu/mc_arithmetic/b_0_sqmuxa (to clk_i_c)
--------
20.815 (19.4% logic, 80.6% route), 10 logic levels.
Clock Skew Details:
Source Clock Path clk_i to LM32/cpu/SLICE_925:
Name Fanout Delay (ns) Site Resource
ROUTE 999 3.487 3.PADDI to R24C25A.CLK clk_i_c
--------
3.487 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clk_i to LM32/cpu/SLICE_963:
Name Fanout Delay (ns) Site Resource
ROUTE 999 3.521 3.PADDI to R17C32A.CLK clk_i_c
--------
3.521 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 19.002ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q LM32/cpu/load_x (from clk_i_c +)
Destination: FF Data in LM32/cpu/mc_arithmetic/b[15] (to clk_i_c +)
FF LM32/cpu/mc_arithmetic/b[14]
Delay: 20.815ns (19.4% logic, 80.6% route), 10 logic levels.
Constraint Details:
20.815ns physical path delay LM32/cpu/SLICE_925 to LM32/cpu/SLICE_955 meets
40.000ns delay constraint less
-0.034ns skew and
0.217ns CE_SET requirement (totaling 39.817ns) by 19.002ns
Physical Path Details:
Data path LM32/cpu/SLICE_925 to LM32/cpu/SLICE_955:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 R24C25A.CLK to R24C25A.Q0 LM32/cpu/SLICE_925 (from clk_i_c)
ROUTE 6 2.877 R24C25A.Q0 to R15C19D.C1 LM32/cpu/load_x
CTOF_DEL --- 0.408 R15C19D.C1 to R15C19D.F1 LM32/cpu/SLICE_1235
ROUTE 1 1.045 R15C19D.F1 to R16C18C.B1 LM32/cpu/decoder/stall_m_0_o2_1
CTOF_DEL --- 0.408 R16C18C.B1 to R16C18C.F1 LM32/cpu/SLICE_2173
ROUTE 8 0.501 R16C18C.F1 to R16C19B.D1 LM32/cpu/N_3786
CTOF_DEL --- 0.408 R16C19B.D1 to R16C19B.F1 LM32/cpu/SLICE_2172
ROUTE 6 0.774 R16C19B.F1 to R16C20D.A1 LM32/cpu/stall_m
CTOF_DEL --- 0.408 R16C20D.A1 to R16C20D.F1 LM32/cpu/SLICE_2037
ROUTE 11 2.229 R16C20D.F1 to R18C24C.C1 LM32/cpu/valid_m_2
CTOF_DEL --- 0.408 R18C24C.C1 to R18C24C.F1 LM32/cpu/SLICE_1224
ROUTE 41 2.291 R18C24C.F1 to R15C23C.B0 LM32/cpu/raw_x_1
CTOF_DEL --- 0.408 R15C23C.B0 to R15C23C.F0 LM32/cpu/SLICE_2185
ROUTE 1 2.079 R15C23C.F0 to R22C21C.C1 LM32/cpu/load_store_unit/un1_read_enable_0_d_3
CTOF_DEL --- 0.408 R22C21C.C1 to R22C21C.F1 LM32/cpu/SLICE_1234
ROUTE 3 0.624 R22C21C.F1 to R23C21C.C1 LM32/cpu/interlock4
CTOF_DEL --- 0.408 R23C21C.C1 to R23C21C.F1 LM32/cpu/SLICE_1897
ROUTE 8 1.531 R23C21C.F1 to R21C20A.B0 LM32/cpu/stall_d
CTOF_DEL --- 0.408 R21C20A.B0 to R21C20A.F0 LM32/cpu/mc_arithmetic/SLICE_2342
ROUTE 16 2.825 R21C20A.F0 to R17C32B.CE LM32/cpu/mc_arithmetic/b_0_sqmuxa (to clk_i_c)
--------
20.815 (19.4% logic, 80.6% route), 10 logic levels.
Clock Skew Details:
Source Clock Path clk_i to LM32/cpu/SLICE_925:
Name Fanout Delay (ns) Site Resource
ROUTE 999 3.487 3.PADDI to R24C25A.CLK clk_i_c
--------
3.487 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clk_i to LM32/cpu/SLICE_955:
Name Fanout Delay (ns) Site Resource
ROUTE 999 3.521 3.PADDI to R17C32B.CLK clk_i_c
--------
3.521 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 19.071ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q LM32/cpu/load_x (from clk_i_c +)
Destination: FF Data in LM32/cpu/mc_arithmetic/a[19] (to clk_i_c +)
FF LM32/cpu/mc_arithmetic/a[18]
Delay: 20.712ns (19.5% logic, 80.5% route), 10 logic levels.
Constraint Details:
20.712ns physical path delay LM32/cpu/SLICE_925 to LM32/cpu/mc_arithmetic/SLICE_941 meets
40.000ns delay constraint less
0.000ns skew and
0.217ns CE_SET requirement (totaling 39.783ns) by 19.071ns
Physical Path Details:
Data path LM32/cpu/SLICE_925 to LM32/cpu/mc_arithmetic/SLICE_941:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 R24C25A.CLK to R24C25A.Q0 LM32/cpu/SLICE_925 (from clk_i_c)
ROUTE 6 2.877 R24C25A.Q0 to R15C19D.C1 LM32/cpu/load_x
CTOF_DEL --- 0.408 R15C19D.C1 to R15C19D.F1 LM32/cpu/SLICE_1235
ROUTE 1 1.045 R15C19D.F1 to R16C18C.B1 LM32/cpu/decoder/stall_m_0_o2_1
CTOF_DEL --- 0.408 R16C18C.B1 to R16C18C.F1 LM32/cpu/SLICE_2173
ROUTE 8 0.501 R16C18C.F1 to R16C19B.D1 LM32/cpu/N_3786
CTOF_DEL --- 0.408 R16C19B.D1 to R16C19B.F1 LM32/cpu/SLICE_2172
ROUTE 6 0.774 R16C19B.F1 to R16C20D.A1 LM32/cpu/stall_m
CTOF_DEL --- 0.408 R16C20D.A1 to R16C20D.F1 LM32/cpu/SLICE_2037
ROUTE 11 2.229 R16C20D.F1 to R18C24C.C1 LM32/cpu/valid_m_2
CTOF_DEL --- 0.408 R18C24C.C1 to R18C24C.F1 LM32/cpu/SLICE_1224
ROUTE 41 2.291 R18C24C.F1 to R15C23C.B0 LM32/cpu/raw_x_1
CTOF_DEL --- 0.408 R15C23C.B0 to R15C23C.F0 LM32/cpu/SLICE_2185
ROUTE 1 2.079 R15C23C.F0 to R22C21C.C1 LM32/cpu/load_store_unit/un1_read_enable_0_d_3
CTOF_DEL --- 0.408 R22C21C.C1 to R22C21C.F1 LM32/cpu/SLICE_1234
ROUTE 3 0.624 R22C21C.F1 to R23C21C.C1 LM32/cpu/interlock4
CTOF_DEL --- 0.408 R23C21C.C1 to R23C21C.F1 LM32/cpu/SLICE_1897
ROUTE 8 1.531 R23C21C.F1 to R21C20A.B1 LM32/cpu/stall_d
CTOF_DEL --- 0.408 R21C20A.B1 to R21C20A.F1 LM32/cpu/mc_arithmetic/SLICE_2342
ROUTE 36 2.722 R21C20A.F1 to R23C26C.CE LM32/cpu/mc_arithmetic/N_59_i (to clk_i_c)
--------
20.712 (19.5% logic, 80.5% route), 10 logic levels.
Clock Skew Details:
Source Clock Path clk_i to LM32/cpu/SLICE_925:
Name Fanout Delay (ns) Site Resource
ROUTE 999 3.487 3.PADDI to R24C25A.CLK clk_i_c
--------
3.487 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clk_i to LM32/cpu/mc_arithmetic/SLICE_941:
Name Fanout Delay (ns) Site Resource
ROUTE 999 3.487 3.PADDI to R23C26C.CLK clk_i_c
--------
3.487 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 19.071ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q LM32/cpu/load_x (from clk_i_c +)
Destination: FF Data in LM32/cpu/mc_arithmetic/cycles[2] (to clk_i_c +)
FF LM32/cpu/mc_arithmetic/cycles[1]
Delay: 20.712ns (19.5% logic, 80.5% route), 10 logic levels.
Constraint Details:
20.712ns physical path delay LM32/cpu/SLICE_925 to LM32/cpu/mc_arithmetic/SLICE_190 meets
40.000ns delay constraint less
0.000ns skew and
0.217ns CE_SET requirement (totaling 39.783ns) by 19.071ns
Physical Path Details:
Data path LM32/cpu/SLICE_925 to LM32/cpu/mc_arithmetic/SLICE_190:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 R24C25A.CLK to R24C25A.Q0 LM32/cpu/SLICE_925 (from clk_i_c)
ROUTE 6 2.877 R24C25A.Q0 to R15C19D.C1 LM32/cpu/load_x
CTOF_DEL --- 0.408 R15C19D.C1 to R15C19D.F1 LM32/cpu/SLICE_1235
ROUTE 1 1.045 R15C19D.F1 to R16C18C.B1 LM32/cpu/decoder/stall_m_0_o2_1
CTOF_DEL --- 0.408 R16C18C.B1 to R16C18C.F1 LM32/cpu/SLICE_2173
ROUTE 8 0.501 R16C18C.F1 to R16C19B.D1 LM32/cpu/N_3786
CTOF_DEL --- 0.408 R16C19B.D1 to R16C19B.F1 LM32/cpu/SLICE_2172
ROUTE 6 0.774 R16C19B.F1 to R16C20D.A1 LM32/cpu/stall_m
CTOF_DEL --- 0.408 R16C20D.A1 to R16C20D.F1 LM32/cpu/SLICE_2037
ROUTE 11 2.229 R16C20D.F1 to R18C24C.C1 LM32/cpu/valid_m_2
CTOF_DEL --- 0.408 R18C24C.C1 to R18C24C.F1 LM32/cpu/SLICE_1224
ROUTE 41 2.291 R18C24C.F1 to R15C23C.B0 LM32/cpu/raw_x_1
CTOF_DEL --- 0.408 R15C23C.B0 to R15C23C.F0 LM32/cpu/SLICE_2185
ROUTE 1 2.079 R15C23C.F0 to R22C21C.C1 LM32/cpu/load_store_unit/un1_read_enable_0_d_3
CTOF_DEL --- 0.408 R22C21C.C1 to R22C21C.F1 LM32/cpu/SLICE_1234
ROUTE 3 0.624 R22C21C.F1 to R23C21C.C1 LM32/cpu/interlock4
CTOF_DEL --- 0.408 R23C21C.C1 to R23C21C.F1 LM32/cpu/SLICE_1897
ROUTE 8 1.531 R23C21C.F1 to R21C20A.B1 LM32/cpu/stall_d
CTOF_DEL --- 0.408 R21C20A.B1 to R21C20A.F1 LM32/cpu/mc_arithmetic/SLICE_2342
ROUTE 36 2.722 R21C20A.F1 to R24C30B.CE LM32/cpu/mc_arithmetic/N_59_i (to clk_i_c)
--------
20.712 (19.5% logic, 80.5% route), 10 logic levels.
Clock Skew Details:
Source Clock Path clk_i to LM32/cpu/SLICE_925:
Name Fanout Delay (ns) Site Resource
ROUTE 999 3.487 3.PADDI to R24C25A.CLK clk_i_c
--------
3.487 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clk_i to LM32/cpu/mc_arithmetic/SLICE_190:
Name Fanout Delay (ns) Site Resource
ROUTE 999 3.487 3.PADDI to R24C30B.CLK clk_i_c
--------
3.487 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 19.071ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q LM32/cpu/load_x (from clk_i_c +)
Destination: FF Data in LM32/cpu/mc_arithmetic/p[29] (to clk_i_c +)
FF LM32/cpu/mc_arithmetic/p[28]
Delay: 20.712ns (19.5% logic, 80.5% route), 10 logic levels.
Constraint Details:
20.712ns physical path delay LM32/cpu/SLICE_925 to LM32/cpu/mc_arithmetic/SLICE_978 meets
40.000ns delay constraint less
0.000ns skew and
0.217ns CE_SET requirement (totaling 39.783ns) by 19.071ns
Physical Path Details:
Data path LM32/cpu/SLICE_925 to LM32/cpu/mc_arithmetic/SLICE_978:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 R24C25A.CLK to R24C25A.Q0 LM32/cpu/SLICE_925 (from clk_i_c)
ROUTE 6 2.877 R24C25A.Q0 to R15C19D.C1 LM32/cpu/load_x
CTOF_DEL --- 0.408 R15C19D.C1 to R15C19D.F1 LM32/cpu/SLICE_1235
ROUTE 1 1.045 R15C19D.F1 to R16C18C.B1 LM32/cpu/decoder/stall_m_0_o2_1
CTOF_DEL --- 0.408 R16C18C.B1 to R16C18C.F1 LM32/cpu/SLICE_2173
ROUTE 8 0.501 R16C18C.F1 to R16C19B.D1 LM32/cpu/N_3786
CTOF_DEL --- 0.408 R16C19B.D1 to R16C19B.F1 LM32/cpu/SLICE_2172
ROUTE 6 0.774 R16C19B.F1 to R16C20D.A1 LM32/cpu/stall_m
CTOF_DEL --- 0.408 R16C20D.A1 to R16C20D.F1 LM32/cpu/SLICE_2037
ROUTE 11 2.229 R16C20D.F1 to R18C24C.C1 LM32/cpu/valid_m_2
CTOF_DEL --- 0.408 R18C24C.C1 to R18C24C.F1 LM32/cpu/SLICE_1224
ROUTE 41 2.291 R18C24C.F1 to R15C23C.B0 LM32/cpu/raw_x_1
CTOF_DEL --- 0.408 R15C23C.B0 to R15C23C.F0 LM32/cpu/SLICE_2185
ROUTE 1 2.079 R15C23C.F0 to R22C21C.C1 LM32/cpu/load_store_unit/un1_read_enable_0_d_3
CTOF_DEL --- 0.408 R22C21C.C1 to R22C21C.F1 LM32/cpu/SLICE_1234
ROUTE 3 0.624 R22C21C.F1 to R23C21C.C1 LM32/cpu/interlock4
CTOF_DEL --- 0.408 R23C21C.C1 to R23C21C.F1 LM32/cpu/SLICE_1897
ROUTE 8 1.531 R23C21C.F1 to R21C20A.B1 LM32/cpu/stall_d
CTOF_DEL --- 0.408 R21C20A.B1 to R21C20A.F1 LM32/cpu/mc_arithmetic/SLICE_2342
ROUTE 36 2.722 R21C20A.F1 to R22C34A.CE LM32/cpu/mc_arithmetic/N_59_i (to clk_i_c)
--------
20.712 (19.5% logic, 80.5% route), 10 logic levels.
Clock Skew Details:
Source Clock Path clk_i to LM32/cpu/SLICE_925:
Name Fanout Delay (ns) Site Resource
ROUTE 999 3.487 3.PADDI to R24C25A.CLK clk_i_c
--------
3.487 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clk_i to LM32/cpu/mc_arithmetic/SLICE_978:
Name Fanout Delay (ns) Site Resource
ROUTE 999 3.487 3.PADDI to R22C34A.CLK clk_i_c
--------
3.487 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 19.071ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q LM32/cpu/load_x (from clk_i_c +)
Destination: FF Data in LM32/cpu/mc_arithmetic/p[3] (to clk_i_c +)
FF LM32/cpu/mc_arithmetic/p[2]
Delay: 20.712ns (19.5% logic, 80.5% route), 10 logic levels.
Constraint Details:
20.712ns physical path delay LM32/cpu/SLICE_925 to LM32/cpu/mc_arithmetic/SLICE_965 meets
40.000ns delay constraint less
0.000ns skew and
0.217ns CE_SET requirement (totaling 39.783ns) by 19.071ns
Physical Path Details:
Data path LM32/cpu/SLICE_925 to LM32/cpu/mc_arithmetic/SLICE_965:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 R24C25A.CLK to R24C25A.Q0 LM32/cpu/SLICE_925 (from clk_i_c)
ROUTE 6 2.877 R24C25A.Q0 to R15C19D.C1 LM32/cpu/load_x
CTOF_DEL --- 0.408 R15C19D.C1 to R15C19D.F1 LM32/cpu/SLICE_1235
ROUTE 1 1.045 R15C19D.F1 to R16C18C.B1 LM32/cpu/decoder/stall_m_0_o2_1
CTOF_DEL --- 0.408 R16C18C.B1 to R16C18C.F1 LM32/cpu/SLICE_2173
ROUTE 8 0.501 R16C18C.F1 to R16C19B.D1 LM32/cpu/N_3786
CTOF_DEL --- 0.408 R16C19B.D1 to R16C19B.F1 LM32/cpu/SLICE_2172
ROUTE 6 0.774 R16C19B.F1 to R16C20D.A1 LM32/cpu/stall_m
CTOF_DEL --- 0.408 R16C20D.A1 to R16C20D.F1 LM32/cpu/SLICE_2037
ROUTE 11 2.229 R16C20D.F1 to R18C24C.C1 LM32/cpu/valid_m_2
CTOF_DEL --- 0.408 R18C24C.C1 to R18C24C.F1 LM32/cpu/SLICE_1224
ROUTE 41 2.291 R18C24C.F1 to R15C23C.B0 LM32/cpu/raw_x_1
CTOF_DEL --- 0.408 R15C23C.B0 to R15C23C.F0 LM32/cpu/SLICE_2185
ROUTE 1 2.079 R15C23C.F0 to R22C21C.C1 LM32/cpu/load_store_unit/un1_read_enable_0_d_3
CTOF_DEL --- 0.408 R22C21C.C1 to R22C21C.F1 LM32/cpu/SLICE_1234
ROUTE 3 0.624 R22C21C.F1 to R23C21C.C1 LM32/cpu/interlock4
CTOF_DEL --- 0.408 R23C21C.C1 to R23C21C.F1 LM32/cpu/SLICE_1897
ROUTE 8 1.531 R23C21C.F1 to R21C20A.B1 LM32/cpu/stall_d
CTOF_DEL --- 0.408 R21C20A.B1 to R21C20A.F1 LM32/cpu/mc_arithmetic/SLICE_2342
ROUTE 36 2.722 R21C20A.F1 to R24C31B.CE LM32/cpu/mc_arithmetic/N_59_i (to clk_i_c)
--------
20.712 (19.5% logic, 80.5% route), 10 logic levels.
Clock Skew Details:
Source Clock Path clk_i to LM32/cpu/SLICE_925:
Name Fanout Delay (ns) Site Resource
ROUTE 999 3.487 3.PADDI to R24C25A.CLK clk_i_c
--------
3.487 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clk_i to LM32/cpu/mc_arithmetic/SLICE_965:
Name Fanout Delay (ns) Site Resource
ROUTE 999 3.487 3.PADDI to R24C31B.CLK clk_i_c
--------
3.487 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 19.071ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q LM32/cpu/load_x (from clk_i_c +)
Destination: FF Data in LM32/cpu/mc_arithmetic/a[27] (to clk_i_c +)
FF LM32/cpu/mc_arithmetic/a[26]
Delay: 20.712ns (19.5% logic, 80.5% route), 10 logic levels.
Constraint Details:
20.712ns physical path delay LM32/cpu/SLICE_925 to LM32/cpu/mc_arithmetic/SLICE_945 meets
40.000ns delay constraint less
0.000ns skew and
0.217ns CE_SET requirement (totaling 39.783ns) by 19.071ns
Physical Path Details:
Data path LM32/cpu/SLICE_925 to LM32/cpu/mc_arithmetic/SLICE_945:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 R24C25A.CLK to R24C25A.Q0 LM32/cpu/SLICE_925 (from clk_i_c)
ROUTE 6 2.877 R24C25A.Q0 to R15C19D.C1 LM32/cpu/load_x
CTOF_DEL --- 0.408 R15C19D.C1 to R15C19D.F1 LM32/cpu/SLICE_1235
ROUTE 1 1.045 R15C19D.F1 to R16C18C.B1 LM32/cpu/decoder/stall_m_0_o2_1
CTOF_DEL --- 0.408 R16C18C.B1 to R16C18C.F1 LM32/cpu/SLICE_2173
ROUTE 8 0.501 R16C18C.F1 to R16C19B.D1 LM32/cpu/N_3786
CTOF_DEL --- 0.408 R16C19B.D1 to R16C19B.F1 LM32/cpu/SLICE_2172
ROUTE 6 0.774 R16C19B.F1 to R16C20D.A1 LM32/cpu/stall_m
CTOF_DEL --- 0.408 R16C20D.A1 to R16C20D.F1 LM32/cpu/SLICE_2037
ROUTE 11 2.229 R16C20D.F1 to R18C24C.C1 LM32/cpu/valid_m_2
CTOF_DEL --- 0.408 R18C24C.C1 to R18C24C.F1 LM32/cpu/SLICE_1224
ROUTE 41 2.291 R18C24C.F1 to R15C23C.B0 LM32/cpu/raw_x_1
CTOF_DEL --- 0.408 R15C23C.B0 to R15C23C.F0 LM32/cpu/SLICE_2185
ROUTE 1 2.079 R15C23C.F0 to R22C21C.C1 LM32/cpu/load_store_unit/un1_read_enable_0_d_3
CTOF_DEL --- 0.408 R22C21C.C1 to R22C21C.F1 LM32/cpu/SLICE_1234
ROUTE 3 0.624 R22C21C.F1 to R23C21C.C1 LM32/cpu/interlock4
CTOF_DEL --- 0.408 R23C21C.C1 to R23C21C.F1 LM32/cpu/SLICE_1897
ROUTE 8 1.531 R23C21C.F1 to R21C20A.B1 LM32/cpu/stall_d
CTOF_DEL --- 0.408 R21C20A.B1 to R21C20A.F1 LM32/cpu/mc_arithmetic/SLICE_2342
ROUTE 36 2.722 R21C20A.F1 to R22C28B.CE LM32/cpu/mc_arithmetic/N_59_i (to clk_i_c)
--------
20.712 (19.5% logic, 80.5% route), 10 logic levels.
Clock Skew Details:
Source Clock Path clk_i to LM32/cpu/SLICE_925:
Name Fanout Delay (ns) Site Resource
ROUTE 999 3.487 3.PADDI to R24C25A.CLK clk_i_c
--------
3.487 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clk_i to LM32/cpu/mc_arithmetic/SLICE_945:
Name Fanout Delay (ns) Site Resource
ROUTE 999 3.487 3.PADDI to R22C28B.CLK clk_i_c
--------
3.487 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 19.071ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q LM32/cpu/load_x (from clk_i_c +)
Destination: FF Data in LM32/cpu/mc_arithmetic/p[9] (to clk_i_c +)
FF LM32/cpu/mc_arithmetic/p[8]
Delay: 20.712ns (19.5% logic, 80.5% route), 10 logic levels.
Constraint Details:
20.712ns physical path delay LM32/cpu/SLICE_925 to LM32/cpu/mc_arithmetic/SLICE_968 meets
40.000ns delay constraint less
0.000ns skew and
0.217ns CE_SET requirement (totaling 39.783ns) by 19.071ns
Physical Path Details:
Data path LM32/cpu/SLICE_925 to LM32/cpu/mc_arithmetic/SLICE_968:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 R24C25A.CLK to R24C25A.Q0 LM32/cpu/SLICE_925 (from clk_i_c)
ROUTE 6 2.877 R24C25A.Q0 to R15C19D.C1 LM32/cpu/load_x
CTOF_DEL --- 0.408 R15C19D.C1 to R15C19D.F1 LM32/cpu/SLICE_1235
ROUTE 1 1.045 R15C19D.F1 to R16C18C.B1 LM32/cpu/decoder/stall_m_0_o2_1
CTOF_DEL --- 0.408 R16C18C.B1 to R16C18C.F1 LM32/cpu/SLICE_2173
ROUTE 8 0.501 R16C18C.F1 to R16C19B.D1 LM32/cpu/N_3786
CTOF_DEL --- 0.408 R16C19B.D1 to R16C19B.F1 LM32/cpu/SLICE_2172
ROUTE 6 0.774 R16C19B.F1 to R16C20D.A1 LM32/cpu/stall_m
CTOF_DEL --- 0.408 R16C20D.A1 to R16C20D.F1 LM32/cpu/SLICE_2037
ROUTE 11 2.229 R16C20D.F1 to R18C24C.C1 LM32/cpu/valid_m_2
CTOF_DEL --- 0.408 R18C24C.C1 to R18C24C.F1 LM32/cpu/SLICE_1224
ROUTE 41 2.291 R18C24C.F1 to R15C23C.B0 LM32/cpu/raw_x_1
CTOF_DEL --- 0.408 R15C23C.B0 to R15C23C.F0 LM32/cpu/SLICE_2185
ROUTE 1 2.079 R15C23C.F0 to R22C21C.C1 LM32/cpu/load_store_unit/un1_read_enable_0_d_3
CTOF_DEL --- 0.408 R22C21C.C1 to R22C21C.F1 LM32/cpu/SLICE_1234
ROUTE 3 0.624 R22C21C.F1 to R23C21C.C1 LM32/cpu/interlock4
CTOF_DEL --- 0.408 R23C21C.C1 to R23C21C.F1 LM32/cpu/SLICE_1897
ROUTE 8 1.531 R23C21C.F1 to R21C20A.B1 LM32/cpu/stall_d
CTOF_DEL --- 0.408 R21C20A.B1 to R21C20A.F1 LM32/cpu/mc_arithmetic/SLICE_2342
ROUTE 36 2.722 R21C20A.F1 to R24C32B.CE LM32/cpu/mc_arithmetic/N_59_i (to clk_i_c)
--------
20.712 (19.5% logic, 80.5% route), 10 logic levels.
Clock Skew Details:
Source Clock Path clk_i to LM32/cpu/SLICE_925:
Name Fanout Delay (ns) Site Resource
ROUTE 999 3.487 3.PADDI to R24C25A.CLK clk_i_c
--------
3.487 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clk_i to LM32/cpu/mc_arithmetic/SLICE_968:
Name Fanout Delay (ns) Site Resource
ROUTE 999 3.487 3.PADDI to R24C32B.CLK clk_i_c
--------
3.487 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 19.071ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q LM32/cpu/load_x (from clk_i_c +)
Destination: FF Data in LM32/cpu/mc_arithmetic/p[25] (to clk_i_c +)
FF LM32/cpu/mc_arithmetic/p[24]
Delay: 20.712ns (19.5% logic, 80.5% route), 10 logic levels.
Constraint Details:
20.712ns physical path delay LM32/cpu/SLICE_925 to LM32/cpu/mc_arithmetic/SLICE_976 meets
40.000ns delay constraint less
0.000ns skew and
0.217ns CE_SET requirement (totaling 39.783ns) by 19.071ns
Physical Path Details:
Data path LM32/cpu/SLICE_925 to LM32/cpu/mc_arithmetic/SLICE_976:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 R24C25A.CLK to R24C25A.Q0 LM32/cpu/SLICE_925 (from clk_i_c)
ROUTE 6 2.877 R24C25A.Q0 to R15C19D.C1 LM32/cpu/load_x
CTOF_DEL --- 0.408 R15C19D.C1 to R15C19D.F1 LM32/cpu/SLICE_1235
ROUTE 1 1.045 R15C19D.F1 to R16C18C.B1 LM32/cpu/decoder/stall_m_0_o2_1
CTOF_DEL --- 0.408 R16C18C.B1 to R16C18C.F1 LM32/cpu/SLICE_2173
ROUTE 8 0.501 R16C18C.F1 to R16C19B.D1 LM32/cpu/N_3786
CTOF_DEL --- 0.408 R16C19B.D1 to R16C19B.F1 LM32/cpu/SLICE_2172
ROUTE 6 0.774 R16C19B.F1 to R16C20D.A1 LM32/cpu/stall_m
CTOF_DEL --- 0.408 R16C20D.A1 to R16C20D.F1 LM32/cpu/SLICE_2037
ROUTE 11 2.229 R16C20D.F1 to R18C24C.C1 LM32/cpu/valid_m_2
CTOF_DEL --- 0.408 R18C24C.C1 to R18C24C.F1 LM32/cpu/SLICE_1224
ROUTE 41 2.291 R18C24C.F1 to R15C23C.B0 LM32/cpu/raw_x_1
CTOF_DEL --- 0.408 R15C23C.B0 to R15C23C.F0 LM32/cpu/SLICE_2185
ROUTE 1 2.079 R15C23C.F0 to R22C21C.C1 LM32/cpu/load_store_unit/un1_read_enable_0_d_3
CTOF_DEL --- 0.408 R22C21C.C1 to R22C21C.F1 LM32/cpu/SLICE_1234
ROUTE 3 0.624 R22C21C.F1 to R23C21C.C1 LM32/cpu/interlock4
CTOF_DEL --- 0.408 R23C21C.C1 to R23C21C.F1 LM32/cpu/SLICE_1897
ROUTE 8 1.531 R23C21C.F1 to R21C20A.B1 LM32/cpu/stall_d
CTOF_DEL --- 0.408 R21C20A.B1 to R21C20A.F1 LM32/cpu/mc_arithmetic/SLICE_2342
ROUTE 36 2.722 R21C20A.F1 to R22C34D.CE LM32/cpu/mc_arithmetic/N_59_i (to clk_i_c)
--------
20.712 (19.5% logic, 80.5% route), 10 logic levels.
Clock Skew Details:
Source Clock Path clk_i to LM32/cpu/SLICE_925:
Name Fanout Delay (ns) Site Resource
ROUTE 999 3.487 3.PADDI to R24C25A.CLK clk_i_c
--------
3.487 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path clk_i to LM32/cpu/mc_arithmetic/SLICE_976:
Name Fanout Delay (ns) Site Resource
ROUTE 999 3.487 3.PADDI to R22C34D.CLK clk_i_c
--------
3.487 (0.0% logic, 100.0% route), 0 logic levels.
Report: 47.624MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "sdram.sdr_clk_c_c" 100.000000 MHz ;
4096 items scored, 156 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 1.014ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram/sdr_fifo_intf_uut/U1/cState_1[4] (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram_sdr_fifo_intf_uut_U2_sdr_Aio[5] (to sdram.sdr_clk_c_c +)
Delay: 11.060ns (21.8% logic, 78.2% route), 6 logic levels.
Constraint Details:
11.060ns physical path delay sdram/sdr_fifo_intf_uut/U1/SLICE_1551 to sdramsdr_A[5]_MGIOL exceeds
10.000ns delay constraint less
-0.167ns skew and
0.121ns DO_SET requirement (totaling 10.046ns) by 1.014ns
Physical Path Details:
Data path sdram/sdr_fifo_intf_uut/U1/SLICE_1551 to sdramsdr_A[5]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 R21C8C.CLK to R21C8C.Q0 sdram/sdr_fifo_intf_uut/U1/SLICE_1551 (from sdram.sdr_clk_c_c)
ROUTE 6 0.827 R21C8C.Q0 to R23C8D.B1 sdram/sdr_fifo_intf_uut/U1/cState_1[4]
CTOF_DEL --- 0.408 R23C8D.B1 to R23C8D.F1 sdram/sdr_fifo_intf_uut/U1/SLICE_2001
ROUTE 1 0.481 R23C8D.F1 to R23C8D.D0 sdram/sdr_fifo_intf_uut/U1/N_322
CTOF_DEL --- 0.408 R23C8D.D0 to R23C8D.F0 sdram/sdr_fifo_intf_uut/U1/SLICE_2001
ROUTE 7 1.057 R23C8D.F0 to R23C5C.A0 sdram/sdr_fifo_intf_uut/N_281_3
CTOF_DEL --- 0.408 R23C5C.A0 to R23C5C.F0 sdram/sdr_fifo_intf_uut/SLICE_1982
ROUTE 1 1.170 R23C5C.F0 to R21C2A.A1 sdram/sdr_fifo_intf_uut/U2/un1_sdr_WEn142
CTOF_DEL --- 0.408 R21C2A.A1 to R21C2A.F1 sdram/sdr_fifo_intf_uut/U2/SLICE_1984
ROUTE 14 0.401 R21C2A.F1 to R21C2B.C0 sdram/sdr_fifo_intf_uut/U2/sdr_BA_1_sqmuxa
CTOF_DEL --- 0.408 R21C2B.C0 to R21C2B.F0 sdram/sdr_fifo_intf_uut/U2/SLICE_2440
ROUTE 1 4.717 R21C2B.F0 to IOL_R2B.OPOS sdram.sdr_fifo_intf_uut.U2.sdr_A_6[5] (to sdram.sdr_clk_c_c)
--------
11.060 (21.8% logic, 78.2% route), 6 logic levels.
Clock Skew Details:
Source Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/sdr_fifo_intf_uut/U1/SLICE_1551:
Name Fanout Delay (ns) Site Resource
ROUTE 211 1.508 LPLL.CLKOP to R21C8C.CLK sdram.sdr_clk_c_c
--------
1.508 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdramsdr_A[5]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 211 1.675 LPLL.CLKOP to IOL_R2B.CLK sdram.sdr_clk_c_c
--------
1.675 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 0.934ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram/sdr_fifo_intf_uut/U1/cState_1[4] (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram_sdr_fifo_intf_uut_U2_sdr_Aio[9] (to sdram.sdr_clk_c_c +)
Delay: 10.980ns (21.9% logic, 78.1% route), 6 logic levels.
Constraint Details:
10.980ns physical path delay sdram/sdr_fifo_intf_uut/U1/SLICE_1551 to sdramsdr_A[9]_MGIOL exceeds
10.000ns delay constraint less
-0.167ns skew and
0.121ns DO_SET requirement (totaling 10.046ns) by 0.934ns
Physical Path Details:
Data path sdram/sdr_fifo_intf_uut/U1/SLICE_1551 to sdramsdr_A[9]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 R21C8C.CLK to R21C8C.Q0 sdram/sdr_fifo_intf_uut/U1/SLICE_1551 (from sdram.sdr_clk_c_c)
ROUTE 6 0.827 R21C8C.Q0 to R23C8D.B1 sdram/sdr_fifo_intf_uut/U1/cState_1[4]
CTOF_DEL --- 0.408 R23C8D.B1 to R23C8D.F1 sdram/sdr_fifo_intf_uut/U1/SLICE_2001
ROUTE 1 0.481 R23C8D.F1 to R23C8D.D0 sdram/sdr_fifo_intf_uut/U1/N_322
CTOF_DEL --- 0.408 R23C8D.D0 to R23C8D.F0 sdram/sdr_fifo_intf_uut/U1/SLICE_2001
ROUTE 7 1.057 R23C8D.F0 to R23C5C.A0 sdram/sdr_fifo_intf_uut/N_281_3
CTOF_DEL --- 0.408 R23C5C.A0 to R23C5C.F0 sdram/sdr_fifo_intf_uut/SLICE_1982
ROUTE 1 1.170 R23C5C.F0 to R21C2A.A1 sdram/sdr_fifo_intf_uut/U2/un1_sdr_WEn142
CTOF_DEL --- 0.408 R21C2A.A1 to R21C2A.F1 sdram/sdr_fifo_intf_uut/U2/SLICE_1984
ROUTE 14 0.596 R21C2A.F1 to R21C2C.B0 sdram/sdr_fifo_intf_uut/U2/sdr_BA_1_sqmuxa
CTOF_DEL --- 0.408 R21C2C.B0 to R21C2C.F0 sdram/sdr_fifo_intf_uut/U2/SLICE_2323
ROUTE 1 4.442 R21C2C.F0 to IOL_R5B.OPOS sdram.sdr_fifo_intf_uut.U2.sdr_A_6[9] (to sdram.sdr_clk_c_c)
--------
10.980 (21.9% logic, 78.1% route), 6 logic levels.
Clock Skew Details:
Source Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/sdr_fifo_intf_uut/U1/SLICE_1551:
Name Fanout Delay (ns) Site Resource
ROUTE 211 1.508 LPLL.CLKOP to R21C8C.CLK sdram.sdr_clk_c_c
--------
1.508 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdramsdr_A[9]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 211 1.675 LPLL.CLKOP to IOL_R5B.CLK sdram.sdr_clk_c_c
--------
1.675 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 0.924ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram/sdr_fifo_intf_uut/U1/cState_1[3] (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram_sdr_fifo_intf_uut_U2_sdr_Aio[5] (to sdram.sdr_clk_c_c +)
Delay: 10.970ns (21.9% logic, 78.1% route), 6 logic levels.
Constraint Details:
10.970ns physical path delay sdram/sdr_fifo_intf_uut/U1/SLICE_1550 to sdramsdr_A[5]_MGIOL exceeds
10.000ns delay constraint less
-0.167ns skew and
0.121ns DO_SET requirement (totaling 10.046ns) by 0.924ns
Physical Path Details:
Data path sdram/sdr_fifo_intf_uut/U1/SLICE_1550 to sdramsdr_A[5]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 R21C5C.CLK to R21C5C.Q1 sdram/sdr_fifo_intf_uut/U1/SLICE_1550 (from sdram.sdr_clk_c_c)
ROUTE 6 0.808 R21C5C.Q1 to R21C7C.A0 sdram/sdr_fifo_intf_uut/U1/cState_1[3]
CTOF_DEL --- 0.408 R21C7C.A0 to R21C7C.F0 sdram/sdr_fifo_intf_uut/U1/SLICE_2442
ROUTE 3 0.964 R21C7C.F0 to R23C5C.C1 sdram/sdr_fifo_intf_uut/un1_LOAD_MODE_REGISTER_1_i_a2_2[0]
CTOF_DEL --- 0.408 R23C5C.C1 to R23C5C.F1 sdram/sdr_fifo_intf_uut/SLICE_1982
ROUTE 7 0.503 R23C5C.F1 to R23C5C.D0 sdram/sdr_fifo_intf_uut/un1_LOAD_MODE_REGISTER_1_i_a2[0]
CTOF_DEL --- 0.408 R23C5C.D0 to R23C5C.F0 sdram/sdr_fifo_intf_uut/SLICE_1982
ROUTE 1 1.170 R23C5C.F0 to R21C2A.A1 sdram/sdr_fifo_intf_uut/U2/un1_sdr_WEn142
CTOF_DEL --- 0.408 R21C2A.A1 to R21C2A.F1 sdram/sdr_fifo_intf_uut/U2/SLICE_1984
ROUTE 14 0.401 R21C2A.F1 to R21C2B.C0 sdram/sdr_fifo_intf_uut/U2/sdr_BA_1_sqmuxa
CTOF_DEL --- 0.408 R21C2B.C0 to R21C2B.F0 sdram/sdr_fifo_intf_uut/U2/SLICE_2440
ROUTE 1 4.717 R21C2B.F0 to IOL_R2B.OPOS sdram.sdr_fifo_intf_uut.U2.sdr_A_6[5] (to sdram.sdr_clk_c_c)
--------
10.970 (21.9% logic, 78.1% route), 6 logic levels.
Clock Skew Details:
Source Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/sdr_fifo_intf_uut/U1/SLICE_1550:
Name Fanout Delay (ns) Site Resource
ROUTE 211 1.508 LPLL.CLKOP to R21C5C.CLK sdram.sdr_clk_c_c
--------
1.508 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdramsdr_A[5]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 211 1.675 LPLL.CLKOP to IOL_R2B.CLK sdram.sdr_clk_c_c
--------
1.675 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 0.915ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram/sdr_fifo_intf_uut/U1/cState_1[1] (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram_sdr_fifo_intf_uut_U2_sdr_Aio[5] (to sdram.sdr_clk_c_c +)
Delay: 10.961ns (22.0% logic, 78.0% route), 6 logic levels.
Constraint Details:
10.961ns physical path delay sdram/sdr_fifo_intf_uut/U1/SLICE_1549 to sdramsdr_A[5]_MGIOL exceeds
10.000ns delay constraint less
-0.167ns skew and
0.121ns DO_SET requirement (totaling 10.046ns) by 0.915ns
Physical Path Details:
Data path sdram/sdr_fifo_intf_uut/U1/SLICE_1549 to sdramsdr_A[5]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 R21C6A.CLK to R21C6A.Q1 sdram/sdr_fifo_intf_uut/U1/SLICE_1549 (from sdram.sdr_clk_c_c)
ROUTE 6 0.799 R21C6A.Q1 to R21C7C.B0 sdram/sdr_fifo_intf_uut/U1/cState_1[1]
CTOF_DEL --- 0.408 R21C7C.B0 to R21C7C.F0 sdram/sdr_fifo_intf_uut/U1/SLICE_2442
ROUTE 3 0.964 R21C7C.F0 to R23C5C.C1 sdram/sdr_fifo_intf_uut/un1_LOAD_MODE_REGISTER_1_i_a2_2[0]
CTOF_DEL --- 0.408 R23C5C.C1 to R23C5C.F1 sdram/sdr_fifo_intf_uut/SLICE_1982
ROUTE 7 0.503 R23C5C.F1 to R23C5C.D0 sdram/sdr_fifo_intf_uut/un1_LOAD_MODE_REGISTER_1_i_a2[0]
CTOF_DEL --- 0.408 R23C5C.D0 to R23C5C.F0 sdram/sdr_fifo_intf_uut/SLICE_1982
ROUTE 1 1.170 R23C5C.F0 to R21C2A.A1 sdram/sdr_fifo_intf_uut/U2/un1_sdr_WEn142
CTOF_DEL --- 0.408 R21C2A.A1 to R21C2A.F1 sdram/sdr_fifo_intf_uut/U2/SLICE_1984
ROUTE 14 0.401 R21C2A.F1 to R21C2B.C0 sdram/sdr_fifo_intf_uut/U2/sdr_BA_1_sqmuxa
CTOF_DEL --- 0.408 R21C2B.C0 to R21C2B.F0 sdram/sdr_fifo_intf_uut/U2/SLICE_2440
ROUTE 1 4.717 R21C2B.F0 to IOL_R2B.OPOS sdram.sdr_fifo_intf_uut.U2.sdr_A_6[5] (to sdram.sdr_clk_c_c)
--------
10.961 (22.0% logic, 78.0% route), 6 logic levels.
Clock Skew Details:
Source Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/sdr_fifo_intf_uut/U1/SLICE_1549:
Name Fanout Delay (ns) Site Resource
ROUTE 211 1.508 LPLL.CLKOP to R21C6A.CLK sdram.sdr_clk_c_c
--------
1.508 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdramsdr_A[5]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 211 1.675 LPLL.CLKOP to IOL_R2B.CLK sdram.sdr_clk_c_c
--------
1.675 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 0.910ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram/sdr_fifo_intf_uut/U1/cState_1[4] (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram_sdr_fifo_intf_uut_U2_sdr_Aio[4] (to sdram.sdr_clk_c_c +)
Delay: 10.956ns (22.0% logic, 78.0% route), 6 logic levels.
Constraint Details:
10.956ns physical path delay sdram/sdr_fifo_intf_uut/U1/SLICE_1551 to sdramsdr_A[4]_MGIOL exceeds
10.000ns delay constraint less
-0.167ns skew and
0.121ns DO_SET requirement (totaling 10.046ns) by 0.910ns
Physical Path Details:
Data path sdram/sdr_fifo_intf_uut/U1/SLICE_1551 to sdramsdr_A[4]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 R21C8C.CLK to R21C8C.Q0 sdram/sdr_fifo_intf_uut/U1/SLICE_1551 (from sdram.sdr_clk_c_c)
ROUTE 6 0.827 R21C8C.Q0 to R23C8D.B1 sdram/sdr_fifo_intf_uut/U1/cState_1[4]
CTOF_DEL --- 0.408 R23C8D.B1 to R23C8D.F1 sdram/sdr_fifo_intf_uut/U1/SLICE_2001
ROUTE 1 0.481 R23C8D.F1 to R23C8D.D0 sdram/sdr_fifo_intf_uut/U1/N_322
CTOF_DEL --- 0.408 R23C8D.D0 to R23C8D.F0 sdram/sdr_fifo_intf_uut/U1/SLICE_2001
ROUTE 7 1.057 R23C8D.F0 to R23C5C.A0 sdram/sdr_fifo_intf_uut/N_281_3
CTOF_DEL --- 0.408 R23C5C.A0 to R23C5C.F0 sdram/sdr_fifo_intf_uut/SLICE_1982
ROUTE 1 1.170 R23C5C.F0 to R21C2A.A1 sdram/sdr_fifo_intf_uut/U2/un1_sdr_WEn142
CTOF_DEL --- 0.408 R21C2A.A1 to R21C2A.F1 sdram/sdr_fifo_intf_uut/U2/SLICE_1984
ROUTE 14 0.292 R21C2A.F1 to R21C2B.D1 sdram/sdr_fifo_intf_uut/U2/sdr_BA_1_sqmuxa
CTOF_DEL --- 0.408 R21C2B.D1 to R21C2B.F1 sdram/sdr_fifo_intf_uut/U2/SLICE_2440
ROUTE 1 4.722 R21C2B.F1 to IOL_R2A.OPOS sdram.sdr_fifo_intf_uut.U2.sdr_A_6[4] (to sdram.sdr_clk_c_c)
--------
10.956 (22.0% logic, 78.0% route), 6 logic levels.
Clock Skew Details:
Source Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/sdr_fifo_intf_uut/U1/SLICE_1551:
Name Fanout Delay (ns) Site Resource
ROUTE 211 1.508 LPLL.CLKOP to R21C8C.CLK sdram.sdr_clk_c_c
--------
1.508 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdramsdr_A[4]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 211 1.675 LPLL.CLKOP to IOL_R2A.CLK sdram.sdr_clk_c_c
--------
1.675 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 0.891ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram/sdr_fifo_intf_uut/U1/cState_1[2] (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram_sdr_fifo_intf_uut_U2_sdr_Aio[5] (to sdram.sdr_clk_c_c +)
Delay: 10.937ns (22.0% logic, 78.0% route), 6 logic levels.
Constraint Details:
10.937ns physical path delay sdram/sdr_fifo_intf_uut/U1/SLICE_1550 to sdramsdr_A[5]_MGIOL exceeds
10.000ns delay constraint less
-0.167ns skew and
0.121ns DO_SET requirement (totaling 10.046ns) by 0.891ns
Physical Path Details:
Data path sdram/sdr_fifo_intf_uut/U1/SLICE_1550 to sdramsdr_A[5]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 R21C5C.CLK to R21C5C.Q0 sdram/sdr_fifo_intf_uut/U1/SLICE_1550 (from sdram.sdr_clk_c_c)
ROUTE 6 0.804 R21C5C.Q0 to R21C6C.B1 sdram/sdr_fifo_intf_uut/U1/cState_1[2]
CTOF_DEL --- 0.408 R21C6C.B1 to R21C6C.F1 sdram/sdr_fifo_intf_uut/U1/SLICE_2324
ROUTE 2 0.787 R21C6C.F1 to R23C6A.A1 sdram/sdr_fifo_intf_uut/U1/un1_LOAD_MODE_REGISTER_1_i_a2_2[1]
CTOF_DEL --- 0.408 R23C6A.A1 to R23C6A.F1 sdram/sdr_fifo_intf_uut/SLICE_1890
ROUTE 31 0.651 R23C6A.F1 to R23C5C.C0 sdram/sdr_fifo_intf_uut/un1_LOAD_MODE_REGISTER_1_i_a2[1]
CTOF_DEL --- 0.408 R23C5C.C0 to R23C5C.F0 sdram/sdr_fifo_intf_uut/SLICE_1982
ROUTE 1 1.170 R23C5C.F0 to R21C2A.A1 sdram/sdr_fifo_intf_uut/U2/un1_sdr_WEn142
CTOF_DEL --- 0.408 R21C2A.A1 to R21C2A.F1 sdram/sdr_fifo_intf_uut/U2/SLICE_1984
ROUTE 14 0.401 R21C2A.F1 to R21C2B.C0 sdram/sdr_fifo_intf_uut/U2/sdr_BA_1_sqmuxa
CTOF_DEL --- 0.408 R21C2B.C0 to R21C2B.F0 sdram/sdr_fifo_intf_uut/U2/SLICE_2440
ROUTE 1 4.717 R21C2B.F0 to IOL_R2B.OPOS sdram.sdr_fifo_intf_uut.U2.sdr_A_6[5] (to sdram.sdr_clk_c_c)
--------
10.937 (22.0% logic, 78.0% route), 6 logic levels.
Clock Skew Details:
Source Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/sdr_fifo_intf_uut/U1/SLICE_1550:
Name Fanout Delay (ns) Site Resource
ROUTE 211 1.508 LPLL.CLKOP to R21C5C.CLK sdram.sdr_clk_c_c
--------
1.508 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdramsdr_A[5]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 211 1.675 LPLL.CLKOP to IOL_R2B.CLK sdram.sdr_clk_c_c
--------
1.675 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 0.885ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram/sdr_fifo_intf_uut/U1/cState_1[6] (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram_sdr_fifo_intf_uut_U2_sdr_Aio[5] (to sdram.sdr_clk_c_c +)
Delay: 10.931ns (22.0% logic, 78.0% route), 6 logic levels.
Constraint Details:
10.931ns physical path delay sdram/sdr_fifo_intf_uut/U1/SLICE_1551 to sdramsdr_A[5]_MGIOL exceeds
10.000ns delay constraint less
-0.167ns skew and
0.121ns DO_SET requirement (totaling 10.046ns) by 0.885ns
Physical Path Details:
Data path sdram/sdr_fifo_intf_uut/U1/SLICE_1551 to sdramsdr_A[5]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 R21C8C.CLK to R21C8C.Q1 sdram/sdr_fifo_intf_uut/U1/SLICE_1551 (from sdram.sdr_clk_c_c)
ROUTE 6 0.798 R21C8C.Q1 to R21C6C.A1 sdram/sdr_fifo_intf_uut/U1/cState_1[6]
CTOF_DEL --- 0.408 R21C6C.A1 to R21C6C.F1 sdram/sdr_fifo_intf_uut/U1/SLICE_2324
ROUTE 2 0.787 R21C6C.F1 to R23C6A.A1 sdram/sdr_fifo_intf_uut/U1/un1_LOAD_MODE_REGISTER_1_i_a2_2[1]
CTOF_DEL --- 0.408 R23C6A.A1 to R23C6A.F1 sdram/sdr_fifo_intf_uut/SLICE_1890
ROUTE 31 0.651 R23C6A.F1 to R23C5C.C0 sdram/sdr_fifo_intf_uut/un1_LOAD_MODE_REGISTER_1_i_a2[1]
CTOF_DEL --- 0.408 R23C5C.C0 to R23C5C.F0 sdram/sdr_fifo_intf_uut/SLICE_1982
ROUTE 1 1.170 R23C5C.F0 to R21C2A.A1 sdram/sdr_fifo_intf_uut/U2/un1_sdr_WEn142
CTOF_DEL --- 0.408 R21C2A.A1 to R21C2A.F1 sdram/sdr_fifo_intf_uut/U2/SLICE_1984
ROUTE 14 0.401 R21C2A.F1 to R21C2B.C0 sdram/sdr_fifo_intf_uut/U2/sdr_BA_1_sqmuxa
CTOF_DEL --- 0.408 R21C2B.C0 to R21C2B.F0 sdram/sdr_fifo_intf_uut/U2/SLICE_2440
ROUTE 1 4.717 R21C2B.F0 to IOL_R2B.OPOS sdram.sdr_fifo_intf_uut.U2.sdr_A_6[5] (to sdram.sdr_clk_c_c)
--------
10.931 (22.0% logic, 78.0% route), 6 logic levels.
Clock Skew Details:
Source Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/sdr_fifo_intf_uut/U1/SLICE_1551:
Name Fanout Delay (ns) Site Resource
ROUTE 211 1.508 LPLL.CLKOP to R21C8C.CLK sdram.sdr_clk_c_c
--------
1.508 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdramsdr_A[5]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 211 1.675 LPLL.CLKOP to IOL_R2B.CLK sdram.sdr_clk_c_c
--------
1.675 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 0.844ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram/sdr_fifo_intf_uut/U1/cState_1[3] (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram_sdr_fifo_intf_uut_U2_sdr_Aio[9] (to sdram.sdr_clk_c_c +)
Delay: 10.890ns (22.1% logic, 77.9% route), 6 logic levels.
Constraint Details:
10.890ns physical path delay sdram/sdr_fifo_intf_uut/U1/SLICE_1550 to sdramsdr_A[9]_MGIOL exceeds
10.000ns delay constraint less
-0.167ns skew and
0.121ns DO_SET requirement (totaling 10.046ns) by 0.844ns
Physical Path Details:
Data path sdram/sdr_fifo_intf_uut/U1/SLICE_1550 to sdramsdr_A[9]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 R21C5C.CLK to R21C5C.Q1 sdram/sdr_fifo_intf_uut/U1/SLICE_1550 (from sdram.sdr_clk_c_c)
ROUTE 6 0.808 R21C5C.Q1 to R21C7C.A0 sdram/sdr_fifo_intf_uut/U1/cState_1[3]
CTOF_DEL --- 0.408 R21C7C.A0 to R21C7C.F0 sdram/sdr_fifo_intf_uut/U1/SLICE_2442
ROUTE 3 0.964 R21C7C.F0 to R23C5C.C1 sdram/sdr_fifo_intf_uut/un1_LOAD_MODE_REGISTER_1_i_a2_2[0]
CTOF_DEL --- 0.408 R23C5C.C1 to R23C5C.F1 sdram/sdr_fifo_intf_uut/SLICE_1982
ROUTE 7 0.503 R23C5C.F1 to R23C5C.D0 sdram/sdr_fifo_intf_uut/un1_LOAD_MODE_REGISTER_1_i_a2[0]
CTOF_DEL --- 0.408 R23C5C.D0 to R23C5C.F0 sdram/sdr_fifo_intf_uut/SLICE_1982
ROUTE 1 1.170 R23C5C.F0 to R21C2A.A1 sdram/sdr_fifo_intf_uut/U2/un1_sdr_WEn142
CTOF_DEL --- 0.408 R21C2A.A1 to R21C2A.F1 sdram/sdr_fifo_intf_uut/U2/SLICE_1984
ROUTE 14 0.596 R21C2A.F1 to R21C2C.B0 sdram/sdr_fifo_intf_uut/U2/sdr_BA_1_sqmuxa
CTOF_DEL --- 0.408 R21C2C.B0 to R21C2C.F0 sdram/sdr_fifo_intf_uut/U2/SLICE_2323
ROUTE 1 4.442 R21C2C.F0 to IOL_R5B.OPOS sdram.sdr_fifo_intf_uut.U2.sdr_A_6[9] (to sdram.sdr_clk_c_c)
--------
10.890 (22.1% logic, 77.9% route), 6 logic levels.
Clock Skew Details:
Source Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/sdr_fifo_intf_uut/U1/SLICE_1550:
Name Fanout Delay (ns) Site Resource
ROUTE 211 1.508 LPLL.CLKOP to R21C5C.CLK sdram.sdr_clk_c_c
--------
1.508 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdramsdr_A[9]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 211 1.675 LPLL.CLKOP to IOL_R5B.CLK sdram.sdr_clk_c_c
--------
1.675 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 0.835ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram/sdr_fifo_intf_uut/U1/cState_1[1] (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram_sdr_fifo_intf_uut_U2_sdr_Aio[9] (to sdram.sdr_clk_c_c +)
Delay: 10.881ns (22.1% logic, 77.9% route), 6 logic levels.
Constraint Details:
10.881ns physical path delay sdram/sdr_fifo_intf_uut/U1/SLICE_1549 to sdramsdr_A[9]_MGIOL exceeds
10.000ns delay constraint less
-0.167ns skew and
0.121ns DO_SET requirement (totaling 10.046ns) by 0.835ns
Physical Path Details:
Data path sdram/sdr_fifo_intf_uut/U1/SLICE_1549 to sdramsdr_A[9]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 R21C6A.CLK to R21C6A.Q1 sdram/sdr_fifo_intf_uut/U1/SLICE_1549 (from sdram.sdr_clk_c_c)
ROUTE 6 0.799 R21C6A.Q1 to R21C7C.B0 sdram/sdr_fifo_intf_uut/U1/cState_1[1]
CTOF_DEL --- 0.408 R21C7C.B0 to R21C7C.F0 sdram/sdr_fifo_intf_uut/U1/SLICE_2442
ROUTE 3 0.964 R21C7C.F0 to R23C5C.C1 sdram/sdr_fifo_intf_uut/un1_LOAD_MODE_REGISTER_1_i_a2_2[0]
CTOF_DEL --- 0.408 R23C5C.C1 to R23C5C.F1 sdram/sdr_fifo_intf_uut/SLICE_1982
ROUTE 7 0.503 R23C5C.F1 to R23C5C.D0 sdram/sdr_fifo_intf_uut/un1_LOAD_MODE_REGISTER_1_i_a2[0]
CTOF_DEL --- 0.408 R23C5C.D0 to R23C5C.F0 sdram/sdr_fifo_intf_uut/SLICE_1982
ROUTE 1 1.170 R23C5C.F0 to R21C2A.A1 sdram/sdr_fifo_intf_uut/U2/un1_sdr_WEn142
CTOF_DEL --- 0.408 R21C2A.A1 to R21C2A.F1 sdram/sdr_fifo_intf_uut/U2/SLICE_1984
ROUTE 14 0.596 R21C2A.F1 to R21C2C.B0 sdram/sdr_fifo_intf_uut/U2/sdr_BA_1_sqmuxa
CTOF_DEL --- 0.408 R21C2C.B0 to R21C2C.F0 sdram/sdr_fifo_intf_uut/U2/SLICE_2323
ROUTE 1 4.442 R21C2C.F0 to IOL_R5B.OPOS sdram.sdr_fifo_intf_uut.U2.sdr_A_6[9] (to sdram.sdr_clk_c_c)
--------
10.881 (22.1% logic, 77.9% route), 6 logic levels.
Clock Skew Details:
Source Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/sdr_fifo_intf_uut/U1/SLICE_1549:
Name Fanout Delay (ns) Site Resource
ROUTE 211 1.508 LPLL.CLKOP to R21C6A.CLK sdram.sdr_clk_c_c
--------
1.508 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdramsdr_A[9]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 211 1.675 LPLL.CLKOP to IOL_R5B.CLK sdram.sdr_clk_c_c
--------
1.675 (0.0% logic, 100.0% route), 0 logic levels.
Error: The following path exceeds requirements by 0.820ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram/sdr_fifo_intf_uut/U1/cState_1[3] (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram_sdr_fifo_intf_uut_U2_sdr_Aio[4] (to sdram.sdr_clk_c_c +)
Delay: 10.866ns (22.2% logic, 77.8% route), 6 logic levels.
Constraint Details:
10.866ns physical path delay sdram/sdr_fifo_intf_uut/U1/SLICE_1550 to sdramsdr_A[4]_MGIOL exceeds
10.000ns delay constraint less
-0.167ns skew and
0.121ns DO_SET requirement (totaling 10.046ns) by 0.820ns
Physical Path Details:
Data path sdram/sdr_fifo_intf_uut/U1/SLICE_1550 to sdramsdr_A[4]_MGIOL:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.367 R21C5C.CLK to R21C5C.Q1 sdram/sdr_fifo_intf_uut/U1/SLICE_1550 (from sdram.sdr_clk_c_c)
ROUTE 6 0.808 R21C5C.Q1 to R21C7C.A0 sdram/sdr_fifo_intf_uut/U1/cState_1[3]
CTOF_DEL --- 0.408 R21C7C.A0 to R21C7C.F0 sdram/sdr_fifo_intf_uut/U1/SLICE_2442
ROUTE 3 0.964 R21C7C.F0 to R23C5C.C1 sdram/sdr_fifo_intf_uut/un1_LOAD_MODE_REGISTER_1_i_a2_2[0]
CTOF_DEL --- 0.408 R23C5C.C1 to R23C5C.F1 sdram/sdr_fifo_intf_uut/SLICE_1982
ROUTE 7 0.503 R23C5C.F1 to R23C5C.D0 sdram/sdr_fifo_intf_uut/un1_LOAD_MODE_REGISTER_1_i_a2[0]
CTOF_DEL --- 0.408 R23C5C.D0 to R23C5C.F0 sdram/sdr_fifo_intf_uut/SLICE_1982
ROUTE 1 1.170 R23C5C.F0 to R21C2A.A1 sdram/sdr_fifo_intf_uut/U2/un1_sdr_WEn142
CTOF_DEL --- 0.408 R21C2A.A1 to R21C2A.F1 sdram/sdr_fifo_intf_uut/U2/SLICE_1984
ROUTE 14 0.292 R21C2A.F1 to R21C2B.D1 sdram/sdr_fifo_intf_uut/U2/sdr_BA_1_sqmuxa
CTOF_DEL --- 0.408 R21C2B.D1 to R21C2B.F1 sdram/sdr_fifo_intf_uut/U2/SLICE_2440
ROUTE 1 4.722 R21C2B.F1 to IOL_R2A.OPOS sdram.sdr_fifo_intf_uut.U2.sdr_A_6[4] (to sdram.sdr_clk_c_c)
--------
10.866 (22.2% logic, 77.8% route), 6 logic levels.
Clock Skew Details:
Source Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/sdr_fifo_intf_uut/U1/SLICE_1550:
Name Fanout Delay (ns) Site Resource
ROUTE 211 1.508 LPLL.CLKOP to R21C5C.CLK sdram.sdr_clk_c_c
--------
1.508 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdramsdr_A[4]_MGIOL:
Name Fanout Delay (ns) Site Resource
ROUTE 211 1.675 LPLL.CLKOP to IOL_R2A.CLK sdram.sdr_clk_c_c
--------
1.675 (0.0% logic, 100.0% route), 0 logic levels.
Warning: 90.794MHz is the maximum frequency for this preference.
================================================================================
Preference: FREQUENCY NET "sdram/sdr_clk_io" 100.000000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 3.334ns
The internal maximum frequency of the following component is 150.015 MHz
Logical Details: Cell type Pin name Component name
Destination: IOLOGIC CLK sdramsdr_CLK_MGIOL
Delay: 6.666ns -- based on Minimum Pulse Width
Report: 150.015MHz is the maximum frequency for this preference.
Report Summary
--------------
----------------------------------------------------------------------------
Preference | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_i_c" 25.000000 MHz ; | 25.000 MHz| 47.624 MHz| 10
| | |
FREQUENCY NET "sdram.sdr_clk_c_c" | | |
100.000000 MHz ; | 100.000 MHz| 90.794 MHz| 6 *
| | |
FREQUENCY NET "sdram/sdr_clk_io" | | |
100.000000 MHz ; | 100.000 MHz| 150.015 MHz| 0
| | |
----------------------------------------------------------------------------
1 preference(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
sdram/sdr_fifo_intf_uut/U2/sdr_BA_1_sqmu| | |
xa | 14| 109| 69.87%
| | |
sdram/sdr_fifo_intf_uut/U2/un1_sdr_WEn14| | |
2 | 1| 98| 62.82%
| | |
sdram/sdr_fifo_intf_uut/un1_LOAD_MODE_RE| | |
GISTER_1_i_a2[0] | 7| 52| 33.33%
| | |
sdram/sdr_fifo_intf_uut/un1_LOAD_MODE_RE| | |
GISTER_1_i_a2_2[0] | 3| 49| 31.41%
| | |
sdram/sdr_fifo_intf_uut/U1/un1_LOAD_MODE| | |
_REGISTER_1_i_a2_2[1] | 2| 48| 30.77%
| | |
sdram/sdr_fifo_intf_uut/un1_LOAD_MODE_RE| | |
GISTER_1_i_a2[1] | 31| 48| 30.77%
| | |
sdram/sdr_fifo_intf_uut/N_281_3 | 7| 33| 21.15%
| | |
sdram/sdr_fifo_intf_uut/U1/N_322 | 1| 29| 18.59%
| | |
sdram/sdr_fifo_intf_uut/U1/cState_1[3] | 6| 26| 16.67%
| | |
sdram.sdr_fifo_intf_uut.U2.sdr_A_6[4] | 1| 23| 14.74%
| | |
sdram.sdr_fifo_intf_uut.U2.sdr_A_6[5] | 1| 22| 14.10%
| | |
sdram/sdr_fifo_intf_uut/U1/cState_1[6] | 6| 18| 11.54%
| | |
sdram/sdr_fifo_intf_uut/U1/cState_1[4] | 6| 18| 11.54%
| | |
sdram/sdr_fifo_intf_uut/cState_1[13] | 11| 18| 11.54%
| | |
sdram/sdr_fifo_intf_uut/U2/sdr_CASn_1_sq| | |
muxa_sn | 13| 16| 10.26%
| | |
----------------------------------------------------------------------------
Clock Domains Analysis
------------------------
Found 5 clocks:
Clock Domain: clk_i_c Source: clk_i.PAD Loads: 1157
Covered under: FREQUENCY NET "clk_i_c" 25.000000 MHz ;
Data transfers from:
Clock Domain: sdram.sdr_clk_c_c Source: sdram/U1_pmi_pll/PLLInst_0.CLKOP
Covered under: FREQUENCY NET "clk_i_c" 25.000000 MHz ; Transfers: 44
Clock Domain: LM32/jtag_update Source: SLICE_2657.F0
Not reported because source and destination domains are unrelated.
Clock Domain: jtaghub16_jtck Source: xo2chub/genblk0_genblk6_jtagf_u.JTCK
Not reported because source and destination domains are unrelated.
Clock Domain: sdram.sdr_clk_c_c Source: sdram/U1_pmi_pll/PLLInst_0.CLKOP Loads: 211
Covered under: FREQUENCY NET "sdram.sdr_clk_c_c" 100.000000 MHz ;
Data transfers from:
Clock Domain: clk_i_c Source: clk_i.PAD
Covered under: FREQUENCY NET "sdram.sdr_clk_c_c" 100.000000 MHz ; Transfers: 97
Clock Domain: sdram/sdr_clk_io Source: sdram/U1_pmi_pll/PLLInst_0.CLKOS Loads: 1
No transfer within this clock domain is found
Clock Domain: LM32/jtag_update Source: SLICE_2657.F0 Loads: 1
No transfer within this clock domain is found
Clock Domain: jtaghub16_jtck Source: xo2chub/genblk0_genblk6_jtagf_u.JTCK Loads: 39
No transfer within this clock domain is found
Timing summary (Setup):
---------------
Timing errors: 156 Score: 58541
Cumulative negative slack: 58541
Constraints cover 441391 paths, 4 nets, and 20774 connections (99.3% coverage)
--------------------------------------------------------------------------------
Lattice TRACE Report - Hold, Version Diamond Version 2.2.0.101
Fri Jun 21 15:18:17 2013
Copyright (c) 1991-1994 by NeoCAD Inc. All rights reserved.
Copyright (c) 1995 AT&T Corp. All rights reserved.
Copyright (c) 1995-2001 Lucent Technologies Inc. All rights reserved.
Copyright (c) 2001 Agere Systems All rights reserved.
Copyright (c) 2002-2013 Lattice Semiconductor Corporation, All rights reserved.
Report Information
------------------
Command line: trce -v 10 -gt -sethld -sp 6 -sphld m -o prj_diamond_ver0_prj_diamond_ver0.twr prj_diamond_ver0_prj_diamond_ver0.ncd prj_diamond_ver0_prj_diamond_ver0.prf
Design file: prj_diamond_ver0_prj_diamond_ver0.ncd
Preference file: prj_diamond_ver0_prj_diamond_ver0.prf
Device,speed: LCMXO2-7000HC,m
Report level: verbose report, limited to 10 items per preference
--------------------------------------------------------------------------------
Preference Summary
FREQUENCY NET "clk_i_c" 25.000000 MHz (71 errors)
4096 items scored, 71 timing errors detected.
FREQUENCY NET "sdram.sdr_clk_c_c" 100.000000 MHz (0 errors) 4096 items scored, 0 timing errors detected.
FREQUENCY NET "sdram/sdr_clk_io" 100.000000 MHz (0 errors) 0 items scored, 0 timing errors detected.
BLOCK ASYNCPATHS
BLOCK RESETPATHS
--------------------------------------------------------------------------------
================================================================================
Preference: FREQUENCY NET "clk_i_c" 25.000000 MHz ;
4096 items scored, 71 timing errors detected.
--------------------------------------------------------------------------------
Error: The following path exceeds requirements by 0.983ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sdram/fifo_sdr2wb/fifo_pfu_0_4/RAM0 (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_sdr2wb/FF_53 (to clk_i_c +)
Delay: 0.271ns (100.0% logic, 0.0% route), 1 logic levels.
Constraint Details:
0.271ns physical path delay sdram/fifo_sdr2wb/fifo_pfu_0_4 to sdram/fifo_sdr2wb/fifo_pfu_0_4 exceeds
-0.013ns DIN_HLD and
0.000ns delay constraint less
-0.531ns skew less
-0.736ns feedback compensation requirement (totaling 1.254ns) by 0.983ns
Physical Path Details:
Data path sdram/fifo_sdr2wb/fifo_pfu_0_4 to sdram/fifo_sdr2wb/fifo_pfu_0_4:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 R21C14A.WCK to R21C14A.F0 sdram/fifo_sdr2wb/fifo_pfu_0_4 (from sdram.sdr_clk_c_c)
ROUTE 1 0.000 R21C14A.F0 to R21C14A.DI0 sdram/fifo_sdr2wb/rdataout12 (to clk_i_c)
--------
0.271 (100.0% logic, 0.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path clk_i to sdram/fifo_sdr2wb/fifo_pfu_0_4:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.409 3.PAD to 3.PADDI clk_i
ROUTE 999 0.253 3.PADDI to LPLL.CLKI clk_i_c
CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP sdram/U1_pmi_pll/PLLInst_0
ROUTE 211 0.665 LPLL.CLKOP to R21C14A.WCK sdram.sdr_clk_c_c
--------
1.327 (30.8% logic, 69.2% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP sdram/U1_pmi_pll/PLLInst_0
ROUTE 211 0.736 LPLL.CLKOP to LPLL.CLKFB sdram.sdr_clk_c_c
--------
0.736 (0.0% logic, 100.0% route), 1 logic levels.
Destination Clock Path clk_i to sdram/fifo_sdr2wb/fifo_pfu_0_4:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.409 3.PAD to 3.PADDI clk_i
ROUTE 999 1.449 3.PADDI to R21C14A.CLK clk_i_c
--------
1.858 (22.0% logic, 78.0% route), 1 logic levels.
Error: The following path exceeds requirements by 0.983ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sdram/fifo_sdr2wb/fifo_pfu_0_1/RAM0 (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_sdr2wb/FF_41 (to clk_i_c +)
Delay: 0.271ns (100.0% logic, 0.0% route), 1 logic levels.
Constraint Details:
0.271ns physical path delay sdram/fifo_sdr2wb/fifo_pfu_0_1.2 to sdram/fifo_sdr2wb/fifo_pfu_0_1.2 exceeds
-0.013ns DIN_HLD and
0.000ns delay constraint less
-0.531ns skew less
-0.736ns feedback compensation requirement (totaling 1.254ns) by 0.983ns
Physical Path Details:
Data path sdram/fifo_sdr2wb/fifo_pfu_0_1.2 to sdram/fifo_sdr2wb/fifo_pfu_0_1.2:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 R22C11A.WCK to R22C11A.F0 sdram/fifo_sdr2wb/fifo_pfu_0_1.2 (from sdram.sdr_clk_c_c)
ROUTE 1 0.000 R22C11A.F0 to R22C11A.DI0 sdram/fifo_sdr2wb/rdataout24 (to clk_i_c)
--------
0.271 (100.0% logic, 0.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path clk_i to sdram/fifo_sdr2wb/fifo_pfu_0_1.2:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.409 3.PAD to 3.PADDI clk_i
ROUTE 999 0.253 3.PADDI to LPLL.CLKI clk_i_c
CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP sdram/U1_pmi_pll/PLLInst_0
ROUTE 211 0.665 LPLL.CLKOP to R22C11A.WCK sdram.sdr_clk_c_c
--------
1.327 (30.8% logic, 69.2% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP sdram/U1_pmi_pll/PLLInst_0
ROUTE 211 0.736 LPLL.CLKOP to LPLL.CLKFB sdram.sdr_clk_c_c
--------
0.736 (0.0% logic, 100.0% route), 1 logic levels.
Destination Clock Path clk_i to sdram/fifo_sdr2wb/fifo_pfu_0_1.2:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.409 3.PAD to 3.PADDI clk_i
ROUTE 999 1.449 3.PADDI to R22C11A.CLK clk_i_c
--------
1.858 (22.0% logic, 78.0% route), 1 logic levels.
Error: The following path exceeds requirements by 0.983ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sdram/fifo_sdr2wb/fifo_pfu_0_2/RAM0 (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_sdr2wb/FF_45 (to clk_i_c +)
Delay: 0.271ns (100.0% logic, 0.0% route), 1 logic levels.
Constraint Details:
0.271ns physical path delay sdram/fifo_sdr2wb/fifo_pfu_0_2 to sdram/fifo_sdr2wb/fifo_pfu_0_2 exceeds
-0.013ns DIN_HLD and
0.000ns delay constraint less
-0.531ns skew less
-0.736ns feedback compensation requirement (totaling 1.254ns) by 0.983ns
Physical Path Details:
Data path sdram/fifo_sdr2wb/fifo_pfu_0_2 to sdram/fifo_sdr2wb/fifo_pfu_0_2:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 R21C12A.WCK to R21C12A.F0 sdram/fifo_sdr2wb/fifo_pfu_0_2 (from sdram.sdr_clk_c_c)
ROUTE 1 0.000 R21C12A.F0 to R21C12A.DI0 sdram/fifo_sdr2wb/rdataout20 (to clk_i_c)
--------
0.271 (100.0% logic, 0.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path clk_i to sdram/fifo_sdr2wb/fifo_pfu_0_2:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.409 3.PAD to 3.PADDI clk_i
ROUTE 999 0.253 3.PADDI to LPLL.CLKI clk_i_c
CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP sdram/U1_pmi_pll/PLLInst_0
ROUTE 211 0.665 LPLL.CLKOP to R21C12A.WCK sdram.sdr_clk_c_c
--------
1.327 (30.8% logic, 69.2% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP sdram/U1_pmi_pll/PLLInst_0
ROUTE 211 0.736 LPLL.CLKOP to LPLL.CLKFB sdram.sdr_clk_c_c
--------
0.736 (0.0% logic, 100.0% route), 1 logic levels.
Destination Clock Path clk_i to sdram/fifo_sdr2wb/fifo_pfu_0_2:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.409 3.PAD to 3.PADDI clk_i
ROUTE 999 1.449 3.PADDI to R21C12A.CLK clk_i_c
--------
1.858 (22.0% logic, 78.0% route), 1 logic levels.
Error: The following path exceeds requirements by 0.983ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sdram/fifo_sdr2wb/fifo_pfu_0_0/RAM0 (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_sdr2wb/FF_37 (to clk_i_c +)
Delay: 0.271ns (100.0% logic, 0.0% route), 1 logic levels.
Constraint Details:
0.271ns physical path delay sdram/fifo_sdr2wb/fifo_pfu_0_0 to sdram/fifo_sdr2wb/fifo_pfu_0_0 exceeds
-0.013ns DIN_HLD and
0.000ns delay constraint less
-0.531ns skew less
-0.736ns feedback compensation requirement (totaling 1.254ns) by 0.983ns
Physical Path Details:
Data path sdram/fifo_sdr2wb/fifo_pfu_0_0 to sdram/fifo_sdr2wb/fifo_pfu_0_0:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 R21C13A.WCK to R21C13A.F0 sdram/fifo_sdr2wb/fifo_pfu_0_0 (from sdram.sdr_clk_c_c)
ROUTE 1 0.000 R21C13A.F0 to R21C13A.DI0 sdram/fifo_sdr2wb/rdataout28 (to clk_i_c)
--------
0.271 (100.0% logic, 0.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path clk_i to sdram/fifo_sdr2wb/fifo_pfu_0_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.409 3.PAD to 3.PADDI clk_i
ROUTE 999 0.253 3.PADDI to LPLL.CLKI clk_i_c
CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP sdram/U1_pmi_pll/PLLInst_0
ROUTE 211 0.665 LPLL.CLKOP to R21C13A.WCK sdram.sdr_clk_c_c
--------
1.327 (30.8% logic, 69.2% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP sdram/U1_pmi_pll/PLLInst_0
ROUTE 211 0.736 LPLL.CLKOP to LPLL.CLKFB sdram.sdr_clk_c_c
--------
0.736 (0.0% logic, 100.0% route), 1 logic levels.
Destination Clock Path clk_i to sdram/fifo_sdr2wb/fifo_pfu_0_0:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.409 3.PAD to 3.PADDI clk_i
ROUTE 999 1.449 3.PADDI to R21C13A.CLK clk_i_c
--------
1.858 (22.0% logic, 78.0% route), 1 logic levels.
Error: The following path exceeds requirements by 0.983ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sdram/fifo_sdr2wb/fifo_pfu_0_3/RAM1 (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_sdr2wb/FF_47 (to clk_i_c +)
Delay: 0.271ns (100.0% logic, 0.0% route), 1 logic levels.
Constraint Details:
0.271ns physical path delay sdram/fifo_sdr2wb/fifo_pfu_0_3 to sdram/fifo_sdr2wb/fifo_pfu_0_3 exceeds
-0.013ns DIN_HLD and
0.000ns delay constraint less
-0.531ns skew less
-0.736ns feedback compensation requirement (totaling 1.254ns) by 0.983ns
Physical Path Details:
Data path sdram/fifo_sdr2wb/fifo_pfu_0_3 to sdram/fifo_sdr2wb/fifo_pfu_0_3:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 R21C11B.WCK to R21C11B.F0 sdram/fifo_sdr2wb/fifo_pfu_0_3 (from sdram.sdr_clk_c_c)
ROUTE 1 0.000 R21C11B.F0 to R21C11B.DI0 sdram/fifo_sdr2wb/rdataout18 (to clk_i_c)
--------
0.271 (100.0% logic, 0.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path clk_i to sdram/fifo_sdr2wb/fifo_pfu_0_3:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.409 3.PAD to 3.PADDI clk_i
ROUTE 999 0.253 3.PADDI to LPLL.CLKI clk_i_c
CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP sdram/U1_pmi_pll/PLLInst_0
ROUTE 211 0.665 LPLL.CLKOP to R21C11B.WCK sdram.sdr_clk_c_c
--------
1.327 (30.8% logic, 69.2% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP sdram/U1_pmi_pll/PLLInst_0
ROUTE 211 0.736 LPLL.CLKOP to LPLL.CLKFB sdram.sdr_clk_c_c
--------
0.736 (0.0% logic, 100.0% route), 1 logic levels.
Destination Clock Path clk_i to sdram/fifo_sdr2wb/fifo_pfu_0_3:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.409 3.PAD to 3.PADDI clk_i
ROUTE 999 1.449 3.PADDI to R21C11B.CLK clk_i_c
--------
1.858 (22.0% logic, 78.0% route), 1 logic levels.
Error: The following path exceeds requirements by 0.983ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sdram/fifo_sdr2wb/fifo_pfu_0_0/RAM1 (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_sdr2wb/FF_35 (to clk_i_c +)
Delay: 0.271ns (100.0% logic, 0.0% route), 1 logic levels.
Constraint Details:
0.271ns physical path delay sdram/fifo_sdr2wb/fifo_pfu_0_0.1 to sdram/fifo_sdr2wb/fifo_pfu_0_0.1 exceeds
-0.013ns DIN_HLD and
0.000ns delay constraint less
-0.531ns skew less
-0.736ns feedback compensation requirement (totaling 1.254ns) by 0.983ns
Physical Path Details:
Data path sdram/fifo_sdr2wb/fifo_pfu_0_0.1 to sdram/fifo_sdr2wb/fifo_pfu_0_0.1:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 R21C13B.WCK to R21C13B.F0 sdram/fifo_sdr2wb/fifo_pfu_0_0.1 (from sdram.sdr_clk_c_c)
ROUTE 1 0.000 R21C13B.F0 to R21C13B.DI0 sdram/fifo_sdr2wb/rdataout30 (to clk_i_c)
--------
0.271 (100.0% logic, 0.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path clk_i to sdram/fifo_sdr2wb/fifo_pfu_0_0.1:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.409 3.PAD to 3.PADDI clk_i
ROUTE 999 0.253 3.PADDI to LPLL.CLKI clk_i_c
CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP sdram/U1_pmi_pll/PLLInst_0
ROUTE 211 0.665 LPLL.CLKOP to R21C13B.WCK sdram.sdr_clk_c_c
--------
1.327 (30.8% logic, 69.2% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP sdram/U1_pmi_pll/PLLInst_0
ROUTE 211 0.736 LPLL.CLKOP to LPLL.CLKFB sdram.sdr_clk_c_c
--------
0.736 (0.0% logic, 100.0% route), 1 logic levels.
Destination Clock Path clk_i to sdram/fifo_sdr2wb/fifo_pfu_0_0.1:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.409 3.PAD to 3.PADDI clk_i
ROUTE 999 1.449 3.PADDI to R21C13B.CLK clk_i_c
--------
1.858 (22.0% logic, 78.0% route), 1 logic levels.
Error: The following path exceeds requirements by 0.983ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sdram/fifo_sdr2wb/fifo_pfu_0_4/RAM1 (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_sdr2wb/FF_51 (to clk_i_c +)
Delay: 0.271ns (100.0% logic, 0.0% route), 1 logic levels.
Constraint Details:
0.271ns physical path delay sdram/fifo_sdr2wb/fifo_pfu_0_4.8 to sdram/fifo_sdr2wb/fifo_pfu_0_4.8 exceeds
-0.013ns DIN_HLD and
0.000ns delay constraint less
-0.531ns skew less
-0.736ns feedback compensation requirement (totaling 1.254ns) by 0.983ns
Physical Path Details:
Data path sdram/fifo_sdr2wb/fifo_pfu_0_4.8 to sdram/fifo_sdr2wb/fifo_pfu_0_4.8:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 R21C14B.WCK to R21C14B.F0 sdram/fifo_sdr2wb/fifo_pfu_0_4.8 (from sdram.sdr_clk_c_c)
ROUTE 1 0.000 R21C14B.F0 to R21C14B.DI0 sdram/fifo_sdr2wb/rdataout14 (to clk_i_c)
--------
0.271 (100.0% logic, 0.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path clk_i to sdram/fifo_sdr2wb/fifo_pfu_0_4.8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.409 3.PAD to 3.PADDI clk_i
ROUTE 999 0.253 3.PADDI to LPLL.CLKI clk_i_c
CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP sdram/U1_pmi_pll/PLLInst_0
ROUTE 211 0.665 LPLL.CLKOP to R21C14B.WCK sdram.sdr_clk_c_c
--------
1.327 (30.8% logic, 69.2% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP sdram/U1_pmi_pll/PLLInst_0
ROUTE 211 0.736 LPLL.CLKOP to LPLL.CLKFB sdram.sdr_clk_c_c
--------
0.736 (0.0% logic, 100.0% route), 1 logic levels.
Destination Clock Path clk_i to sdram/fifo_sdr2wb/fifo_pfu_0_4.8:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.409 3.PAD to 3.PADDI clk_i
ROUTE 999 1.449 3.PADDI to R21C14B.CLK clk_i_c
--------
1.858 (22.0% logic, 78.0% route), 1 logic levels.
Error: The following path exceeds requirements by 0.983ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sdram/fifo_sdr2wb/fifo_pfu_0_2/RAM1 (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_sdr2wb/FF_43 (to clk_i_c +)
Delay: 0.271ns (100.0% logic, 0.0% route), 1 logic levels.
Constraint Details:
0.271ns physical path delay sdram/fifo_sdr2wb/fifo_pfu_0_2.5 to sdram/fifo_sdr2wb/fifo_pfu_0_2.5 exceeds
-0.013ns DIN_HLD and
0.000ns delay constraint less
-0.531ns skew less
-0.736ns feedback compensation requirement (totaling 1.254ns) by 0.983ns
Physical Path Details:
Data path sdram/fifo_sdr2wb/fifo_pfu_0_2.5 to sdram/fifo_sdr2wb/fifo_pfu_0_2.5:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 R21C12B.WCK to R21C12B.F0 sdram/fifo_sdr2wb/fifo_pfu_0_2.5 (from sdram.sdr_clk_c_c)
ROUTE 1 0.000 R21C12B.F0 to R21C12B.DI0 sdram/fifo_sdr2wb/rdataout22 (to clk_i_c)
--------
0.271 (100.0% logic, 0.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path clk_i to sdram/fifo_sdr2wb/fifo_pfu_0_2.5:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.409 3.PAD to 3.PADDI clk_i
ROUTE 999 0.253 3.PADDI to LPLL.CLKI clk_i_c
CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP sdram/U1_pmi_pll/PLLInst_0
ROUTE 211 0.665 LPLL.CLKOP to R21C12B.WCK sdram.sdr_clk_c_c
--------
1.327 (30.8% logic, 69.2% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP sdram/U1_pmi_pll/PLLInst_0
ROUTE 211 0.736 LPLL.CLKOP to LPLL.CLKFB sdram.sdr_clk_c_c
--------
0.736 (0.0% logic, 100.0% route), 1 logic levels.
Destination Clock Path clk_i to sdram/fifo_sdr2wb/fifo_pfu_0_2.5:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.409 3.PAD to 3.PADDI clk_i
ROUTE 999 1.449 3.PADDI to R21C12B.CLK clk_i_c
--------
1.858 (22.0% logic, 78.0% route), 1 logic levels.
Error: The following path exceeds requirements by 0.983ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sdram/fifo_sdr2wb/fifo_pfu_0_1/RAM1 (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_sdr2wb/FF_39 (to clk_i_c +)
Delay: 0.271ns (100.0% logic, 0.0% route), 1 logic levels.
Constraint Details:
0.271ns physical path delay sdram/fifo_sdr2wb/fifo_pfu_0_1.3 to sdram/fifo_sdr2wb/fifo_pfu_0_1.3 exceeds
-0.013ns DIN_HLD and
0.000ns delay constraint less
-0.531ns skew less
-0.736ns feedback compensation requirement (totaling 1.254ns) by 0.983ns
Physical Path Details:
Data path sdram/fifo_sdr2wb/fifo_pfu_0_1.3 to sdram/fifo_sdr2wb/fifo_pfu_0_1.3:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 R22C11B.WCK to R22C11B.F0 sdram/fifo_sdr2wb/fifo_pfu_0_1.3 (from sdram.sdr_clk_c_c)
ROUTE 1 0.000 R22C11B.F0 to R22C11B.DI0 sdram/fifo_sdr2wb/rdataout26 (to clk_i_c)
--------
0.271 (100.0% logic, 0.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path clk_i to sdram/fifo_sdr2wb/fifo_pfu_0_1.3:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.409 3.PAD to 3.PADDI clk_i
ROUTE 999 0.253 3.PADDI to LPLL.CLKI clk_i_c
CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP sdram/U1_pmi_pll/PLLInst_0
ROUTE 211 0.665 LPLL.CLKOP to R22C11B.WCK sdram.sdr_clk_c_c
--------
1.327 (30.8% logic, 69.2% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP sdram/U1_pmi_pll/PLLInst_0
ROUTE 211 0.736 LPLL.CLKOP to LPLL.CLKFB sdram.sdr_clk_c_c
--------
0.736 (0.0% logic, 100.0% route), 1 logic levels.
Destination Clock Path clk_i to sdram/fifo_sdr2wb/fifo_pfu_0_1.3:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.409 3.PAD to 3.PADDI clk_i
ROUTE 999 1.449 3.PADDI to R22C11B.CLK clk_i_c
--------
1.858 (22.0% logic, 78.0% route), 1 logic levels.
Error: The following path exceeds requirements by 0.983ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: Sync_RAM Q sdram/fifo_sdr2wb/fifo_pfu_0_7/RAM1 (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_sdr2wb/FF_63 (to clk_i_c +)
Delay: 0.271ns (100.0% logic, 0.0% route), 1 logic levels.
Constraint Details:
0.271ns physical path delay sdram/fifo_sdr2wb/fifo_pfu_0_7 to sdram/fifo_sdr2wb/fifo_pfu_0_7 exceeds
-0.013ns DIN_HLD and
0.000ns delay constraint less
-0.531ns skew less
-0.736ns feedback compensation requirement (totaling 1.254ns) by 0.983ns
Physical Path Details:
Data path sdram/fifo_sdr2wb/fifo_pfu_0_7 to sdram/fifo_sdr2wb/fifo_pfu_0_7:
Name Fanout Delay (ns) Site Resource
CLKTOF_DEL --- 0.271 R23C11B.WCK to R23C11B.F0 sdram/fifo_sdr2wb/fifo_pfu_0_7 (from sdram.sdr_clk_c_c)
ROUTE 1 0.000 R23C11B.F0 to R23C11B.DI0 sdram/fifo_sdr2wb/rdataout2 (to clk_i_c)
--------
0.271 (100.0% logic, 0.0% route), 1 logic levels.
Clock Skew Details:
Source Clock Path clk_i to sdram/fifo_sdr2wb/fifo_pfu_0_7:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.409 3.PAD to 3.PADDI clk_i
ROUTE 999 0.253 3.PADDI to LPLL.CLKI clk_i_c
CLKI2OP_DE --- 0.000 LPLL.CLKI to LPLL.CLKOP sdram/U1_pmi_pll/PLLInst_0
ROUTE 211 0.665 LPLL.CLKOP to R23C11B.WCK sdram.sdr_clk_c_c
--------
1.327 (30.8% logic, 69.2% route), 2 logic levels.
Source Clock f/b:
Name Fanout Delay (ns) Site Resource
CLKFB2OP_D --- 0.000 LPLL.CLKFB to LPLL.CLKOP sdram/U1_pmi_pll/PLLInst_0
ROUTE 211 0.736 LPLL.CLKOP to LPLL.CLKFB sdram.sdr_clk_c_c
--------
0.736 (0.0% logic, 100.0% route), 1 logic levels.
Destination Clock Path clk_i to sdram/fifo_sdr2wb/fifo_pfu_0_7:
Name Fanout Delay (ns) Site Resource
PADI_DEL --- 0.409 3.PAD to 3.PADDI clk_i
ROUTE 999 1.449 3.PADDI to R23C11B.CLK clk_i_c
--------
1.858 (22.0% logic, 78.0% route), 1 logic levels.
================================================================================
Preference: FREQUENCY NET "sdram.sdr_clk_c_c" 100.000000 MHz ;
4096 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Passed: The following path meets requirements by 0.132ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram/sdr_fifo_intf_uut/U3/regSdrDQ[27] (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_sdr2wb/fifo_pfu_0_1/RAM1 (to sdram.sdr_clk_c_c +)
FF sdram/fifo_sdr2wb/fifo_pfu_0_1/RAM1
Delay: 0.261ns (50.2% logic, 49.8% route), 2 logic levels.
Constraint Details:
0.261ns physical path delay sdram/sdr_fifo_intf_uut/U3/SLICE_2431 to sdram/fifo_sdr2wb/fifo_pfu_0_1.3 meets
0.129ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.129ns) by 0.132ns
Physical Path Details:
Data path sdram/sdr_fifo_intf_uut/U3/SLICE_2431 to sdram/fifo_sdr2wb/fifo_pfu_0_1.3:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R22C11D.CLK to R22C11D.Q1 sdram/sdr_fifo_intf_uut/U3/SLICE_2431 (from sdram.sdr_clk_c_c)
ROUTE 1 0.130 R22C11D.Q1 to R22C11C.D1 sdram/sdr2wb_data[27]
ZERO_DEL --- 0.000 R22C11C.D1 to R22C11C.WDO3 sdram/fifo_sdr2wb/fifo_pfu_0_1
ROUTE 1 0.000 R22C11C.WDO3 to R22C11B.WD1 sdram/fifo_sdr2wb/fifo_pfu_0_1/WD3_INT (to sdram.sdr_clk_c_c)
--------
0.261 (50.2% logic, 49.8% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/sdr_fifo_intf_uut/U3/SLICE_2431:
Name Fanout Delay (ns) Site Resource
ROUTE 211 0.665 LPLL.CLKOP to R22C11D.CLK sdram.sdr_clk_c_c
--------
0.665 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/fifo_sdr2wb/fifo_pfu_0_1.3:
Name Fanout Delay (ns) Site Resource
ROUTE 211 0.665 LPLL.CLKOP to R22C11B.WCK sdram.sdr_clk_c_c
--------
0.665 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.134ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram/sdr_fifo_intf_uut/U3/regSdrDQ[23] (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_sdr2wb/fifo_pfu_0_2/RAM1 (to sdram.sdr_clk_c_c +)
FF sdram/fifo_sdr2wb/fifo_pfu_0_2/RAM1
Delay: 0.263ns (49.8% logic, 50.2% route), 2 logic levels.
Constraint Details:
0.263ns physical path delay sdram/sdr_fifo_intf_uut/U3/SLICE_2438 to sdram/fifo_sdr2wb/fifo_pfu_0_2.5 meets
0.129ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.129ns) by 0.134ns
Physical Path Details:
Data path sdram/sdr_fifo_intf_uut/U3/SLICE_2438 to sdram/fifo_sdr2wb/fifo_pfu_0_2.5:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R21C11D.CLK to R21C11D.Q1 sdram/sdr_fifo_intf_uut/U3/SLICE_2438 (from sdram.sdr_clk_c_c)
ROUTE 1 0.132 R21C11D.Q1 to R21C12C.D1 sdram/sdr2wb_data[23]
ZERO_DEL --- 0.000 R21C12C.D1 to R21C12C.WDO3 sdram/fifo_sdr2wb/fifo_pfu_0_2.4
ROUTE 1 0.000 R21C12C.WDO3 to R21C12B.WD1 sdram/fifo_sdr2wb/fifo_pfu_0_2/WD3_INT (to sdram.sdr_clk_c_c)
--------
0.263 (49.8% logic, 50.2% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/sdr_fifo_intf_uut/U3/SLICE_2438:
Name Fanout Delay (ns) Site Resource
ROUTE 211 0.665 LPLL.CLKOP to R21C11D.CLK sdram.sdr_clk_c_c
--------
0.665 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/fifo_sdr2wb/fifo_pfu_0_2.5:
Name Fanout Delay (ns) Site Resource
ROUTE 211 0.665 LPLL.CLKOP to R21C12B.WCK sdram.sdr_clk_c_c
--------
0.665 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.136ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram/sdr_fifo_intf_uut/U3/regSdrDQ[22] (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_sdr2wb/fifo_pfu_0_2/RAM1 (to sdram.sdr_clk_c_c +)
FF sdram/fifo_sdr2wb/fifo_pfu_0_2/RAM1
Delay: 0.265ns (49.4% logic, 50.6% route), 2 logic levels.
Constraint Details:
0.265ns physical path delay sdram/sdr_fifo_intf_uut/U3/SLICE_2438 to sdram/fifo_sdr2wb/fifo_pfu_0_2.5 meets
0.129ns WD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.129ns) by 0.136ns
Physical Path Details:
Data path sdram/sdr_fifo_intf_uut/U3/SLICE_2438 to sdram/fifo_sdr2wb/fifo_pfu_0_2.5:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R21C11D.CLK to R21C11D.Q0 sdram/sdr_fifo_intf_uut/U3/SLICE_2438 (from sdram.sdr_clk_c_c)
ROUTE 1 0.134 R21C11D.Q0 to R21C12C.C1 sdram/sdr2wb_data[22]
ZERO_DEL --- 0.000 R21C12C.C1 to R21C12C.WDO2 sdram/fifo_sdr2wb/fifo_pfu_0_2.4
ROUTE 1 0.000 R21C12C.WDO2 to R21C12B.WD0 sdram/fifo_sdr2wb/fifo_pfu_0_2/WD2_INT (to sdram.sdr_clk_c_c)
--------
0.265 (49.4% logic, 50.6% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/sdr_fifo_intf_uut/U3/SLICE_2438:
Name Fanout Delay (ns) Site Resource
ROUTE 211 0.665 LPLL.CLKOP to R21C11D.CLK sdram.sdr_clk_c_c
--------
0.665 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/fifo_sdr2wb/fifo_pfu_0_2.5:
Name Fanout Delay (ns) Site Resource
ROUTE 211 0.665 LPLL.CLKOP to R21C12B.WCK sdram.sdr_clk_c_c
--------
0.665 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.249ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram/fifo_sdr2wb/FF_82 (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_sdr2wb/fifo_pfu_0_0/RAM1 (to sdram.sdr_clk_c_c +)
FF sdram/fifo_sdr2wb/fifo_pfu_0_0/RAM1
Delay: 0.378ns (34.7% logic, 65.3% route), 2 logic levels.
Constraint Details:
0.378ns physical path delay sdram/fifo_sdr2wb/SLICE_126 to sdram/fifo_sdr2wb/fifo_pfu_0_0.1 meets
0.129ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.129ns) by 0.249ns
Physical Path Details:
Data path sdram/fifo_sdr2wb/SLICE_126 to sdram/fifo_sdr2wb/fifo_pfu_0_0.1:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R23C13C.CLK to R23C13C.Q0 sdram/fifo_sdr2wb/SLICE_126 (from sdram.sdr_clk_c_c)
ROUTE 8 0.247 R23C13C.Q0 to R21C13C.D0 sdram/fifo_sdr2wb/wptr_3
ZERO_DEL --- 0.000 R21C13C.D0 to R21C13C.WADO3 sdram/fifo_sdr2wb/fifo_pfu_0_0.0
ROUTE 2 0.000 R21C13C.WADO3 to R21C13B.WAD3 sdram/fifo_sdr2wb/fifo_pfu_0_0/WAD3_INT (to sdram.sdr_clk_c_c)
--------
0.378 (34.7% logic, 65.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/fifo_sdr2wb/SLICE_126:
Name Fanout Delay (ns) Site Resource
ROUTE 211 0.665 LPLL.CLKOP to R23C13C.CLK sdram.sdr_clk_c_c
--------
0.665 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/fifo_sdr2wb/fifo_pfu_0_0.1:
Name Fanout Delay (ns) Site Resource
ROUTE 211 0.665 LPLL.CLKOP to R21C13B.WCK sdram.sdr_clk_c_c
--------
0.665 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.249ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram/fifo_sdr2wb/FF_82 (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_sdr2wb/fifo_pfu_0_6/RAM0 (to sdram.sdr_clk_c_c +)
FF sdram/fifo_sdr2wb/fifo_pfu_0_6/RAM0
Delay: 0.378ns (34.7% logic, 65.3% route), 2 logic levels.
Constraint Details:
0.378ns physical path delay sdram/fifo_sdr2wb/SLICE_126 to sdram/fifo_sdr2wb/fifo_pfu_0_6 meets
0.129ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.129ns) by 0.249ns
Physical Path Details:
Data path sdram/fifo_sdr2wb/SLICE_126 to sdram/fifo_sdr2wb/fifo_pfu_0_6:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R23C13C.CLK to R23C13C.Q0 sdram/fifo_sdr2wb/SLICE_126 (from sdram.sdr_clk_c_c)
ROUTE 8 0.247 R23C13C.Q0 to R23C12C.D0 sdram/fifo_sdr2wb/wptr_3
ZERO_DEL --- 0.000 R23C12C.D0 to R23C12C.WADO3 sdram/fifo_sdr2wb/fifo_pfu_0_6.13
ROUTE 2 0.000 R23C12C.WADO3 to R23C12A.WAD3 sdram/fifo_sdr2wb/fifo_pfu_0_6/WAD3_INT (to sdram.sdr_clk_c_c)
--------
0.378 (34.7% logic, 65.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/fifo_sdr2wb/SLICE_126:
Name Fanout Delay (ns) Site Resource
ROUTE 211 0.665 LPLL.CLKOP to R23C13C.CLK sdram.sdr_clk_c_c
--------
0.665 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/fifo_sdr2wb/fifo_pfu_0_6:
Name Fanout Delay (ns) Site Resource
ROUTE 211 0.665 LPLL.CLKOP to R23C12A.WCK sdram.sdr_clk_c_c
--------
0.665 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.249ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram/fifo_sdr2wb/FF_82 (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_sdr2wb/fifo_pfu_0_0/RAM0 (to sdram.sdr_clk_c_c +)
FF sdram/fifo_sdr2wb/fifo_pfu_0_0/RAM0
Delay: 0.378ns (34.7% logic, 65.3% route), 2 logic levels.
Constraint Details:
0.378ns physical path delay sdram/fifo_sdr2wb/SLICE_126 to sdram/fifo_sdr2wb/fifo_pfu_0_0 meets
0.129ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.129ns) by 0.249ns
Physical Path Details:
Data path sdram/fifo_sdr2wb/SLICE_126 to sdram/fifo_sdr2wb/fifo_pfu_0_0:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R23C13C.CLK to R23C13C.Q0 sdram/fifo_sdr2wb/SLICE_126 (from sdram.sdr_clk_c_c)
ROUTE 8 0.247 R23C13C.Q0 to R21C13C.D0 sdram/fifo_sdr2wb/wptr_3
ZERO_DEL --- 0.000 R21C13C.D0 to R21C13C.WADO3 sdram/fifo_sdr2wb/fifo_pfu_0_0.0
ROUTE 2 0.000 R21C13C.WADO3 to R21C13A.WAD3 sdram/fifo_sdr2wb/fifo_pfu_0_0/WAD3_INT (to sdram.sdr_clk_c_c)
--------
0.378 (34.7% logic, 65.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/fifo_sdr2wb/SLICE_126:
Name Fanout Delay (ns) Site Resource
ROUTE 211 0.665 LPLL.CLKOP to R23C13C.CLK sdram.sdr_clk_c_c
--------
0.665 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/fifo_sdr2wb/fifo_pfu_0_0:
Name Fanout Delay (ns) Site Resource
ROUTE 211 0.665 LPLL.CLKOP to R21C13A.WCK sdram.sdr_clk_c_c
--------
0.665 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.249ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram/fifo_sdr2wb/FF_82 (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_sdr2wb/fifo_pfu_0_7/RAM1 (to sdram.sdr_clk_c_c +)
FF sdram/fifo_sdr2wb/fifo_pfu_0_7/RAM1
Delay: 0.378ns (34.7% logic, 65.3% route), 2 logic levels.
Constraint Details:
0.378ns physical path delay sdram/fifo_sdr2wb/SLICE_126 to sdram/fifo_sdr2wb/fifo_pfu_0_7 meets
0.129ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.129ns) by 0.249ns
Physical Path Details:
Data path sdram/fifo_sdr2wb/SLICE_126 to sdram/fifo_sdr2wb/fifo_pfu_0_7:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R23C13C.CLK to R23C13C.Q0 sdram/fifo_sdr2wb/SLICE_126 (from sdram.sdr_clk_c_c)
ROUTE 8 0.247 R23C13C.Q0 to R23C11C.D0 sdram/fifo_sdr2wb/wptr_3
ZERO_DEL --- 0.000 R23C11C.D0 to R23C11C.WADO3 sdram/fifo_sdr2wb/fifo_pfu_0_7.15
ROUTE 2 0.000 R23C11C.WADO3 to R23C11B.WAD3 sdram/fifo_sdr2wb/fifo_pfu_0_7/WAD3_INT (to sdram.sdr_clk_c_c)
--------
0.378 (34.7% logic, 65.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/fifo_sdr2wb/SLICE_126:
Name Fanout Delay (ns) Site Resource
ROUTE 211 0.665 LPLL.CLKOP to R23C13C.CLK sdram.sdr_clk_c_c
--------
0.665 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/fifo_sdr2wb/fifo_pfu_0_7:
Name Fanout Delay (ns) Site Resource
ROUTE 211 0.665 LPLL.CLKOP to R23C11B.WCK sdram.sdr_clk_c_c
--------
0.665 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.249ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram/fifo_sdr2wb/FF_82 (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_sdr2wb/fifo_pfu_0_6/RAM1 (to sdram.sdr_clk_c_c +)
FF sdram/fifo_sdr2wb/fifo_pfu_0_6/RAM1
Delay: 0.378ns (34.7% logic, 65.3% route), 2 logic levels.
Constraint Details:
0.378ns physical path delay sdram/fifo_sdr2wb/SLICE_126 to sdram/fifo_sdr2wb/fifo_pfu_0_6.12 meets
0.129ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.129ns) by 0.249ns
Physical Path Details:
Data path sdram/fifo_sdr2wb/SLICE_126 to sdram/fifo_sdr2wb/fifo_pfu_0_6.12:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R23C13C.CLK to R23C13C.Q0 sdram/fifo_sdr2wb/SLICE_126 (from sdram.sdr_clk_c_c)
ROUTE 8 0.247 R23C13C.Q0 to R23C12C.D0 sdram/fifo_sdr2wb/wptr_3
ZERO_DEL --- 0.000 R23C12C.D0 to R23C12C.WADO3 sdram/fifo_sdr2wb/fifo_pfu_0_6.13
ROUTE 2 0.000 R23C12C.WADO3 to R23C12B.WAD3 sdram/fifo_sdr2wb/fifo_pfu_0_6/WAD3_INT (to sdram.sdr_clk_c_c)
--------
0.378 (34.7% logic, 65.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/fifo_sdr2wb/SLICE_126:
Name Fanout Delay (ns) Site Resource
ROUTE 211 0.665 LPLL.CLKOP to R23C13C.CLK sdram.sdr_clk_c_c
--------
0.665 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/fifo_sdr2wb/fifo_pfu_0_6.12:
Name Fanout Delay (ns) Site Resource
ROUTE 211 0.665 LPLL.CLKOP to R23C12B.WCK sdram.sdr_clk_c_c
--------
0.665 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.249ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram/fifo_sdr2wb/FF_82 (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_sdr2wb/fifo_pfu_0_7/RAM0 (to sdram.sdr_clk_c_c +)
FF sdram/fifo_sdr2wb/fifo_pfu_0_7/RAM0
Delay: 0.378ns (34.7% logic, 65.3% route), 2 logic levels.
Constraint Details:
0.378ns physical path delay sdram/fifo_sdr2wb/SLICE_126 to sdram/fifo_sdr2wb/fifo_pfu_0_7.14 meets
0.129ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.129ns) by 0.249ns
Physical Path Details:
Data path sdram/fifo_sdr2wb/SLICE_126 to sdram/fifo_sdr2wb/fifo_pfu_0_7.14:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R23C13C.CLK to R23C13C.Q0 sdram/fifo_sdr2wb/SLICE_126 (from sdram.sdr_clk_c_c)
ROUTE 8 0.247 R23C13C.Q0 to R23C11C.D0 sdram/fifo_sdr2wb/wptr_3
ZERO_DEL --- 0.000 R23C11C.D0 to R23C11C.WADO3 sdram/fifo_sdr2wb/fifo_pfu_0_7.15
ROUTE 2 0.000 R23C11C.WADO3 to R23C11A.WAD3 sdram/fifo_sdr2wb/fifo_pfu_0_7/WAD3_INT (to sdram.sdr_clk_c_c)
--------
0.378 (34.7% logic, 65.3% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/fifo_sdr2wb/SLICE_126:
Name Fanout Delay (ns) Site Resource
ROUTE 211 0.665 LPLL.CLKOP to R23C13C.CLK sdram.sdr_clk_c_c
--------
0.665 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/fifo_sdr2wb/fifo_pfu_0_7.14:
Name Fanout Delay (ns) Site Resource
ROUTE 211 0.665 LPLL.CLKOP to R23C11A.WCK sdram.sdr_clk_c_c
--------
0.665 (0.0% logic, 100.0% route), 0 logic levels.
Passed: The following path meets requirements by 0.250ns
Logical Details: Cell type Pin type Cell/ASIC name (clock net +/-)
Source: FF Q sdram/fifo_sdr2wb/FF_83 (from sdram.sdr_clk_c_c +)
Destination: FF Data in sdram/fifo_sdr2wb/fifo_pfu_0_2/RAM0 (to sdram.sdr_clk_c_c +)
FF sdram/fifo_sdr2wb/fifo_pfu_0_2/RAM0
Delay: 0.379ns (34.6% logic, 65.4% route), 2 logic levels.
Constraint Details:
0.379ns physical path delay sdram/fifo_sdr2wb/SLICE_126 to sdram/fifo_sdr2wb/fifo_pfu_0_2 meets
0.129ns WAD_HLD and
0.000ns delay constraint less
0.000ns skew requirement (totaling 0.129ns) by 0.250ns
Physical Path Details:
Data path sdram/fifo_sdr2wb/SLICE_126 to sdram/fifo_sdr2wb/fifo_pfu_0_2:
Name Fanout Delay (ns) Site Resource
REG_DEL --- 0.131 R23C13C.CLK to R23C13C.Q1 sdram/fifo_sdr2wb/SLICE_126 (from sdram.sdr_clk_c_c)
ROUTE 8 0.248 R23C13C.Q1 to R21C12C.C0 sdram/fifo_sdr2wb/wptr_2
ZERO_DEL --- 0.000 R21C12C.C0 to R21C12C.WADO2 sdram/fifo_sdr2wb/fifo_pfu_0_2.4
ROUTE 2 0.000 R21C12C.WADO2 to R21C12A.WAD2 sdram/fifo_sdr2wb/fifo_pfu_0_2/WAD2_INT (to sdram.sdr_clk_c_c)
--------
0.379 (34.6% logic, 65.4% route), 2 logic levels.
Clock Skew Details:
Source Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/fifo_sdr2wb/SLICE_126:
Name Fanout Delay (ns) Site Resource
ROUTE 211 0.665 LPLL.CLKOP to R23C13C.CLK sdram.sdr_clk_c_c
--------
0.665 (0.0% logic, 100.0% route), 0 logic levels.
Destination Clock Path sdram/U1_pmi_pll/PLLInst_0 to sdram/fifo_sdr2wb/fifo_pfu_0_2:
Name Fanout Delay (ns) Site Resource
ROUTE 211 0.665 LPLL.CLKOP to R21C12A.WCK sdram.sdr_clk_c_c
--------
0.665 (0.0% logic, 100.0% route), 0 logic levels.
================================================================================
Preference: FREQUENCY NET "sdram/sdr_clk_io" 100.000000 MHz ;
0 items scored, 0 timing errors detected.
--------------------------------------------------------------------------------
Report Summary
--------------
----------------------------------------------------------------------------
Preference(MIN Delays) | Constraint| Actual|Levels
----------------------------------------------------------------------------
| | |
FREQUENCY NET "clk_i_c" 25.000000 MHz ; | -| -| 1 *
| | |
FREQUENCY NET "sdram.sdr_clk_c_c" | | |
100.000000 MHz ; | -| -| 2
| | |
FREQUENCY NET "sdram/sdr_clk_io" | | |
100.000000 MHz ; | -| -| 0
| | |
----------------------------------------------------------------------------
1 preference(marked by "*" above) not met.
----------------------------------------------------------------------------
Critical Nets | Loads| Errors| % of total
----------------------------------------------------------------------------
sdram/read_tmn | 22| 28| 39.44%
| | |
sdram/fifo_sdr2wb/rRst | 30| 25| 35.21%
| | |
----------------------------------------------------------------------------
Clock Domains Analysis
------------------------
Found 5 clocks:
Clock Domain: clk_i_c Source: clk_i.PAD Loads: 1157
Covered under: FREQUENCY NET "clk_i_c" 25.000000 MHz ;
Data transfers from:
Clock Domain: sdram.sdr_clk_c_c Source: sdram/U1_pmi_pll/PLLInst_0.CLKOP
Covered under: FREQUENCY NET "clk_i_c" 25.000000 MHz ; Transfers: 44
Clock Domain: LM32/jtag_update Source: SLICE_2657.F0
Not reported because source and destination domains are unrelated.
Clock Domain: jtaghub16_jtck Source: xo2chub/genblk0_genblk6_jtagf_u.JTCK
Not reported because source and destination domains are unrelated.
Clock Domain: sdram.sdr_clk_c_c Source: sdram/U1_pmi_pll/PLLInst_0.CLKOP Loads: 211
Covered under: FREQUENCY NET "sdram.sdr_clk_c_c" 100.000000 MHz ;
Data transfers from:
Clock Domain: clk_i_c Source: clk_i.PAD
Covered under: FREQUENCY NET "sdram.sdr_clk_c_c" 100.000000 MHz ; Transfers: 97
Clock Domain: sdram/sdr_clk_io Source: sdram/U1_pmi_pll/PLLInst_0.CLKOS Loads: 1
No transfer within this clock domain is found
Clock Domain: LM32/jtag_update Source: SLICE_2657.F0 Loads: 1
No transfer within this clock domain is found
Clock Domain: jtaghub16_jtck Source: xo2chub/genblk0_genblk6_jtagf_u.JTCK Loads: 39
No transfer within this clock domain is found
Timing summary (Hold):
---------------
Timing errors: 71 Score: 46648
Cumulative negative slack: 46648
Constraints cover 441391 paths, 4 nets, and 20774 connections (99.3% coverage)
Timing summary (Setup and Hold):
---------------
Timing errors: 156 (setup), 71 (hold)
Score: 58541 (setup), 46648 (hold)
Cumulative negative slack: 105189 (58541+46648)
--------------------------------------------------------------------------------
--------------------------------------------------------------------------------